1. For the hexadecimal hexadecimal main memory memory addresses 1111 111111 11,, 666666,BBBB 666666,BBBBBB, BB, show the following information, in hexadecimal format: a. Tag, Tag, Line, Line, and Wo Word values values for a directma!! directma!!ed ed cache, where where tag " #$its, line line " 1% $its, word " & $its $. Tag Tag and Word Word values values for an associative cache, where tag " && $its, word " & $its c. Tag, Tag, 'et, and and Wor Word d values for for a twoway twoway setassociat setassociative ive cache, cache, where tag tag " ( $its, set " 1) $its, word " & $its &. List List the the fol follo lowi wing ng val value ues: s: a. For the the direct direct cache cache from from the $elow Fig: address length, length, num$er num$er of addressa$le units, $loc* si+e, si+ e, num$er of $loc*s in main memory, num$er num$er of lines in cache, si+e of tag
$. For the associative cache from $elow Figure: address length, num$er of addressa$le units, $loc* si+e, si+ e, num$er of $loc*s in main memory, num$er num$er of lines in cache, si+e of tag
c. For the the twoway twoway setassociat setassociative ive cache cache exam!le exam!le of Figure Figure %.1: %.1: address address length, length, num$er of addressa$le units, $loc* si+e, num$er of $loc*s in main memory, num$er of lines in set, num$er of sets, num$er of lines in cache, si+e of tag
). -onsider -onsider a )&$it )&$it micro!roces micro!rocessor sor that has has an onchi! onchi! 16By 16Byte te fourway fourway set set associative cache. /ssume that the cache has a line si+e of four )&$it words. 0raw a $loc* diagram of this cache showing its organi+ation organi+ation and how the different address fields are used to determine a cache hitmiss. Where in the cache is the word from memory location /B-02#F# ma!!ed3 %. -onsider -onsider a machine machine with a $yte addressa$ addressa$le le main memory memory of of &16 $ytes $ytes and $loc* $loc* si+e of # $ytes. /ssume that a direct ma!!ed cache consisting of )& lines is used with this machine. a. 4ow is a 16$it 16$it memory memory address address divided divided into tag, tag, line line num$er, num$er, and $yte $yte num$er3 $. 5nto what line would $ytes with each of the following following addresses $e stored3 1 1 1 111 11 11 11 1 111 1 111 11 11 11 11
c. 'u!!ose the $yte with address 1 11 1 11 is stored in the cache. What are the addresses of the other $ytes stored along with it3 d. 4ow many total $ytes of memory can $e stored in the cache3 e. Why the tag is also stored in the cache3 . / setassociative cache has a $loc* si+e of four 16$it words and a set si+e of &. The cache can accommodate a total of %(6 words. The main memory si+e that is cachea$le is 6% 7 )& $its. 'how how the !rocessor8s addresses are inter!reted3 6. -onsider a memory system that uses a )&$it address to address at the $yte level, !lus a cache that uses a 6%$yte line si+e. a. /ssume a direct ma!!ed cache with a tag field in the address of & $its. 'how the address format and determine the following !arameters: num$er of addressa$le units, num$er of $loc*s in main memory, num$er of lines in cache, si+e of tag. $. /ssume an associative cache. 'how the address format and determine the following !arameters: num$er of addressa$le units, num$er of $loc*s in main memory, num$er of lines in cache, si+e of tag. c. /ssume a fourway setassociative cache with a tag field in the address of ( $its. 'how the address format and determine the following !arameters: num$er of addressa$le units, num$er of $loc*s in main memory, num$er of lines in set, num$er of sets in cache, num$er of lines in cache, si+e of tag. 9. -onsider a com!uter with the following characteristics: total of 1$yte of main memory; word si+e of 1 $yte; $loc* si+e of 16 $ytes; and cache si+e of 6% $ytes. a. For the main memory addresses of F1, 1&)%, and -/BB2, give the corres!onding tag, cache line address, and word offsets for a directma!!ed cache. $. ; i ? &; i@@A for = > ; ? 1; @@A aCiD > aCiD E a. 1ns; Tm > 1&ns 5f the effective access time is 1 greater than the cache access time, what is the hit ratio 4 for loo* through cache3 1. -onsider a loo* through cache with an access time of 1 ns and a hit ratio of 4 .(. 'u!!ose that we can change the cache design =si+e of cache, cache organi+ationA such
that we increase 4 to .(9, $ut increase access time to 1. ns. What conditions must $e met for this change to result in im!roved !erformance3
