8051 MICROCONTROLLER INTERRUPTS
Submitted by: Preet Komal Singh 010714 Ece-E1
8051 Interrupts As the name implies, an interrupt is some event which interrupts normal program execution. As stated earlier, program flow is always sequential, being altered only by those instructions which expressly cause program flow to deviate in some way. However, interrupts give us a mechanism to "put on hold" the normal program flow, execute a subroutine, subroutine, and then resume normal normal program flow as if we had never left it. This subroutine, called an interrupt handler, is only executed when a certain event (interrupt) occurs. The event may be one of the timers "overflowing," receiving a character via the serial port, transmitting a character via the serial port, or one of two "external events." The 8051 may be configured so that when any of these events occur the main program is temporarily suspended and control passed to a special section of code which presumably would execute some function related to the event that occurred. Once complete, control would be returned to the original program. The main program never even knows it was interrupted. The ability to interrupt normal program execution when certain events occur makes it much easier and much more efficient to handle certain conditions. If it were not for interrupts we would have to manually check in our main program whether the timers had over flown, whether we had received another character via the serial port, or if some external event had occurred. Besides making the main program ugly and hard to read, such a situation would make our program inefficient since wed be burning precious "instruction "instruction cycles" checking for events that usually don’t happen.
The 8051 provides five interrupt sources. These are listed below. 1. Timer Timer 0 (TFO) (TFO) and and timer timer 1 (TF1) (TF1) inter interrupt rupt..
2. External External hardw hardware are interr interrupts, upts, INTO and INT1. INT1.
3. Serial Serial commu communicat nication ion interr interrupt upt TI and RI RI
The Fig. shows the interrupt structure of of 8051. 8051.
Interrupt Vector Table In 8051, all interrupts are vectored interrupts and have vector locations as listed in Table 15.1 when interrupt is activated 8051 reads the address of interrupt service routine from the vector location. Interrupt
Vector location
External hardware interrupt 0 (INTO)
Timer 0 internet (TFO Overflow)
External hardware Interrupt 1 (INT1)
Timer 1 interrupt (TF1 Overflow)
Serial communication communication interrupt (Rl and Tl) (Reception/Transmission (Reception/Transmission of Serial Character)
0003H
00OBH
0013H
001BH
0023H
INTERRUPT VECTOR TABLE FOR 8051
Enabling and Disabling an Interrupt When 8051 is reset, all interrupts are disabling. These are enabled by software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled in software. Each of these interrupt sources can be individually
enabled or disabled by setting or clearing a bit in Special Function Register IE (Fig. 15.2) . IE contains also a global disable bit, EA, which disables all, interrupts at once. Note in Fig. 15.2 that bit position IE.6 is unimplemented. unimplemented. In the 8051s, bit position IE.5 is also unimplemented. unimplemented. User software should not write is to these bit positions, since they may be used in future MCS-51 products. (MSB) (LSB) EA
-
ET2
ES
Symbol
Position
Name and Signific ficance
EA
IE.7
Enable AH control bit.
ET1
EX1
ET0
EX0
Cleared by software to disable all interrupts, independent of the state of IE.4-IE.0. -
IE.6
(Reserved)
ET2
IE.5
(Reserved)
ES
IE.4
Enable Serial port control bit Set/cleared Set/cleared by software to enable/disable enable/disable interrupts from Tl or Rl flags.
ET1
IE.3
Enable Timer 1 control bit. Set/cleared Set/cleared by software to enable/disable interrupts from timer/counter 1
EX1
IE.2
Enable External interrupt 1 control bit. Set/cleared Set/cleared by software to enable/ disable interrupts from INT1.
ETO
IE.1
Enable Timer 0 control bit Set/cleared Set/cleared by software to enable/disable interrupts from timer/counter 0.
EXO
IE 0
Enable external interrupt 0 control bit. Set/cleared Set/cleared by software to enable/disable interrupts from INTO.
INTERRUPT ENABLE REGISTER
Timer Interrupts and Programming The Timer 0 and Timer 1 Interrupts are generated by TFO and TF1, which are set by a rollover in their respective respective Timer/Counter Timer/Counter registers (except see Timer 0 in Mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored. As the timer flag (TF) is set (=1) when the timer rolls over. In polling method, the TF is monitored with the instruction 'JNB TF, target address'. We have to wait until the TF is raised. The problem with this polling method is that 8051 cannot do anything else until TF is set to high. This problem can be solved using interrupt method. If the timer interrupt interrupt in the IE register is enabled, TF is set whenever the timer is rolled over and the 8051 is interrupted. Thus the 8051 can perform anything else until it is interrupted. After interruption (timer rolling over) only the 8051 remains busy in executing interrupt service routine.
Programming External Hardware Interrupts Pins, P 3.2 (pin number 12) and P 3.3 (pin number 13) in port 3 are used as external hardware interrupts INTO and INT1, respectively. The external Interrupts INTO and INT1
can each be either level-activated or transition-activated, depending on bits ITO and IT1 in Register TCON. The flags that actually generate these interrupts are bits IEO and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware. If ITx = 0, external e xternal interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for at least one machine cycle, and then hold it low for at least one machine cycle to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically automatically cleared by the CPU when the service routine is called. If the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. Then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated.
Example: Write an 8051 ALP to glow LED for a fraction of second when external interrupt INTO is activated. Solution
ORG 0000H LJMP MAIN
B
M
O R C G L R 0 P 0 1 0 . 3 0 H S ; E R T E B T I P 1 ; . 0 O R ; G 0 M 0 O 3 V 0 E H R 2 , # 0 F F H ; D J N Z B A C K
M O V I E , # 1 0 0 0 0 0 0 1 B
S E
n T d u r i n f O n N o t L E z D e r o
L o a r d e p c e o a u t n T t u r D n O e c F r F e L m E e D n R t e t c u o r u n n t t o m a ai
n S ; ;
Serial Commu nication Interru pts and Progra mming The Serial port Interrupt is generated by the logical OR of RI and TI. Neither Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine will normally have to determine whether it was RI or TI that
generated the interrupt, and the bit will have to be cleared in software. In this case, the 8051 can perform other tasks in addition to serial communic ation, i.e. sending and receiving data from serial communic ation port. We know know that that transmit interrupt (TI) flag is set
(=1)
when
the
last last bit bit of the framed
data (stop bit)
is
transmitte d.
This
indicates
that the SBUF register is ready to transmit the next byte. The receive interrupt (RI) flag is set (=1) when when the the complete fram rame of data (with stop top bit) bit) is received. RI indicates that the received byte needs eds to be picked up before
it is lost by new incoming serial data. All the above concepts are applied equally using polling or an interrupt. Only differenc e is in serving the serial communi cation needs. In polling method, the flag (TI or RI) is monitore d. The 8051 cannot do anything else until this flag
is set to high. This problem is solved using interrupt method. When 8051 has received a byte or is ready to send the next byte, the RI or TI flag respectiv ely is set. Any other work can be performe d while the serial communi cation needs are served. There is a single interrupt set aside for serial communi
cation. If IE register (IE.4) is enabled, when RI or TI is set (= 1), the 8051 is interrupt ed. When interrupt ed, the ISR written at 0023h is executed by 8051. In ISR, the TI and RI flags must be examined to check which one caused the interrupt and according to flag the
response is given.
Interru pt priority Each interrupt source can also be individuall y programm ed to one of two priority levels levels by sett settin ing g or cleari clearing ng a bit in Special Function Register IP. A lowpriority interrupt can can itse itself lf be interrupte d by a highpriority interrupt, but not by another low priority interrupt. A highpriority interrupt can’t be
interrupte d by another interrupt source.
If two requests of different priority levels are received
simultane ously, the request of higher priority level is served. If requests of the same priority level are received simultane ously, an internal polling sequence determine s which request is serviced. Thus within each priority level there is a second priority structure determine d by the polling sequence, as follows:
Note that the "priority within level" structure is only used to resolve simultane ous requests of the same priority level. The IP register contains a number of unimplem ented bits. 1P.7 and IP.6 are vacant in the 8052s, and in the 8051s
these and IP.5 are vacant. User software should not write Is to these bit positions, since they User software should not write Is to these bit positions, since they may be used in future MCS-51 products.
Nested Interru pts Consid er a case, the 8051 is executing an ISR for servicing an interrupt and another interrupt is occurred. In such a case, if the new
coming interrupt is high priority interrupt then only it can interrupt the previously occurred lowpriority interrupt. These are called nested interrupts ". Thus, in 8051 a lowpriority interrupt can be interrupte d by highpriority interrupt but not by another lowpriority interrupt. In 8051, all the interrupts are latched and kept internally. But the
lowpriority interrupt is serviced only after finishing the servicing of the highpriority interrupts.
Softwar e Triggeri ng of Interru pt Sof twa twa re triggering of the interrupts is possible in 8051. This means the interrupt can be caused by setting an interrupt flag with an instruction . For example, if the IE bit for timer 1 is set, an instruction
'SETB TFV will interrupt the 8051 and 8051 will start executing ISR. Thus, it is not needed to wait for timer 1 to roll over to have an interrupt. Since we are using instruction to create an interrupt, it is called software triggering .This is useful for testing an ISR by way of simulation .
