Conformal Ref

Encounter® Conformal® Equivalence Checking Reference Manual Conformal ASIC, Conformal Ultra, and Conformal Custom Product Version 7.2 May 2008

 1997– 2008 Cadence Design Systems, Inc. All rights reserved. Printed in the United States of America. Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA Trademarks: Trademarks and service marks of Cadence Design Systems, Inc. (Cadence) contained in this document are attributed to Cadence with the appropriate symbol. For queries regarding Cadence’s trademarks, contact the corporate legal department at the address shown above or call 800.862.4522. Open SystemC, Open SystemC Initiative, OSCI, SystemC, and SystemC Initiative are trademarks or registered trademarks of Open SystemC Initiative, Inc. in the United States and other countries and are used with permission. All other trademarks are the property of their respective holders. Restricted Print Permission: This publication is protected by copyright and any unauthorized use of this publication may violate copyright, trademark, and other laws. Except as specified in this permission statement, this publication may not be copied, reproduced, modified, published, uploaded, posted, transmitted, or distributed in any way, without prior written permission from Cadence. This statement grants you permission to print one (1) hard copy of this publication subject to the following conditions: 1. The publication may be used solely for personal, informational, and noncommercial purposes; 2. The publication may not be modified in any way; 3. Any copy of the publication or portion thereof must include all original copyright, trademark, and other proprietary notices and this permission statement; and 4. Cadence reserves the right to revoke this authorization at any time, and any such use shall be discontinued immediately upon written notice from Cadence. Patents: Cadence Product Encounter™ Equivalency Checker described in this document, is protected by U.S. Patent [6,842,884] Disclaimer: Information in this publication is subject to change without notice and does not represent a commitment on the part of Cadence. The information contained herein is the proprietary and confidential information of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’s customer in accordance with, a written agreement between Cadence and its customer. Except as may be explicitly set forth in such agreement, Cadence does not make, and expressly disclaims, any representations or warranties as to the completeness, accuracy or usefulness of the information contained in this document. Cadence does not warrant that use of such information will not infringe any third party rights, nor does Cadence assume any liability for damages or costs of any kind that may result from use of such information. Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Encounter Conformal Equivalence Checking Reference Manual

Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2 Command Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using UNIX Commands with Conformal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ABSTRACT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADD MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

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26 28 30 32 35 37 39 41 43 44 46 47 48 50 52 53 55 57 59 61 63 65 68 70

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ADD NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADD NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADD NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADD NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADD NOTRANSLATE LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADD NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADD OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADD OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADD PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADD PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ADD PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADD PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADD PRIMARY INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADD PRIMARY OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 ADD RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 ADD RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ADD SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 ADD SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ADD TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ANALYZE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 ANALYZE DATAPATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ANALYZE ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 ANALYZE IMPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 ANALYZE MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ANALYZE NONEQUIVALENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 ANALYZE POWER ASSOCIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 ANALYZE RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 ANALYZE SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 APPLY PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 ASSIGN PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 BACKWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 CHANGE GATE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 CHANGE NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 CHECK LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 CHANGE NET TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

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Product Version 7.2


CLOSE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMMIT CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPY MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

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147 148 150 154 155 157 158 159 161 163 164 166 167 168 169 170 171 172 173 174 175 176 178 179 181 183 184 185 186 187 188 189 190 192 193 194

Product Version 7.2


DELETE PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DELETE TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIAGNOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ELABORATE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLATTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FORWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GENERATE ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVERT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LICENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAP ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAP KEY POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOS2BUFIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVE INSTANCE DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPEN SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OPTIMIZE PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRINTENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PROVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ FSM ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ LEF FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REDUCE MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

6

195 196 198 199 200 202 204 205 208 209 210 211 213 214 216 218 219 220 221 223 224 225 228 230 231 233 234 247 249 250 257 259 260 261 263 266

Product Version 7.2


REMODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CPF LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DATAPATH RESOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DESIGN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DESIGN SIMILARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT FLOATING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT KEY POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LIBRARY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT LOWPOWER DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

7

268 272 274 275 276 278 280 281 284 287 288 289 290 291 292 295 296 297 298 299 300 303 305 309 311 312 313 314 315 316 318 320 321 324 328 330

Product Version 7.2


REPORT MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PARTITION RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT PULSE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT REMOVED INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT STATISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TESTCASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TEST VECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT UNMAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REPORT VERIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESET HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESOLVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RESTORE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

8

331 334 336 337 339 340 341 342 343 344 345 346 347 348 350 351 353 354 355 356 357 358 359 360 362 363 364 366 368 370 373 375 376 377 378 380

Product Version 7.2


RUN HIER_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUN PARALLEL COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RUN PARTITION_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAVE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ANALYZE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET_ATTR INPUT_PRAGMA_KEYWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET CASE SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMPARE EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET COMPARE OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET CPU LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DIRECTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET DOFILE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET EXIT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET FLATTEN MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET FPGA TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET GATE REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET HDL DIAGNOSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET HDL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET LOG FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET LOWPOWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MAPPING METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MOS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MULTIPLIER IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET NAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET PARALLEL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET RETIMING OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET ROOT MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

9

381 385 387 388 389 390 391 392 397 398 399 400 401 402 404 406 408 415 416 417 422 423 425 426 427 431 435 437 440 443 444 447 448 454 456 457

Product Version 7.2


SET RULE FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET RULE HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SCREEN DISPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SPICE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET STATETABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYNTHESIS_OFF_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYNTHESIS_ON_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET SYSTEM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UDP PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDEFINED CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDEFINED PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET UNDRIVEN SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET WIRE RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET X CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SET XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUBSTITUTE BLACKBOX MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SUBSTITUTE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TCLMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIQUIFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VALIDATE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VALIDATE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPXMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE ECO DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE HIER_COMPARE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WRITE PARTITION DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

10

458 459 461 462 464 465 466 467 468 469 471 472 473 474 476 477 478 479 481 482 483 487 489 490 494 497 498 499 501 503 505 507 512 513 515 517

Product Version 7.2


WRITE RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

3 HDL Rule Check Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DIR9.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

11

522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 540 541 542 543 544 545 547 549 550 551 553 554 555 556

Product Version 7.2


HRC1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.4a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.5c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC3.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HRC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

12

557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592

Product Version 7.2


IGN3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IGN7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Transfer Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL2.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

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593 594 595 596 597 598 599 600 601 602 603 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632

Product Version 7.2


RTL2.10 RTL2.11 RTL2.12 RTL2.13 RTL3.1 RTL3.2 RTL3.3 RTL3.4 RTL3.5 RTL4.1 RTL4.2 RTL4.3 RTL4.4 RTL5.1 RTL5.2 RTL5.3 RTL5.4 RTL6.1 RTL6.2 RTL6.3 RTL6.4 RTL6.5 RTL6.6 RTL7.1 RTL7.2 RTL7.3 RTL7.4 RTL7.5 RTL7.6 RTL7.7 RTL7.8 RTL7.9 RTL7.10 RTL7.11 RTL7.12 RTL7.13

May 2008

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633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668

Product Version 7.2


RTL7.14 RTL7.15 RTL7.16 RTL7.17 RTL7.18 RTL7.19 RTL7.20 RTL7.21 RTL8.1 RTL8.2 RTL8.3 RTL8.4 RTL8.5 RTL9.1 RTL9.2 RTL9.3 RTL9.4 RTL9.5 RTL9.7 RTL9.8 RTL9.9 RTL9.10 RTL9.11 RTL9.12 RTL9.13 RTL9.14 RTL10 RTL11 RTL12 RTL12.1 RTL13 RTL13.1 RTL13.2 RTL14 RTL14.1 RTL15

May 2008

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Product Version 7.2


RTL15.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL15.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL16.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL16.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL17.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL18.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL18.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL18.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL18.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL19.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL20.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL20.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RTL20.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPICE Netlist Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

16

706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741

Product Version 7.2


SV1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV1.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SV3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User-Defined Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UDP4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

17

742 743 744 745 746 747 748 749 750 751 752 753 754 755 757 758 759 760 761 762 763 764 767 768 769 770 771 772 773 774 775 776 777 778 779 780

Product Version 7.2


VLG4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG5.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.3a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG6.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG9.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG10.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG10.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG10.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLG11.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

18

781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816

Product Version 7.2


VLG11.2 VLG12.1 VLG13.1 VLG13.2 VLG13.3 VLG14.1 VLG15.1 VLG16.1

............................................................. ............................................................. ............................................................. ............................................................. ............................................................. ............................................................. ............................................................. .............................................................

817 818 819 820 821 822 823 824

4 Modeling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

May 2008

19

826 827 828 829 830 831 832 833 834 835 836 837 838 840 841 842 843 844 845 846 847 849 850 851

Product Version 7.2


F30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F34.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Tcl Command Entry Mode Support

. . . . . . . . . . . . . . . . . . . . . . . . . . . 863

find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_compare_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_compare_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_exit_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_fanins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_gate_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_handle_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_keypoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_map_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_module_definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_parent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_primitive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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852 853 854 855 856 857 858 859 860 861 862

865 866 866 867 868 868 868 868 868 868 869 869 870 871 871 872 872 873 874 875 876

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get_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_root_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_unmap_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . set_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . echo_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_license_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_version_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . objtype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

877 878 878 879 879 879 879 880 880 880

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

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About This Manual This manual documents commands, HDL rule checking messages, and modeling messages for the following Encounter® Conformal® Equivalence Checking solutions: ■

Conformal Extended Checks Conformal Extended Checks has equivalency checking capabilities with functional checks for ASIC design flows.

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Conformal Ultra Conformal Ultra includes Extended Checks and extends equivalency checking capabilities to datapath synthesis and layout.

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Conformal Custom Conformal Custom includes Conformal Ultra and extends equivalency checking capabilities to digital custom logic and custom memories.

■

Conformal LowPower Conformal LowPower enables low power equivalence and functional checks for isolation cells, level-shifter cells, and retention-register cells.

Audience This manual is written for experienced designers of digital integrated circuits who must be familiar with RTL, synthesis, and design verification; as well as having a solid understanding of UNIX and Tcl/Tk programming.

Related Documents For more information about the Conformal family of products, see the following documents. You can access these and other Cadence documents with the CDSDoc online documentation system. For a complete list of documents provided with this release, see the CDSDoc library.

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Encounter Conformal Equivalence Checking Reference Manual About This Manual ■

Encounter Conformal Equivalence Checking User Guide Describes how to install, configure, and use Conformal to verify RTL, gate, or transistorlevel designs.

Conventions Convention

Definition

Bold Case

Indicates the command name.

UPPERCASE

Indicates the required minimum character entry.

< >

Indicates required arguments. Do not type the angle brackets.

[ ]

Indicates optional arguments. Do not type the square brackets.

|

Indicates a choice among alternatives. Do not type the vertical bar.

\

The backslash character (\) at the end of a line indicates that the command you are typing continues on the next line.

…

Indicates multiple entries of an argument.

*

Indicates that LEC lets the wildcard (*) represent zero or more characters.

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2 Command Reference This chapter describes the Encounter® Conformal® commands. The commands are presented in alphabetical order. This chapter also includes the following sections: ■

Command Syntax on page 26

■

Wildcards on page 28

■

Using UNIX Commands with Conformal on page 30

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Encounter Conformal Equivalence Checking Reference Manual Command Reference

Command Syntax ■

Conformal commands are not case sensitive.

■

For every Conformal ADD command, there are corresponding DELETE and REPORT commands. For example: ADD OUTPUT EQUIVALENCES DELETE OUTPUT EQUIVALENCES REPORT OUTPUT EQUIVALENCES

■

Conformal commands adhere to the “3-2-1” rule, which reduces the number of characters you must type. ❑

3: Type the leading three characters of the first term.

❑

2: Then type the leading two characters of the second term.

❑

1: End with the leading character of the third term.

In some cases, you must use more characters to resolve ambiguity. In this manual, the minimal sets of characters you must type are shown as uppercase letters in the syntax. When you use the 3-2-1 rule in conjunction with the syntax guide to resolve any possible ambiguity, you reduce the number of characters in a command, as the following example shows: ADD OUtput Equivalences becomes add ou e ■

Reduce the number of characters you type for command options to the characters shown in uppercase in the syntax, as the following example shows: add output equivalences out10 out20 -module sub_mod1 -revised becomes add ou e out10 out20 -m sub_mod1 -r

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Searching the Help Database for Specified Strings Use the SEARCH command to search s the Help database of commands and options for matches to strings you specify. Viewing TCLmode Help Information The HELP command also displays a list of Conformal TCLmode commands. While in TCLmode, use the following syntax: HELp

To view command usage for a specific command, use the HELP command followed by the command name. HELp [command_name]

System prompt and command example: TCL_SETUP> help set_current_module

Viewing Conformal UNIX-Style Man Pages Conformal includes a man directory housed in: /doc/mann/. Important Observe the following requirements for viewing UNIX-style man pages: ❑

You must type the entire command name.

❑

Do not apply the 3-2-1 rule (described below).

❑

Do replace each space in the command name with an underscore ( _ ).

1. To access this resource from your UNIX shell, add the following variable: % setenv MANPATH “/doc:$MANPATH”

2. Type the following: man command_name

For example: man read_design man set_system_mode

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Wildcards On an as-needed basis, Cadence adds wildcard pattern-matching support to Conformal commands. The syntax convention that alerts you to wildcard support is the asterisk (*). If you use a pattern where a filename or design object is expected, Conformal Equivalence Checker expands the pattern using the same conventions as in the UNIX shell. ■

Triggering pattern matching for filenames To trigger pattern matching for filenames, a string must include at least one asterisk (*), question mark (?), or a pair of square brackets ( [ ] ).

■

Triggering pattern matching for design objects To trigger pattern matching for design objects, a string must include at least one asterisk (*) or question mark (?).

In arguments that are considered patterns, the following characters have special meaning: ^, {, }, [, ], ?, *. The dash (-) also has special meaning when it falls between square brackets. Note: When you use wildcards for design objects, a wildcard can match a string that includes the hierarchical delimiter (/). For example, the pattern *[10] matches the design object a/b/c[10]. When you use wildcards for filenames, every wildcard applies to part of a single directory or filename (this convention is the normal UNIX convention). For example, the pattern *.v does not match the filename a/b/c.v.

Special Characters for Filename and Design Object Pattern-Matching Wildcard Character

Definition

Example

?

Match any single character.

a?c matches: aac, abc, a4c, a?c

*

Match any (possibly empty) string.

a*c matches the following: ac, abc, a*c

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Special Characters for Filename and Design Object Pattern-Matching Wildcard Character [ ]

Definition

Example

Match any single character listed between the square brackets: “[” and “]”.

For filenames:

That is, “[” followed by If the first character is “^”, characters and Conformal Equivalence Checker “]” matches any single character not listed between the brackets. If the list shown between the brackets includes x-y, Conformal Equivalence Checker matches all characters in the range x–y.

a[145] matches the following: a1 a4 a5 For design objects: a*[145] matches the following:

ab1 a34 To match square brackets, you must at5 include the escape character a*\[145\] matches the following: immediately preceding the square ab[145] bracket. a3[145] To be matched, the characters “-” at[145] and “]” must appear first in the list (possibly after ^). Note: For design objects, recall that a string triggers pattern matching with an asterisk or question mark. In those cases, this convention applies. ^

At the beginning of the pattern, the character “^” negates the result of the match:

â* matches any name that does not begin with a.

\

Matches only the character that follows the “\” character.

a\[10] matches the following: a[10] But it does not match: a1 a0

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Special Characters for Filename and Design Object Pattern-Matching Wildcard Character {p1,p2,…}

Definition

Example

Matches any string matched by any design/{top,sub{5,11}}/*.v of the sub-patterns listed. matches the following: design/top/a.v design/sub5/b.v design/sub11/c.v Braces can nest. a/{d{e,f},g{h,i}}_0 matches the following: a/de_0 a/df_0 a/gh_0 a/gi_0

Using UNIX Commands with Conformal To execute a UNIX command from within LEC or an LEC command script, start the line with an exclamation point “!” or with the SYSTEM command. When you execute commands in this way, they display to the standard output, and LEC records them in a log file, if one is active.

Using the -all Option This option applies within the given defaults. For example, the syntax for the ADD OUTPUT EQUIVALENCES command is as follows: ADD OUtput Equivalences [-Invert ] [-ROot | -Module | -All] [-Golden | -Revised | -Both]

In the above syntax, -golden is a default. Therefore, if you type the command with primary pin names and the -all option, but no other option, this command specifies output pin equivalences on all output boundary module pins in the Golden design.

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Using the -both Option When you use this option in conjunction with a specific name (for example, a pin name), that name must appear in both designs. Otherwise, LEC returns an error message. For example, the syntax for the ADD PIN EQUIVALENCES command is as follows: ADD PIn Equivalences [-Invert ] [-ROot | -Module |-All] [-User | -Hier] [-Golden | -REvised | -Both]

Notice -both in the above syntax. If you specify three primary pins (for example, a1, a2, and a) and the -both option; all three pin names must exist in both the Golden and Revised designs. If they do not, LEC returns an error message. If you specify a1, a2, a and include the -revised option; LEC applies equivalence to the pins in the Revised design only (even if these three pins also exist in the Golden design).

Saving the Command’s Output to a File To save the command’s output to a file, Cadence recommends using the command line > operator. This works for all Conformal commands. For example, to save the default output of the REPORT GATE command to a file named gate.out, you would run the following: report gate > gate.out

You can also use the >> operator to append output text to an existing file. Note: Although some commands include a -file type option to save the command’s output to a file, Cadence recommends using the command line > operator.

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ABSTRACT LOGIC ABSTract LOGic [-MODule ] [-All] [-PURE] [-AUTO | -NOAUTO] [-Golden | -Revised] [-ASM | -NOASM] [-TEST_VIEW] (Setup Mode)

Note: This is a Conformal Custom command. Use this instead of the pre-5.0 EXTRACT command. Performs functional analysis on circuit netlists, which can contain different devices, including transistors, gates, and state elements. The analysis abstracts a logically-correct gate and a state primitive model. Use the logic model and compare it to the RTL model for complete functional verification. You can also write out the logic model and use it during high-performance simulation or fault grading. Note: If neither the -all nor -module option is specified, Conformal abstracts the current root module and any modules that are instantiated under it.

Parameters -MODule name

Abstracts logic information from the specified module and its hierarchy.

-All

Abstracts logic information from all cells in the database, including cells that are not used by the current root module.

-Pure

Performs basic gate abstraction, which is useful for debugging.

-AUTO

Enables propagation of constants, pin constraints, non-inverted and inverted pin relationships across module boundaries. This is the default.

-NOAUTO

Does not invoke hierarchical analysis.

-Golden

Abstracts logic from the Golden design. This is the default.

-Revised

Abstracts logic from the Revised design.

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-ASM

Enables the Advanced State-element Modeling (ASM) algorithm. This helps to analyze loop structure to produce better modeling of state elements, such as D-Latch, DFF, and bus-keeping I/O logic. This is the default.

-NOASM

Disables the Advanced State-element Modeling (ASM) algorithm. Tip If there are any unexpected results, you can use this option to revert back to the functionality of the 6.2 release and earlier.

-TEST_VIEW

Performs structurally accurate abstraction. With this option, only limited boolean simplification is done for abstraction. As a result, the gate-level structure of the original logic is preserved as much as possible after abstraction.

Related Commands ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE MOS2BUFIF READ PATTERN REPORT ABSTRACT MODEL REPORT CLOCK REPORT MOS DIRECTION

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESET ABSTRACT MODEL RESOLVE SET ABSTRACT MODEL

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ADD ALIAS ADD ALias (Setup / LEC Mode)

Adds alias names for quick command entry. Assign an alias to long command names and arguments to minimize typing and character entry. If you add an alias with an alias name that already exists, Conformal accepts the new alias and returns a warning as shown in the following example: //Warning: Alias ‘myread’ is already defined, will be replaced by the new definition

For the greatest benefit, create aliases at the start of a Conformal session. Also, add aliases to an initial command file: .conformal_lec. The CONFORMAL_RC Environment Variable Conformal checks for the CONFORMAL_RC environment variable. If this variable is set, Conformal uses the file this variable refers to and does not search for other files. If the CONFORMAL_RC variable is not set, Conformal continues the search as follows: ■

First, the installation directory: /share/cfm/lec/.conformal_lec

■

Second, the user’s home directory: ~/.conformal_lec

■

Third, the current working directory: ./.conformal_lec

If one or more of these initial command files exist, Conformal runs them in the order noted above. This process offers flexibility in the way you choose to use the initial command file. You can set up initial command files for any or all of the following purposes: ■

A global initial command file for all users

■

A global initial command file for an individual user

■

An initial command file for a test case

Parameters name

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Specifies the name of the alias.

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string

Specifies the command that the alias represents.

Related Commands DELETE ALIAS REPORT ALIAS

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ADD BLACK BOX ADD BLack Box [<[-Module | -Instance] [name*…] [-File ]> | -All] [ | -Design | -Library]> [-Golden | -Revised | -Both] (Setup Mode)

Specifies modules or instances that will be defined as blackboxes. These newly defined blackboxes are classified in the User class of blackboxes. Blackboxes already contained in the original design are classified in the System class of blackboxes. Note: The wildcard (*) represents any zero or more characters in blackbox names.

Parameters -Module

Defines this list of module names as blackboxes. This is the default.

-Instance

Defines this list of instance names as blackboxes.

name ...

Defines the list of names of modules or instances. Note: Wildcard names are only supported for the module names. The wildcard (*) represents any zero or more characters in the blackbox module names.

-File

Specifies the name of the blackbox file. This file must contain only names of modules or instances, it is not a Verilog file. The names in the file are added to the [name...] list.

-All

Blackboxes all modules except the top module. -All applies within the given defaults.

-Design

(Used with the -all option only) Blackboxes all modules in the design. If you do not specify either -design or -library, blackboxing applies to both the library and the design.

-Library

(Used with the -all option only) Blackboxes all modules in the library. If you do not specify either -design or -library, blackboxing applies to both the library and the design.

-Golden

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-Revised

Blackboxing applies to the Revised design only.

-Both

Blackboxing applies to both the Golden and Revised designs.

Related Commands DELETE BLACK BOX REPORT BLACK BOX

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ADD CLOCK ADD CLock <0 | 1> [-Module ] [-Golden | -Revised] (Setup Mode)

Defines a clock state where data can change. You can use this command to define: ■

Pre-charge clock states for domino style circuits

■

Stable nets for clock-gating modeling Caution When using the ADD CLOCK command with set flatten model -gated_clock, there is an assumption that the ENABLE signal going into the AND gate of the clock cone is stable. Use with caution.

Parameters 0

Specifies that the off-state of the clock pin is 0. This means that when the pin is low, pre-charge occurs.

1

Specifies that the off-state of the clock pin is 1.

primary_pin…

Defines the listed primary input pins as clocks in pre-charged transistor-MOS.

-Module name

Specifies that the defined clock pin is located in this module.

-Golden

Specifies that the clock is in the Golden design. This is the default.

-Revised

Specifies that the clock is in the Revised design.

Related Commands ABSTRACT LOGIC ADD MOS DIRECTION ADD NET ATTRIBUTE

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE SET ABSTRACT MODEL

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ADD COMPARED POINTS ADD COmpared Points <-All | > (LEC Mode)

Adds mapped points to the compare list. You can add compare points for all mapped points, or for a list of the gate ID numbers, instance paths, or pin paths. If you add a compare point to the Golden design, the Conformal software also adds its mapped compare point from the Revised design. Alternately, if you add a compare point to the Revised design, the software also adds its mapped compare point in the Golden design. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths.

Parameters -All

Adds “all” mapped points, excluding primary inputs, as compare points. -All applies within the given defaults.

gate_id

Adds the specified gate ID numbers as compare points. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname*

Adds the specified instance paths as compare points.

pin_pathname*

Adds the specified pin paths as compare points.

-FRONTier

Adds the specified key points and its frontier to the compare list. If no key points are specified, the frontier is computed from the existing compare points, and added to the compare list. No key points are added to the compare list if the frontier contains any unmapped key points.

-Golden

The gate ID numbers, instance paths, or pin paths are in the Golden design. This is the default.

-Revised

The gate ID numbers, instance paths, or pin paths are in the Revised design.

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Examples For a set of sample commands that shows this and related commands in context, see the example for the COMPARE command.

Related Commands DELETE COMPARED POINTS REPORT COMPARED POINTS

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ADD CUT POINT ADD CUt Point [-Net | -Pin] [-Golden | -Revised | -Both] (Setup Mode)

Adds a cut point to the specified net or pin path. This overrides automatic feedback loop cuts, which Conformal otherwise establishes on entering the LEC mode.

Parameters pathname

Specifies the path that is the cut point of the feedback loop.

-Net

Specifies that the path is a net. This is the default.

-Pin

Specifies that the path is a pin.

-Golden

Applies the cut point to the Golden design. This is the default.

-Revised

Applies the cut point to the Revised design.

-Both

Applies the cut point to both the Golden and Revised designs.

Related Commands DELETE CUT POINT REPORT CUT POINT REPORT PATH

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ADD DYNAMIC CONSTRAINTS ADD DYnamic Constraints <0 | 1> [-INStance | -Pin | -Net | -ID] [-Golden | -Revised | -Both] (LEC Mode)

Adds dynamic constraints for use with the PROVE command. Place constraints on the following: ■

Hierarchical instance paths

■

Hierarchical pin paths

■

Hierarchical net paths

■

Gate identification numbers

These constraints are either a 0-state or 1-state. Use this command as you diagnose and debug logic cones to help prove gate equivalence.

Parameters 0

Constrains the identifier to a 0-state.

1

Constrains the identifier to a 1-state.

identifier…

If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order.

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-INStance

Hierarchical instance path This is the default.

-Pin

Pin path, which is the module instance name concatenated with the pin name.

-Net

Net path, which is the instance name concatenated with the net name.

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-ID

Identification number (ID) of a gate. The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

-Golden

Adds the dynamic constraints to the Golden design only. This is the default.

-Revised

Adds the dynamic constraints to the Revised design only.

-Both

Adds the dynamic constraints to both the Golden and Revised designs.


Related Commands DELETE DYNAMIC CONSTRAINTS PROVE REPORT DYNAMIC CONSTRAINTS

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ADD ECO CELL ADD ECo Cell [-DEFfile ] [-FReedcell] [-SParecell ] (Setup Mode)

Adds the spare cells or freed cells as the available cells for the MAP ECO PATCH command.

Parameters -DEFfile Specifies the DEF file name. If specified, the spare cell will be searched in DEF file. Otherwise, the spare cell will be searched in current hierarchy. -FReedcell

Specifies that freed cells will be used for mapping.

-SParecell

Specifies the spare cells to be added.

Related Commands DELETE ECO CELL MAP ECO PATCH REPORT ECO CELL

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ADD ECO LIBRARY ADD ECo Library [ | -ALL] [-Golden | -Revised] (Setup Mode)

Adds the library to the library list used by the by the MAP ECO PATCH command.

Parameters

Specifies the name of the library.

-ALL

Adds all the libraries in Golden or Revised.

-Golden

Specifies that the library is in the Golden library. This is the default.

-Revised

Specifies that the library is in the Revised library.

Related Commands MAP ECO PATCH

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ADD ECO PATCH ADD ECo PAtch [-PATH ] (Setup Mode)

Specifies the ECO patch and adds the patch module to be mapped by the MAP ECO PATCH command.

Parameters Specifies the name of the module being changed for ECO. Specifies the name of the patch module that contains the ECO changes. [-PATH ] Specifies the hierarchy path to the module under ECO. This is for the ADD ECO CELL command to locate the freed cell locations in DEF file.

Examples In the following command sequence, the ECOs defined in the G1_eco and G2_eco patch modules will be applied to the design and mapped to the spare cells and freed cells, and will write out the new mapped patch modules to the map.v file. add add add add map

eco eco eco eco eco

patch G1 G1_eco -path /U1/U1 patch G2 G2_eco -path /U1/U2 library typical cell -def layout.def -freed -spare *spare* patch map.v -replace

Related Commands ADD ECO CELL ADD ECO LIBRARY

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Encounter Conformal Equivalence Checking Reference Manual Command Reference DELETE ECO PATCH MAP ECO PATCH REPORT ECO PATCH

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ADD ECO PIN ADD ECo PIn | > ... [-INput | -OUTput | -IO] [-FORce] [-Golden | -Revised] (Setup Mode)

Adds a pin to a module. If the Revised module has extra ports, you can use this command to add new pins to the Golden module. Cadence recommends that you add the extra pins before running the WRITE HIER_COMPARE DOFILE command.

Parameters

Specifies the name of the module.

Specifies the name of the pin(s).

>

Specifies the name of the bus(es), where is [msb:lsb], for example, [16:0]. You must include the braces in the command. See the Examples section.

-INput

Specifies that the pin is an input pin. This is the default.

-OUTput

Specifies that the pin is a output pin.

-IO

Specifies that the pin is an input/output pin.

-FORce

Renames the signal if it conflicts with the port name. See the Examples section.

-Golden

Applies to the Golden design. This is the default.

-Revised

Applies to the Revised design.

Examples ■

The following command adds wr_req input port and data[15:0] input bus to module mod_A add eco pin mod_A wr_req data[15:0] -input -golden

■

This example shows how the command’s -force option affects the following design: module top(x,y);

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Encounter Conformal Equivalence Checking Reference Manual Command Reference wire z; endmodule ❑

The following command will error out because there is a conflict between the net z and the new port z: add eco pin -output top z

❑

The following command will not error out and net z will be renamed z_1: add eco pin -output top z -FORce

Related Commands ANALYZE ECO DELETE ECO PIN WRITE HIER_COMPARE DOFILE

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ADD IGNORE RTLCHECK ADD IGnore Rtlcheck <-All | -Module > (Setup Mode)

Ignores RTL (HDL) rule checking for all or specified modules. Run this command before the READ LIBRARY and READ DESIGN commands. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about specific rules. Tip When using the -module option, ensure that you have entered the module name correctly. If you enter a nonexistent module name, Conformal conducts the checks and issues messages as usual. Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace previous commands. In the following example, Conformal ultimately enables RTL rule checking for all modules, including module abc. add ignore rtlcheck -module abc delete ignore rtlcheck -all

Wildcard: The wildcard (*) represent any zero or more characters in module names.

Parameters -All

Ignores RTL rule checking for all modules.

-Module name*…

Ignores RTL rule checking for the specified modules.

Related Commands DELETE IGNORE RTLCHECK REPORT RULE CHECK

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ADD IGNORED INPUTS ADD IGnored Inputs [-ROot | -Module | -All] [-Golden | -REvised | -Both] (Setup Mode)

Specifies which input pins Conformal ignores during comparison. You can use this command when the input pins are part of a blackboxed module. Note: Specified pins must be boundary module pins. Although boundary module pins are generally not compared points, they are compared points when the corresponding module becomes a blackbox. For example, when Conformal compares two blackboxes and one of them has extra input pins, such as scan in and scan enable pins, use this command to tell Conformal to ignore these extra input pins during comparison. Wildcard: The wildcard (*) represent any zero or more characters in ignored inputs and module names.

Parameters primary_pin*…

Ignores this list of primary input pins (associated with the root module or the specified submodule).

-ROot

Ignores the specified input pins in the root module. This is the default.

-Module name*

Ignores the specified input pins in this module.

-All

Ignores the specified input pins in “all” the modules, including the root module. -All applies within the given defaults.

-Golden

Ignores the specified input pins in the Golden design. This is the default.

-REvised

Ignores the specified input pins in the Revised design.

-Both

Ignores the specified input pins in both the Golden and Revised designs.

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Related Commands DELETE IGNORED INPUTS REPORT IGNORED INPUTS

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ADD IGNORED OUTPUTS ADD IGnored Outputs [-Module |-All] [-Golden |-REvised |-Both] [-EQuivalences] (Setup Mode)

Specifies which output pins Conformal ignores during comparison. Note: Specified pins are boundary module pins. For example, when Conformal compares two modules and one of them has extra outputs, such as scan out pins, use this command to tell Conformal to ignore these extra output pins during comparison. Wildcard: The wildcard (*) represents any zero or more characters in ignored outputs and module names.

Parameters primary_pin*…

Ignores this list of primary output pins (associated with the root module or the specified submodule).

-Module name*

Ignores the output pins in the specified module. The default is the root module.

-All

Ignores the specified output pins in “all” the modules, including the root module. -All applies within the given defaults.

-Golden

Ignores the specified output pins in the Golden design. This is the default.

-REvised

Ignores the specified output pins in the Revised design.

-Both

Ignores the specified output pins in both the Golden and Revised designs.

-EQuivalences

Ignores the specified output pins and their equivalences. The equivalences of a pin must be specified by the ADD OUTPUT EQUIVALENCES command prior to using this option. Equivalences created after using this option will not be ignored.

Related Commands ADD OUTPUT EQUIVALENCES

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Encounter Conformal Equivalence Checking Reference Manual Command Reference DELETE IGNORED OUTPUTS REPORT IGNORED OUTPUTS

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ADD INSTANCE ATTRIBUTE ADD INstance Attribute [ | ] [-Golden | -Revised] (Setup Mode)

Specifies how to treat an attribute for a gate or transistor primitive. Attributes can either be WEAK or deleted from the database for the purposes of a complete abstraction and comparison. However, newer abstraction capabilities can make the WEAK feature unnecessary.

Parameters module_name

Applies the instance attribute to the specified module, which contains the instance.

instance_name

Applies the instance attribute to the specified instance.

WEAK

Note: This option applies to Conformal Custom. Specifies drive strength of WEAK on an attribute. In the case of multiple drivers, ■

First, the state of the node is determined by devices that are not WEAK (STRONG).

■

Then, if there are none, or if all of the STRONG devices are disabled, the WEAK devices impact the net’s function.

This option affects extraction behavior and loop handling. DELETE

Removes the specified device from the circuit. Note: This option applies to Conformal Custom. Tip The preferred method is to use the REMOVE command.

-Golden

Applies the instance attribute to the Golden design. This is the default.

-Revised

Applies the instance attribute to the Revised design.

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Related Commands DELETE INSTANCE ATTRIBUTE REMOVE REPORT INSTANCE ATTRIBUTE

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ADD INSTANCE CONSTRAINTS ADD INstance Constraints <0 | 1>
-Module name*>

Places constraints on specified instance paths in either the Golden or Revised design. You can only place 0-state or 1-state constraints on the outputs of instances. You can only apply instance constraints to D flip-flops and D-latches inside the specified instance paths. Wildcard: The wildcard (*) represents any zero or more characters in instance and module names.

Parameters 0

Constrains the specified instance paths to a 0-state.

1

Constrains the specified instance paths to a 1-state

instance_pathname*… Places the constraints on these instance paths. Note: The instances are either DFFs or D-latches. name…

-Module name* Applies the constraint to the specified module(s).

-REPlace

Changes the previously specified instance constraint.

-Golden

Applies the instance constraints to the Golden design. This is the default.

-Revised

Applies the instance constraints to the Revised design.

-Both

Applies the instance constraints to both the Golden and Revised designs.

Examples add instance constraints 0 /U1/U2/U3 -revised add instance constraints 1 /U6/U5 /U7/U8 -golden add instance constraints 0 /U6/U5 /U7/U8 -replace -golden

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Related Commands DELETE INSTANCE CONSTRAINTS REPORT INSTANCE CONSTRAINTS

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ADD INSTANCE EQUIVALENCES ADD INstance Equivalences [-Invert ] [-Golden | -Revised | -Both] (Setup Mode)

Defines D-latches and D flip-flops as equivalent or inverted equivalences. This command is useful in mapping and its output is verified during the comparison. Use this command when you have one state element in a design that corresponds to two or more state elements in another design. Note: Only apply instance equivalences to D flip-flops and D-latches. Effects on Comparison This command affects comparisons when you use add compared points -all. In that situation, Conformal merges the instances specified with the ADD INSTANCE EQUIVALENCES command and then verifies them at the end of the comparison. Wildcard: The wildcard (*) represents any zero or more characters in instance names.

Parameters instance_pathname*… Defines the group of instances that are equivalent. The first instance is the representative instance. The following instances are equivalent to the representative instance. Note: The instances are either DFFs or D-latches. The wildcard (*) is supported. -Invert instance_pathname*… Defines a group of instances that is an inverted equivalence of the group that is equivalent. Note: The instances are either DFFs or D-latches. -Golden

Applies instance equivalences to the Golden design. This is the default.

-Revised

Applies instance equivalences to the Revised design.

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-Both

Applies instance equivalences to both the Golden and Revised designs.

Related Commands ADD COMPARED POINTS DELETE INSTANCE EQUIVALENCES REPORT INSTANCE EQUIVALENCES SET FLATTEN MODEL

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ADD LOWPOWER CELLS ADD LOwpower Cells [-isolation | -level_shifter | [-retention -attribute ] ] [-Both | -Golden| -Revised] (Setup Mode)

Note: This is a Conformal Low Power command. Defines the low power attribute for specified modules.


Applies the low power cell attribute to the specified module(s). Wildcards are accepted.

-isolation

Specifies the module as isolation cell. This is equivalent to the attribute is_isolation_cell : true in the liberty library.

-level_shifter

Specifies the module as level shifter cell. This is equivalent to the attribute is_level_shifter : true in the liberty library.

-retention -attribute Specifies the module as a state retention cell with its associated power gate cell attribute. This is equivalent to the attribute power_gating_cell : ATTRIBUTE in the liberty library. -Both

Applies the low power cell attribute to both the Golden and Revised designs. This is the default.

-Golden

Applies the low power cell attribute to the Golden design.

-Revised

Applies the low power cell attribute to the Revised design.

Examples ■

The following command assigns cell fdf1a1 as a state retention cell with a CLK_LOW attribute: add lowpower cells fdf1a1 -retention -attribute CLK_LOW -revised

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ■

The following command assigns cell and2b1 as an isolation cell: add lowpower cells and2b1 -iso -revised

Related Commands CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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ADD MAPPED POINTS ADD MApped Points << > |<-NET > |<-RULE >> [-INSTance | -NET] [-OUTput_pin ]… [-INPut_pin ]… [-GOLden | -REVised] [-NOINVert | -INVert] (LEC Mode)

When Conformal moves from Setup to LEC system mode, it automatically maps key points and places them in the System class of mapped points. If any additional mapped points are necessary, use this command, and Conformal will place them in the User class of mapped points. Note: If you attempt to add mapped points that were already mapped, Conformal returns a warning message. In the syntax shown below, the first gate_id, instance_pathname, or pin_pathname refers to the Golden design; the second argument refers to the Revised design. The -invert option makes one mapped point inverted with respect to the other mapped point. The (-) sign represents an inverted-mapped point. The (+) sign represents a non-inverted mapped point.

Parameters gate_id

Adds this gate (identified by number) as a mapped point. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname

Adds this instance path as a mapped point.

pin_pathname

Adds this pin path as a mapped point.

-NET net net

Uses the specified Golden and Revised net names to map key points together.

-RULE pattern substitution

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Uses the instance or net renaming rule with the specified original pattern and substitution pattern to map key points together. -INSTance

Specifies that the rule is an instance renaming rule. This is the default.

-NET

Specifies that the rule is a net renaming rule.

-OUTput_pin Golden_pin Revised_pin… Maps the specified Golden and Revised blackboxed output pins. Multiples are permitted. However, you must list Golden and Revised pins in pairs and you must precede each pair with the -output_pin option. (See the example below. For each pair that is listed, the first output pin is from the Golden design and the second output pin is from the Revised design.) -INPut_pin Golden_pin Revised_pin… Maps the specified Golden and Revised blackboxed input pins. Multiples are permitted. However, you must list Golden and Revised pins in pairs and you must precede each pair with the -input_pin option. (See the example below. For each pair that is listed, the first input pin is from the Golden design and the second input pin is from the Revised design.) -GOLden

Applies this rule pattern substitution to the Golden design. This is the default.

-REVised

Applies this rule pattern substitution to the Revised design.

-NOINVert

Does not invert the two mapped points with respect to one another. This is the default.

-INVert

Inverts the two mapped points with respect to one another.

Examples In the following two commands, A1 is the instance path of a blackbox: add mapped points A1 A1 -input_pin in1[0] inA[0] -input_pin in1[1] inA[1] add mapped points A1 A1 -output_pin out1[0] outA[0] -output_pin out1[1] outA[1]

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Encounter Conformal Equivalence Checking Reference Manual Command Reference INVERT MAPPED POINTS MAP KEY POINTS READ MAPPED POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE

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ADD MODULE ATTRIBUTE ADD MOdule Attribute <-PIPELINE_Retime [-DFF2Buffer] | -COMPARE_Effort < Low | Medium | High | AUto | None> | -CPU_Limit # > [-Golden |-Revised] [-ECO_module] [-HIER_Compare ] (Setup Mode)

Defines the attributes for specified modules.

Parameters module_name*…

Applies the attribute to the specified modules. The wildcard (*) is supported.

-PIPELINE_Retime

Checks the specified modules for pipeline retiming (and remodel if pipeline retiming is detected). This option requires Conformal to check the module and remodel it if the Golden and Revised designs have pipeline-retiming.

-DFF2Buffer

Changes registers to buffers.This option lets you compare models with no registers to those with pipeline registers inserted.

-COMPARE_Effort

Assigns a specified comparison effort level to the module. This option is generally applied to hierarchical comparisons where some modules need a higher compare effort than others. For advanced pipeline retiming, see ANALYZE RETIMING.

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Low

Applies minimal effort to equivalency checking for the specified module. This is the default.

Medium

Applies greater effort to equivalency checking for the specified module.

High

Applies the maximum effort to equivalency checking for the specified module.

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AUto

Starts with low effort and automatically increases the compare effort when abort points are in the specified module.

None

Applies no compare effort to equivalency checking for the specified module.

-CPU_Limit #

Specifies a number of seconds for each module during hierarchical compare.This option decreases the amount of time Conformal spends comparing a particular module.

-Golden

Specifies that the module attribute applies to the Golden design. This is the default.

-Revised

Specifies that the module attribute applies to the Revised design.

-HIER_Compare For the specified module, replaces the default ’add compared points -all’ and ’compare’ commands in the hierarchical script generated using the ’write hier_compare dofile’ command with the specified .

Example In the following command sequence, the hierarchical dofile script hier.do that is generated with the ’write hier_compare dofile’ command contains the commands ‘add partition points -all,’ ‘set compare effort high,’ ‘add compared points -all,’ and ‘compare’ for module modA, instead of the default ‘add compared points -all’ and ‘compare’ command sequence: add module attribute modA -hier_compare "add partition points -all; set compare effort high; add compared points -all; compare" write hier_compare dofile hier.do -constraints

Related Commands ANALYZE RETIMING DELETE MODULE ATTRIBUTE REPORT MODULE ATTRIBUTE WRITE HIER_COMPARE DOFILE

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ADD MOS DIRECTION ADD MOs Direction | -All> [-FROM_Source_pin | -FROM_Drain_pin]> > [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Adds unidirection to bidirectional MOS devices. This can change a tranif0 into a PMOS, or change a tranif1 to an NMOS. Use the REPORT MOS DIRECTION command to display the list of all unidirectional and bidirectional transistor-MOS instances and their source and drain ports. Use this command to resolve bidirectional transistor-MOS instances, when the ABSTRACT command is not able to fully resolve all bidirectional transistor-MOS instances not supported for comparison.


Adds unidirection to the specified module.

instance_name

Adds unidirection to the specified instance.

net_name

Specifies the source net name, which is the input pin of the MOS device.

-Module name

Adds unidirection to all bidirectional MOS devices in this module.

-All

Adds unidirection to all bidirectional MOS devices. -All applies within the given defaults.

-FROM_Source_pin

Specifies that all source pins are inputs. This is the default.

-FROM_Drain_pin

Specifies that all drain pins are inputs.

-Golden

Applies the MOS direction to the Golden design. This is the default.

-Revised

Applies the MOS direction to the Revised design.

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Related Commands ABSTRACT LOGIC ADD CLOCK ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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ADD NET ATTRIBUTE ADD NEt Attribute [-Module ] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Defines pre-charge nets; power and ground; or with DYNSTate, defines a dynamic latch state. If you do not use the -module option with this command, Conformal applies the attribute to every module on the specified side (Golden or Revised).

Parameters VDD

Specifies that the net has a VDD attribute.

GND

Specifies that the net has a GND attribute.

CLOCK0

Specifies that the net has a Clock-0 attribute. This option places an off-state of 0 at the specified net. The off-state is defined as the value at which the clock port is inactive.

CLOCK1

Specifies that the net has a Clock-1 attribute. This option places an off-state of 1 at the specified net. The off-state is defined as the value at which the clock port is inactive.

DYNSTate

Specifies that the net is a dynamic state point, which Conformal Custom will abstract as a latch.

net_name

Specifies the transistor-MOS net name.

-Module name

Specifies that the specified module contains the transistor-MOS. If you do not use the -module option with this command, Conformal applies the attribute to every module on the specified side (Golden or Revised).

-Golden

Applies the net attribute to the Golden design. This is the default.

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-Revised

Applies the net attribute to the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE SET ABSTRACT MODEL

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ADD NET CONSTRAINTS ADD NEt Constraints [-Golden | -Revised | -Both] (Setup Mode)

Adds one-hot or one-cold constraints on specified net paths. The one-hot constraint lets only one net be at a 1-state and the remaining nets be at a 0-state. The one-cold constraint lets only one net be at a 0-state and the remaining nets be at a 1-state.

Parameters ONE_Hot

Places one-hot constraints on the specified net paths.

ONE_Cold

Places one-cold constraints on the specified net paths.

ZERO_ONE_Hot

Places zero-one-hot constraints on the specified net paths.

ZERO_ONE_Cold

Places zero-one-cold constraints on the specified net paths.

net_pathname…

Places constraints on the listed net paths.

-Golden

Applies the net constraints to the Golden design. This is the default.

-Revised

Applies the net constraints to the Revised design.

-Both

Applies the net constraints to both the Golden and Revised designs.

Related Commands DELETE NET CONSTRAINTS REPORT NET CONSTRAINTS

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ADD NOBLACK BOX ADD NOblack Box [-Golden | -Revised | -Both] (Setup Mode)

Specifies the modules that are excluded from the hierarchical dofile script generation. (Execute it before the WRITE HIER_COMPARE DOFILE command.) Wildcard: The wildcard (*) represents any zero or more characters in module names.


Does not include the listed modules in the hierarchical dofile script generation. The wildcard (*) is supported.

All

Does not include any instances or modules in the hierarchical dofile script generation except the top module. “All” applies within the given defaults.

-Golden

Does not include the specified modules in the Golden design. This is the default.

-Revised

Does not include the specified modules in the Revised design.

-Both

Does not include the specified modules in either the Golden or Revised designs.

Related Commands DELETE NOBLACK BOX REPORT NOBLACK BOX WRITE HIER_COMPARE DOFILE

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ADD NOTRANSLATE FILEPATHNAMES ADD NOtranslate Filepathnames [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Specifies library or design files, where modules defined in these files will not be translated when running the READ LIBRARY or READ DESIGN command. These modules will automatically become blackboxes. This command is applied during initial parsing, so name matching applies only to original module names. For parameterized or VHDL generic modules whose names are determined and applied by the Conformal software after parsing and preprocessing, you must use the ADD BLACK BOX command. The following are examples of modules that should not be compiled: ■

RAM models

■

Analog blocks

■

Modules that contain non synthesizable RTL constructs

Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters filepath_names*…

Specifies the filepath name, which can be directory names and Verilog filenames.The wildcard (*) and search path is supported.

-Library

Does not translate the modules in the specified library. If you do not specify -library or -design, Conformal applies this command to both the library and design modules.

-Design

Does not translate the modules in the specified design. If you do not specify -library or -design, Conformal applies this command to both the library and design modules.

-Both

Does not translate the specified modules in either the Golden or Revised libraries and designs. This is the default.

-Golden

Does not translate the specified modules in the Golden library or design.

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-Revised

Does not translate the specified modules in the Revised library or design.

Related Commands ADD NOTRANSLATE MODULES ADD SEARCH PATH DELETE NOTRANSLATE FILEPATHNAMES DELETE NOTRANSLATE MODULES REPORT NOTRANSLATE FILEPATHNAMES REPORT NOTRANSLATE MODULES

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ADD NOTRANSLATE LINES ADD NOtranslated Lines <[start:end | line] ... > (Setup Mode)

Specifies lines to skip in a Verilog or VHDL file. This has the same effect as commenting out the lines in the file. With this command, you can instruct the Conformal software to skip certain lines in the design file without having to modify the file.

Parameters filename

Specifies the Verilog or VHDL file.

start:end

Specifies the a line number range to skip. For example, 6:8 would skip lines 6, 7, and 8.

line

Specifies a line number to skip.

Example The following commands skip lines 6 through 8 and line 17 in the foo.v file when reading in the design: add notranslated lines foo.v 6:8 17 read dessign foo.v

As a result, lines 6, 7, 8 and 17 are skipped in the foo.v file: (1) module test(clk, rst, set, d, z); (2) input clk, set, rst, d; (3) output z; (4) reg z; (5) (6) garbage 1........... (7) initial begin end (8) garbage 2........... (9) (10) always @(negedge clk or negedge set or negedge rst) begin (11) if (!rst) z <= 1’b0; (12) else if (!set) z <= 1’b1; (13) else z <= d; (14) end (15) (17) garbage 3.... (18) (19)endmodule

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Related Commands READ DESIGN READ LIBRARY

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ADD NOTRANSLATE MODULES ADD NOtranslate Modules [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Specifies library or design modules that are parsed, but will not be translated when running the READ LIBRARY or READ DESIGN command. These modules automatically become blackboxes. Note: The ADD NOTRANSLATE MODULES command is applied during initial parsing, so name matching applies only to original module names. For parameterized or VHDL generic modules whose names are determined and applied by Conformal after parsing and preprocessing, you must use the ADD BLACK BOX command. Examples of modules that should not be compiled include: ■

RAM models

■

Analog blocks

■

Modules that contain non-synthesizable RTL constructs

Wildcard: The wildcard (*) represents any zero or more characters in module names.


Does not compile the listed library or design modules. The wildcard (*) is supported.

-Library

Does not compile the specified library modules. If you do not specify -library or -design, Conformal applies this command to both the library and design modules.

-Design

Does not compile the specified design modules. If you do not specify -library or -design, Conformal applies this command to both the library and design modules.

-Both

Does not compile the specified modules in either the Golden or Revised libraries and designs. This is the default.

-Golden

Does not compile the specified modules in the Golden library or design.

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-Revised

Does not compile the specified modules in the Revised library or design.

Related Commands ADD BLACK BOX DELETE NOTRANSLATE MODULES READ DESIGN READ LIBRARY REPORT NOTRANSLATE MODULES

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ADD OUTPUT EQUIVALENCES ADD OUtput Equivalences [-Invert ] [-ROot | -Module < name*> | -All] [-Golden | -Revised | -Both] (Setup Mode)

Specifies output pin equivalences or inverted pin equivalences on output boundary module pins. Conformal uses the equivalences when the parent module is being compared and the subsequent module is a blackbox. The first specified output pin is the representative pin. The remaining primary output pins refer to the representative pin in that added equivalence group. Effects on Comparison This command affects comparisons when you use add compared points -all. In that situation, Conformal merges the output pins specified with the ADD OUTPUT EQUIVALENCES command and then verifies them at the end of the comparison. Wildcard: The wildcard (*) represents any zero or more characters in output boundary module pin and module names.

Parameters primary_pin primary_pin*… Specifies a list of output boundary module pins that are equivalent. The first output pin is classified as the representative pin. The wildcard (*) is supported for the second pin. -Invert primary_pin*… Specifies a list of output boundary module pins that have inverted equivalences with respect to the representative pin. These inverted output pins are identified as (-) with the REPORT OUTPUT EQUIVALENCES command. The wildcard (*) is supported. -ROot

Adds output equivalences to the root module output pins. This is the default.

-Module name*

Adds output equivalences to the specified module output pins.

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-All

Adds output equivalences to “all” modules. -All applies within the given defaults.

-Golden

Adds output equivalences to the Golden design. This is the default.

-Revised

Adds output equivalences to the Revised design.

-Both

Adds output equivalences to both the Golden and Revised designs.

Related Commands ADD COMPARED POINTS DELETE OUTPUT EQUIVALENCES REPORT OUTPUT EQUIVALENCES

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ADD OUTPUT STUCK_AT ADD OUtput Stuck_at <0 | 1> [-ROot | -Module | -All] [-Golden | -Revised | -Both] (Setup Mode)

Places values at the output boundary module pins. This value has no effect on the current specified module comparison. However, Conformal uses the value when it compares the parent (or higher) module. Note: This command is limited to blackboxes. For a flat run, if the module is not blackboxed, all applied constraints will not take effect. Wildcard: The wildcard (*) represents any zero or more characters in boundary module pin and module names.

Parameters 0

Specifies that the output stuck_at value is 0.

1

Specifies that the output stuck_at value is 1.

primary_pin*…

Applies the stuck_at value to this list of output boundary module pins. The wildcard (*) is supported.

-ROot

Applies the output stuck_at value to the root module boundary pin. This is the default.

-Module name*

Applies the output stuck_at value to the specified module boundary pin. The wildcard (*) is supported.

-All

Applies the output stuck_at value to all output boundary module pins.

-Golden

Applies the output stuck_at value to the Golden design. This is the default.

-Revised

Applies the output stuck_at value to the Revised design.

-Both

Applies the output stuck_at value to both the Golden and Revised designs.

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Related Commands DELETE OUTPUT STUCK_AT REPORT OUTPUT STUCK_AT

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ADD PARTITION KEY_POINT ADD PArtition Key_point [-Pin |-Instance] < name… [-Golden |-Revised]] |gname0 rname0 gname1 rname1… -Pair> [-ALL_pattern | -ONE_Hot | -ONE_Cold] (Setup Mode)

Specifies the pin or instance names that partition the design into different compare iterations when the normal comparison process cannot finish. Execute this command before the WRITE PARTITION DOFILE command. ■

The -all_pattern option creates all possible binary combinations for n key points specified.

■

The -one_hot option creates all combinations where only one key point has a 1-state and the rest have a 0-state.

■

The -one_cold option creates combinations where only one key point has a 0-state and the rest have a 1-state. Important A maximum of 14 partition points can be added. If you try to add more than 14 partition points, then only the first 14 will be taken.

Parameters -Pin

Specifies that the partition key point names are pin names. This is the default.

-Instance

Specifies that the partition key point names are instance names.

name…

Specifies a list of partition pin or instance key point names.

-Golden

Specifies that the partition key points are in the Golden design. This is the default.

-Revised

Specifies that the partition key points are in the Revised design.

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-ALL_pattern

Applies all possible combinations of constraints to the partition key point names. This is the default.

-ONE_Hot

Applies a one-hot constraint to the partition key point names.

-ONE_Cold

Applies a one-cold constraint to the partition key point names.

Related Commands DELETE PARTITION KEY_POINT REPORT PARTITION KEY_POINT WRITE PARTITION DOFILE

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ADD PARTITION POINTS ADD PARtition Points < [-Net | -Pin | -GAte_instance | -ID] identifier... [-Pair] | -MODule | -INstance | -Datapath | -OUTPUT_TRIstate | -ALL > [-OUTPUT_port | -INPUT_port | -INTRA_operator] [-NAME] [-ABORT_cone [compare point ...] ] [-Cut | -NOCut] [-Golden | -Revised] [-EFFORT ] [-Verbose] (LEC Mode)

Note: This is a Conformal Ultra command. Adds partition (cut) points to the design. If a location in one design is specified, the Conformal software will attempt to find the corresponding point in the other design. If found, it adds a cut point to both the Golden and Revised designs. These cut points are automatically mapped. This command automatically handles inverted points. In the cases where the added cut points are not equivalent, you will need to diagnose them. If the non-equivalency is caused by the cut point, then you will need to delete that pair of cut points with the DELETE PARTITION POINTS command. After adding the partition points, you would normally run the ADD COMPARED POINTS -all command to add the cut points to the compare list. Note: If a cut point has already been added to a location, a second cut point cannot be added to the same location. If a specified point has more than one corresponding point in the design, the software will not add a cut point. Caution Adding cut points in LEC mode causes flattened netlists to change. As a result, all the gate IDs are subjected to change. Adding cut points does not affect the existing compare points list; however, all the compare data is invalidated after adding cut points.

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Parameters -Net

Specifies that the identifier is a net pathname.

-Pin

Specifies that the identifier is a pin pathname.

-GAte_instance

Specifies that the identifier is a gate-instance pathname.

-ID

Specifies that the identifier is a gate identification number. This number is an integer assigned automatically by Conformal. ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

identifier

Specifies the identifier for adding the partition point. If you do not specify -Net, -Pin, -GAte_instance, or -ID, the Conformal software automatically determines if the identifier is a gate-identification number, pin pathname, net pathname, or a gate-instance pathname.

-Pair

Allows specification of multiple pairs of identifiers, where the first identifier in each pair refers to the Golden design and the second identifier in each pair refers to the Revised design.

-MODule Adds partition points to all the instances of the specified module(s). -INstance Specifies the module instance pathname. By default, the partition points are all the output pins of the specified instance. Note: If an instance is removed during the Conformal flattening and modeling process, you cannot add partition points to the instance. -Datapath

Adds partition points to all module instances containing datapath operators. The datapath operator is the multiplier (including the merged operator) in the Golden design. By default, the partition points are all the output pins of the datapath operator(s).

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-OUTPUT_TRIstate

Specifies the partition points as the tri-state buffer at the primary output.

-ALL

Adds partition points to all possible locations. This is useful when resolving aborts.

-OUTPUT_port

Specifies the partition points as all the output pins of the module instance or datapath operator. This is the default.

-INPUT_port

Specifies the partition points as all the input pins of the module instance or datapath operator.

-INTRA_operator

Specifies the partition points as the gates inside the datapath operator.

-NAME

Adds partition points around instances using a name-based algorithm. This is faster than the default algorithm which adds partition points based on function. To perform a flat run with hierarchical partitioning, add partition points to all module instances using the following command: add partition points -instance * -name -input -output

To get better datapath quality, add partition points to all module instances containing datapath operators using the following command: add partition points -datapath -name -input -output

-ABORT_cone [compare point ...] Adds the specified partition points only in the fan-in logic cone of the specified compare points. If no compare point is specified, by default, the partition points are added in the fanin logic cone of all the compare points with abort or unknown results. Note: You must add compare points first to use this option. -CUT

Generates the cut gates in the flattened netlists for the feasible partition points in Golden and Revised design. This is the default.

-NOCUT

Does not generate any cut gates in flattened netlists.

-Golden

Specifies that the partition points are from the Golden design. This is the default.

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-Revised

Specifies that the partition points are from the Revised design.

-EFFORT Specifies the effort level for adding partition points. Increasing the effort level from Low to High will improve the quality of partition points being added, but will result in increased time. The default effort level is Medium. -Verbose

Reports the partition points with correspondences in the other design.

Examples ■

The following commands specify partition points in Golden and Revised design by pin pathnames: add partition points -pin i0_gold/sum[17] add compared points -all

■

i0_rev/z[17] -pair

The following commands specify the partition points in the Golden design. The commands will automatically find the corresponding gates in the Revised design, and if found, will physically add the cut gate pair in the flattened netlist. add partition points -pin i0/sum[17] i0/sum[16] -golden add compared points -all

■

The following commands specify the partition points from the output pins of multiplier operators in the Golden design. The commands will automatically find the correspondence gates in the Revised design, and add partition point pairs as cut gates in the flattened netlists. add partition points -datapath add compared points -all

■

The following command specifies an instance of datapath operator in the Golden design and add some gates inside the operator as partition points: add partition points -instance i0 -intra_operator

■

The following command specifies all the datapath operators in the Golden design and add some gates inside the operators as partition points: add partition points -datapath -intra_operator

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The following command adds partition points for all the tri-state buffers at the primary outputs: add partition points -output_tristate

■

The following command adds partition points to all instances of the DW_ module: add partition points -module DW_*

■

The following commands add partition points at all the possible locations in the fan-in logic cone of the compare points with abort or unknown compare results: add partition points -all -abort_cone add compared points -all

Related Commands ADD COMPARED POINTS DELETE PARTITION POINTS REPORT PARTITION POINTS

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ADD PIN CONSTRAINTS ADD PIn Constraints <0 | 1 | ONE_Hot | ONE_Cold | ZERO_ONE_Hot | ZERO_ONE_Cold> [-REPlace] [-ROot | -Module | -All] [-Golden | -Revised | -Both] (Setup Mode)

Constrains pins to a logic value or relationship. You can use this command on primary input pins, or compare two different designs under certain input constraints. The supported constraints are: ■

0-state

■

1-state

■

One-hot

■

One-cold

■

Zero-one-hot

■

Zero-one-cold

The one-hot constraint lets only one pin be at a 1-state and the remaining pins be at a 0-state. The one-cold constraint lets only one pin be at a 0-state and the remaining pins be at a 1-state. Wildcard: The wildcard (*) represents any zero or more characters in primary input and module names.

Parameters 0 | 1

Constrains pins to a constant 0 or 1 value.

ONE_Hot

Specifies that only one of the pins can have a high value.

ONE_Cold

Specifies that only one of the pins can have a low value.

ZERO_ONE_Hot

Specifies that all pins can have a low value, but only one can have a high value.

ZERO_ONE_Cold

Specifies that all pins can have a high value, but only one can have a low value.

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primary_pin*…

Specifies that a list of primary input names that will be constrained to a certain state. (These primary inputs are from either the Golden or Revised design.) The wildcard (*) is supported.

-REPlace

Changes the previously specified pin constraint.

-ROot

Applies the constraints to the root module(s). This is the default.

-Module name*

Applies the constraints to the specified module(s). The wildcard (*) is supported.

-All

Applies pin constraints to “all” modules. -All applies within the given defaults.

-Golden

Specifies that the primary input names are from the Golden design. This is the default.

-Revised

Specifies that the primary input names are from the Revised design.

-Both

Specifies that the primary input names are from both the Golden and Revised designs.

Related Commands DELETE PIN CONSTRAINTS REPORT PIN CONSTRAINTS

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ADD PIN EQUIVALENCES ADD PIn Equivalences < primary_pin primary_pin*…> [-Invert ] [-ROot | -Module | -All] [-INPUT_OUTPUT] [-User | -Hier] [-Golden | -REvised | -Both] (Setup Mode)

Defines the relationship between pins; specifies whether module pins are equal or inverted. Use this command to complete logic abstraction or to resolve differences in logic during comparisons. Note: Pin equivalences are considered only when the pin equivalences are on a root module. If a submodule has black-box pin equivalences, the Conformal Equivalence Checker checks to see if they are true when you use the ADD COMPARE POINT -all command. Wildcard: The wildcard (*) represents any zero or more characters in primary input and module names. Wildcards are not valid for buses.

Parameters primary_pin primary_pin*… Specifies a list of primary input pins that are equivalent. The first input pin is classified as the representative pin. The wildcard (*) is supported for the second pin. -Invert primary_pin*… Specifies that the primary pins are inverted with respect to the referenced primary pin. Use the REPORT PIN EQUIVALENCES command to identify the inverted primary input pins. The (-) denotes inverted pins. The wildcard (*) is supported. -ROot

Applies the pin equivalences to the root module. This is the default.

-Module name*

Applies the pin equivalences to the specified module. The default is the root module. You can also use this command on buses, by defining the bus range using .

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-All

Applies the pin equivalences to “all” the modules. -All applies within the given defaults.

-INPUT_OUTPUT

Enables the handling of internal signals that pass in and out of the same module. With this option, you can also constrain an output pin of a blackbox to be equivalent to an input pin. Note: The representative pin should always be driving all the equivalent pins.

-User

When you use this option, Conformal includes these added pin equivalences in the comparison, when the corresponding module is a blackbox. (This option does not apply to primary inputs.) This is the default.

-Hier

When you use this option, Conformal does not do the additional check associated with the -user option.

-Golden

Specifies that the pin equivalences are from the Golden design. This is the default.

-Revised

Specifies that the pin equivalences are from the Revised design.

-Both

Specifies that the pins specified as equivalent exist in both the Golden and Revised designs. Note: If you use the -both option, every primary input pin you list must exist in both designs (Golden and Revised). Otherwise, Conformal returns an error message.

Example The following example implies that p1, p2, and p3 are equivalent and are inverted to p4, p5, and p6. add pin equivalences p1 p2 p3 -inv p4 p5 p6

Related Commands DELETE PIN EQUIVALENCES REPORT PIN EQUIVALENCES

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ADD PRIMARY INPUT ADD PRimary Input < pathname* [-Net] | pathname -Pin> [-Cut | -NOCut] [-Golden | -Revised | -Both] (Setup Mode)

Adds a new primary input pin to a specified net or pin name. This new primary input pin is classified in the User class of primary inputs. (The original primary inputs of the design are classified in the System class of primary inputs.) Use the -cut option if the added primary input is the only driver to the net or pin. Otherwise, along with the other original drivers, the net becomes a wired net. Wildcard: The wildcard (*) represents any zero or more characters in net paths.

Parameters pathname* -Net

Adds the primary input to the specified net path. -Net is the default.

pathname -Pin

Adds the primary input to the specified pin path.

-Cut

Cuts the other original drivers of the specified path and allow only the newly added primary input as the driver of the net or pin. This is the default.

-NOCut

Does not cut the other original drivers of the specified net or pin name. This option makes the new net a wired net.

-Golden

Adds the new primary input in the Golden design. This is the default.

-Revised

Adds the new primary input in the Revised design.

-Both

Adds the new primary input in both the Golden and Revised designs.

Related Commands DELETE PRIMARY INPUTS REPORT PRIMARY INPUTS

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ADD PRIMARY OUTPUT ADD PRimary Output [-Golden | -Revised | -Both] (Setup Mode)

Adds a new primary output pin to a specified net name. This new primary output pin is classified in the User class of primary outputs. (The original primary outputs of the design are classified in the System class of primary outputs.) This command is used for diagnosis when an internal value can be observed at a primary output. Wildcard: The wildcard (*) represents any zero or more characters in net paths.

Parameters net_pathname*

Adds the primary output to the specified net path. The wildcard (*) is supported.

-Golden

Adds the new primary output in the Golden design. This is the default.

-Revised

Adds the new primary output in the Revised design.

-Both

Adds the new primary output in both the Golden and Revised designs.

Related Commands DELETE PRIMARY OUTPUTS REPORT PRIMARY OUTPUTS

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ADD RENAMING RULE ADD REnaming Rule [[-PIN_MULTIDIM_TO_1DIM] [-ADD | -NOADD] [-NOASCEND | -ASCEND] [-VERBOSE] ] [ [[ -MAp ] [-TYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>… |-NOTYpe …] |-MOdule |-PIn [-BBox ] ] [-REPlace] [-Golden | -Revised | -BOth] ] (Setup / LEC Mode)

Specifies renaming rules for key point mapping, module renaming (when reading in the library and designs for hierarchical comparisons), and pin renaming for blackboxes Use the REPORT RENAMING RULE command to display the list of all renaming rules. Conformal applies renaming rules sequentially, in the order they were added. Key Point Mapping When you define renaming rules in the Setup system mode, they guide the automatic mapping process that occurs during the system mode switch from Setup to LEC. When you are in the LEC system mode, and find that the key point mapping is not complete, define additional renaming rules and repeat key point mapping to improve the mapping results. The automatic mapping process refers to the naming specified by the final renaming rules. Module Renaming You must use this command before the READ LIBRARY and READ DESIGN commands. It helps map modules together for hierarchical comparisons. Pin Renaming This command applies to the specified blackbox or to all blackboxes, which is the default.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Renaming Rule Structure When defining renaming rules, the first string specifies the pattern to be matched; the second string specifies how Conformal is to rename or make substitutions. The first string can contain expressions of the following types: %d

Matches one or more digits, [0-9]+

%a

Matches one or more alphabetical characters, [a-zA-Z]+

%s

Matches one or more digits or alphabetical characters, [0-9a-zA-Z]+

%u

Matches one or more alphabetical characters or underscores, [a-zA-Z_]+

%w

Matches one or more digits or alphabetical characters or underscores, [0-9a-zA-Z_]+

x

Matches character “x”

abc

Matches string “abc”

.

Matches any single character

*

Matches zero or more repetitions of the preceding expression

+

Matches one or more repetitions of the preceding expression

^bol

Matches “bol” only when it occurs at the beginning of a string

eol$

Matches “eol” only when it occurs at the end of a string

x|abc

Matches “x” or “abc”

[oz!]

Matches “o”, “z”, or “!”

(pattern)

Matches anything that is matched by “pattern” and renders it referable (through @n) in the substitution string

Any character can be preceded by the escape character “\” to cancel any special meaning it has. Use the escape character whenever any of the following special characters represents a simple character. %

.

*

+

^

$

|

(

)

[

]

\

The second string can contain expressions of the following types: abc

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Replaces string “abc” for each matched string

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@n

Replaces the string that matches the nth %d, %a, %s, or a pattern enclosed in parentheses. The n is a digit other than 0, and you can use @{nn} to refer to further matches (that is, 10…99)

#(expr)

Where “expr” is an arbitrary expression that can only contain constant integers, @n expressions, and the operators +,-,*, / and ( )

The following table shows implementation examples for various pattern-matching and substitution strings. For pattern-matching strings, use parentheses to group individual patterns into a single pattern, as demonstrated in the example (ab|de)*. First String

Second String

Source

Result

%a%d

@1[@2]

xyz123

xyz[123]

%a_%d

@1[@2]

arr_5

arr[5]

_z_

/

_z_top_z_inst

/top/inst

XYZ

abcabc

XYZabc

abc$

XYZ

abcabc

abcXYZ

âbc$

XYZ

abcabc

abcabc

âbc$

XYZ

abc

XYZ

[oz!]

$

aaoaazaa!aa

aa$aa$aa$aa

\%d\%s

AA

%a%d%s%b

%aAA%b

\(ab

ZZ

xx(abcd

xxZZcd

%s\.%d

@1[@2]

xx.123

xx[123]

(x|abc)

YY

abcx abcx

YYYY YYYY

(ab|de)*

YY

ababdeab

YY

%s%d

@1[#(7-@2)]

abc3

abc[4]

%s%d

@1[#(2*@2)]

abc5

abc[10]

reg%d\[%d\]

reg[@2]

reg2[5]

reg[5]

âbc

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Important Do not include the forward slash, “/”, at the top level for either the first or second string. For example, express /top_module/adder/reg[5] as top_module/adder/reg[5].

Parameters -PIN_MULTIDIM_TO_1DIM Allows you to create renaming rules to map multidimensional array pins to one-dimensional array pins. -ADD

Shows the pins found when adding the rules into the system. This is the default.

-NOADD

Shows the pins found without adding the rules.

-NOASCEND

Renames the pins in an descending order. This is the default.

-ASCEND

Renames the pins in an ascending order.

-VERBOSE

Shows the renaming patterns.

rule_name

Specifies a rule identification name assigned to a specific renaming rule.

The first string represents the pattern to be matched. The second string represents the substitution pattern.

-MAp

Specifies that the renaming rule applies to key point mapping. This is the default.

-TYpe keypoint_type… Renames all key points with the specified type. The available types are as follows:

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PI

Primary Inputs

E

TIE-E gates

Z

TIE-Z gates

DFF

D flip-flops

DLAT

D-latches

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CUT

Artificial gates for breaking combinational feedback loops

BBOX

Blackboxes

PO

Primary Outputs

-NOTYpe keypoint_type… Renames all key points except the specified types. The available types are as follows: PI

Primary Inputs

E

TIE-E gates

Z

TIE-Z gates

DFF

D flip-flops

DLAT

D-latches

CUT


BBOX

Blackboxes

PO

Primary Outputs

-MOdule

Specifies that the renaming rule applies to module renaming when the library and design are read in.

-PIn

Specifies that the renaming rule applies to pin names of blackboxes.

-BBox module_name

Specifies that the pin renaming rules apply to the specified blackbox module.

-REPlace

Allows the redefinition of an existing renaming rule. Tip The difference between using add renaming rule -replace as opposed to using delete renaming rule followed by add renaming rule is that renaming rules that are redefined remain in the same position in the list of renaming rules. By deleting and adding a rule, the new definition will appear at the end of the list. In some cases, the order in which renaming rules are applied might affect the result.

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-Golden

Specifies that the renaming rule applies to the Golden design. This is the default.

-Revised

Specifies that the renaming rule applies to the Revised design.

-BOth

Specifies that the renaming rule applies to both the Golden and Revised designs.

Example In the following command, y2[1:0][2:0] in module test2 is renamed y2[5:0]: add renaming rule -pin_multidim_to_1dim // Rule created for (test2) y2[1:0][2:0] // Rule created for (test1) y1[1:0][1:0] // Rule created for (top) y2[1:0][2:0] // Rule created for (top) y1[1:0][1:0] // Rule created for (top) ym[2:3][2:0][1:0] // 5 rules created. Rules for top module must be manually validated.

You can use the REPORT RENAMING RULE command to view the added rules.

Related Commands CHANGE NAME DELETE RENAMING RULE MAP KEY POINTS READ DESIGN READ LIBRARY REPORT RENAMING RULE SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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ADD RETENTION MAPPING ADD REtention Mapping <-Module | -Instance |-NOTag | -Tag -Tag ... > <-NOAttribute | -Attribute > [-TYpe ] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Adds the state retention mapping rules for validation of technology mapping of the sequential elements (DFFs or DLATs) from RTL to gate-level, gate-level to gate-level, or RTL to RTL. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 143.

Parameters rule_name

Specifies a rule identification name assigned to a specific retention mapping rule.

-Module

Specifies the module name in the Golden design. All the DFFs or DLATs under the named module will be subjected to this rule.

-Instance

Specifies the instance pathname in the Golden design. Here instance pathname refers to only DFF or DLAT instances. The named DFF or DLAT instance(s) would be subjected to this rule. Wildcards (*) are supported for the instance pathname. When using a wildcard, it might point to multiple instances.

-Tag

Specifies the tag name in the RTL golden side. The ’tag name’ refers to the label names used with a) ’process’ blocks in the VHDL RTL and b) ’always’ blocks in the Verilog RTL. All the DFFs or DLATs under the tag-named block will be subjected to this rule. Wildcards (*) are supported.

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-NOTag

When the Golden side is an RTL design, this implies that all the DFFs or DLATs which do not have any tag-name associated with their ’process’ or ’always’ block will be subjected to this rule.

-Attribute

Specifies the ’power gating cell attribute’ for the DFFs or DLATs in the Revised netlist. Different power gating cell attributes are defined for different sets of retention cells in the Synopsys library (liberty format). When synthesized (technology mapped), the DFFs or DLATs in the Golden design (specified using module-name, instance-name, or tag-name) should have the named attribute in Revised netlist.

-NOAttribute

Specifies that, when synthesized (technology mapped), the DFFs or DLATs in the Golden design (specified using module-name, instance-name, or tag-name) should not have any attribute (power gating cell attribute) in Revised netlist. In other words, the specified DFFs or DLATs should be technology mapped as ordinary or non-retention cells.

-TYpe Indicates the sequential element type on which to apply the retention mapping rule. ALL applies the retention mapping rule to all sequential elements (both DFF and DLAT type). This is the command default when you do not specify the -TYpe option. DFF applies the retention mapping rule to DFFs only, and DLAT applies the retention mapping rule to DLATs only.

Examples ■

The following command verifies that all registers with a tag label lp_sel* are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF1: add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1

■

The following command verifies that all registers in module blockA are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF1: add retention mapping R1 -module dma -attribute LPRET_DFF1

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The following command verifies that all registers with instance name /U0/*/fifo_dma* are implemented with a state retention cell whose power_gating_cell attribute is LPRET_DFF2: add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2

Related Commands CHECK LOWPOWER CELLS DELETE RETENTION MAPPING REPORT RETENTION MAPPING

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ADD SEARCH PATH ADD SEarch Path [ |-Design | -Library] [-Both | -Golden | -Revised] (Setup Mode)

Defines additional search paths outside the current directory for filenames you use in the READ DESIGN and READ LIBRARY commands. This command is necessary because the default is to search for filenames in the current directory; but your design or library can include filenames that are housed in other directories. When you add multiple search paths to the list, Conformal does the search in the order paths were added to the list. Use the REPORT SEARCH PATH command to display all search paths. Use the tilde character (~) to shorten the specified path.

Parameters pathname…

Specifies the search path for filenames used in the READ DESIGN and READ LIBRARY commands.

-Design

The READ DESIGN command uses the specified search path. If you do not specify -library or -design, Conformal applies this command to both the READ DESIGN and READ LIBRARY commands.

-Library

The READ LIBRARY command uses the specified search path. If you do not specify -library or -design, Conformal applies this command to both the READ DESIGN and READ LIBRARY commands.

-Both

Specifies that the search path applies to both the Golden and Revised designs. This is the default.

-Golden

Specifies that the search path applies to the Golden design and library.

-Revised

Specifies that the search path applies to the Revised design and library.

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Related Commands DELETE SEARCH PATH READ DESIGN READ LIBRARY REPORT SEARCH PATH

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ADD SUPPLY ADD SUpply <-power | -ground> [-port [-root | -Module ] | -global] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Defines power/ground ports of a module or the global power/ground signals for the entire design.

Parameters -power

Specifies that the listed names have a VDD attribute.

-ground

Specifies that the listed names have a GND attribute.

-port

Specifies that the listed names are module ports.

-root

Specifies that the listed names reside in the root module. By default, all modules will be applied.

-Module

Specifies that the listed names reside in the specified module. By default, all modules will be applied.

-global

Specifies that the listed names are global signals. This is the default.

...

Specifies that a list of net/port names that will be specified as VDD or GND.

-Golden

Specifies that the listed names are from the Golden design.

-Revised

Specifies that the listed names are from the Revised design.

Examples Instead of specifying .global in a spice netlist, the following commands command have the same effect: add supply -power VDD add supply -ground GND

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Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE SET ABSTRACT MODEL

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ADD TIED SIGNALS ADD TIed Signals <0 | 1> [-Net | -Pin] [-ROot | -Module | -All] [ |-Design |-Library] [-Golden | -Revised | -Both] (Setup Mode)

Assigns the specified floating nets or pins to a 0-state or a 1-state in the Golden or Revised design. These tied signals are classified in the User class of tied signals. The original tied signals of the design are classified in the System class of tied signals. Wildcard: The wildcard (*) represents any zero or more characters in net, pin, and module names.

Parameters 0

Ties the floating nets or pins to a 0-state.

1

Ties the floating nets or pins to a 1-state.

name*…

Specifies a list of names that correspond to either floating nets or floating pins where you intend to add the tied signal.

-Net

Specifies that the listed names are net names. This is the default.

-Pin

Specifies that the listed names are pin names.

-ROot

Specifies that the floating net or pin resides in the current root module. This is the default.

-Module name*

Specifies that the floating net or pin resides in the specified module. The default is the root module. The wildcard (*) is supported.

-All

Applies the tied signals to “all” the modules. -All applies within the given defaults.

-Design

Applies the tied signals to the design. If you do not specify -design or -library, Conformal applies tied signals to both designs and libraries.

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-Library

Applies the tied signals to the library. If you do not specify -design or -library, Conformal applies tied signals to both designs and libraries.

-Golden

Adds the tied signals to the Golden design. This is the default.

-Revised

Adds the tied signals to the Revised design.

-Both

Adds the tied signals to both the Golden and Revised designs.

Related Commands DELETE TIED SIGNALS REPORT FLOATING SIGNALS REPORT TIED SIGNALS

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ANALYZE ABORT ANAlyze ABort [-All | < ... [-Golden | -Revised]> | -Number ] [-Summary | -Verbose | -COmpare] [-CLass ] (LEC Mode)

Note: This is a Conformal Ultra command. Analyzes abort points and recommends actions to help solve the abort points. This command can also provide useful information for further abort investigation.

Parameters -ALL

Analyzes all abort points. This is the default.

gate_id

Specifies the gate ID for abort analysis.

instance_pathname

Specifies the instance pathname for abort analysis.

pin_pathname

Specifies the pin pathname for abort analysis.

-Golden

Specifies whether the gate ID or pathname is in the Golden design. This is the default.

-Revised

Specifies whether the gate ID or pathname is in the Revised design.

-Number

Specifies the number of abort points to analyze.

-Summary

Prints out the summary count of the abort points. This is the default.

-Verbose

Prints out additional information, such as RTL statistics.

-COmpare

Automatically compares the aborted points. Cadence recommends using this option when running the ANALYZE ABORT command.

-CLass Specifies the class of points to analyze. Select Abort to analyze abort points, or Notcompared to analyze not-compared points.

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Example The following commands run abort analysis after the initial compare: compare analyze abort -compare

Related Commands COMPARE RUN HIER_COMPARE SET ANALYZE OPTION

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ANALYZE DATAPATH ANAlyze DAtapath [-MODULE [-RESOURCEFILE ]] [-MERGE | -NOMERGE] [-NOSHARE | -SHARE] [-EFFort ] [-SHARE_OPerator ] [-NOADDERTREE | -ADDERTREE] [-Verbose] (LEC Mode)

Note: This is a Conformal Ultra command. Analyzes datapath modules. Based on the results of the analysis, Conformal can automatically resolve multipliers, operator merging, and resource sharing problems. Note: You cannot run datapath analysis without first mapping the Revised design keypoints to the Golden design keypoints.

Parameters -MODULE

Applies analysis on the datapath modules. The default is in the Revised design netlist.

-RESOURCEFILE Specifies the resource filename to analyze the datapath modules. -MERGE

Applies the operator merging technique. This is the default.

-NOMERGE

Does not apply the operator merging technique.

-NOSHARE

Does not apply the resource sharing technique. This is the default.

-SHARE

Analyzes the design for datapath resource sharing.

-SHARE_OPerator

Shares the specified operators. See the example for the recommended flow. Note: If this option is specified, only the sharing is performed, and does not run datapath analysis.

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-EFFort Specifies the effort level. Choose MEDium (the default), or HIgh to help provide better analysis of some multipliers, but might increase the analysis runtime. -NOADDERTREE

Does not automatically add parentheses to the input operands of adder trees. This is the default.

-ADDERTREE

Automatically adds parentheses to the input operands of adder trees.

-Verbose

Provides additional information.

Example ■

The following commands show an example of the recommended flow when using the -SHARE_OPerator option: analyze datapath -verbose -share_operator mult_30 mult_31 // Note: mult_30: shared analyze datapath -verbose -share_operator mult_32 mult_33 // Note: mult_32: shared analyze datapath -verbose // Note: add_2(clustered): quality evaluated 70% success // Note: mult_30: quality evaluated 80% success // Note: mult_32: quality evaluated 100% success

■

The following commands apply datapath module-based analysis followed by the datapath operator-level analysis: analyze datapath -verbose -module -resourcefile resourcefile.name analyze datapath -verbose

Related Commands ANALYZE MULTIPLIER REPORT DATAPATH OPTION REPORT DATAPATH RESOURCE REPORT MULTIPLIER OPTION SET DATAPATH OPTION

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Encounter Conformal Equivalence Checking Reference Manual Command Reference SET MULTIPLIER IMPLEMENTATION SET MULTIPLIER OPTION WRITE HIER_COMPARE DOFILE

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ANALYZE ECO ANAlyze ECo [-REPlace] [-EFFort ] [-PRESERVE_clock] (LEC Mode)

Analyzes the ECO change in the Revised root module comparing to the Golden root module. The logic change is written to the specified patch file, which contains the Verilog module with the port names corresponding to the nets in the Golden design. Note: Only the logic cone under Non-EQ points are analyzed by the command.

Parameters

Specifies the name of the patch file.

-REPlace

Replaces the existing file.

[-EFFort ] Specifies the analysis effort level. The command default is HIGH. -PRESERVE_clock

Attempts to minimize the changes to the clock network.

Examples In the following commands, module G1 contains the placed and routed netlist, and module G2 contains the synthesized netlist from modified RTL. The two netlist will be compared first, then the ANALYZE ECO command will analyze the change implemented by G2 and generates a patch file, which contains a single Verilog module G1_eco. The patch can then can be read back and applied to G1 with the APPLY PATCH command, such that the G1 will be equivalent to G2, meaning that G1 implements the ECO change in G2. Note: The patch can be remapped or optimized by other tools before it is read back. SETUP> set root module G1 -golden SETUP> set root module G2 -revised SETUP> set system mode lec LEC> add compare point -all LEC> compare LEC> analyze eco patch.v -replace

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Encounter Conformal Equivalence Checking Reference Manual Command Reference SETUP> set system mode setup SETUP> read design patch.v -append SETUP> apply patch G1 G1_eco

Related Commands ADD ECO PATCH APPLY PATCH COMPARE WRITE HIER_COMPARE DOFILE

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ANALYZE IMPLICATION ANAlyze IMplication [-ONE | -1 ] [-ZERO | -0 ] [-ADD <-ONE | -1 | -ZERO | -0> ] [-DELete ] [-CHECK_Redundancy ] [-CHECK_Constant ] [-Block ] [-DEPTH ] [-Golden | -Revised] (LEC Mode)

Note: This is a Conformal Ultra command. Analyzes implication values on the design. If you assign value(s) on certain gate(s), this command shows what the necessary values are on other gates to satisfy the assignment. It can also show if a gate has redundant fanin and if a gate is a constant gate. The results are displayed in the schematic view with the following colors: ■

Blue: initial assignments

■

Green: current implication values

■

Red: gates on the conflict path

■

Purple: location where conflict occurred

In the schematic view, you can also right click the gate and set a value. Holding the mouse pointer on a gate, an information box will show if this gate has redundant fanin and if it is a constant gate.

Parameters -ONE | -1

Specifies that the following gate(s) will be assigned one.

-ZERO | -0

Specifies that the following gate(s) will be assigned zero.

-ADD

Specifies that the following assignment(s) will be added into previous assignment(s).

-DELete

Specifies that the following gate(s) will be removed from previous assignment(s).

-CHECK_Redundacy

Checks the specified gate to see if it has redundant fanins.

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-CHECK_Constant

Checks the specified gate to see if it is constant gate.

-Block

Blocks the gate(s) so that implication will not go across it.

-DEPTH

Specifies the logic depth beyond which implication will not be performed. The default value is 10.

-Golden

Specifies that the gate IDs are from the Golden design. This is the default.

-Revised

Specifies that the gate IDs are from the Revised design.


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ANALYZE MULTIPLIER ANAlyze MUltiplier [-NOCDP_INFO | -CDP_INFO] (LEC Mode)

Initiates an analysis of multiplier modules. Based on the results of the analysis, Conformal can automatically resolve architecture mismatches and operand swapping problems. Additionally, use the -cdp_info option if you want Conformal to let you know when Conformal Ultra will be helpful. Use this command after switching from Setup to LEC mode: set system mode lec … analyze multiplier -cdp_info add compared points -all compare

Parameters -NOCDP_INFO

Does not display a message when Conformal Ultra can enhance multiplier analysis. This is the default.

-CDP_INFO

Displays a message when Conformal Ultra can enhance multiplier analysis.

Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT DATAPATH OPTION REPORT DATAPATH RESOURCE REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION

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ANALYZE NONEQUIVALENT ANAlyze NOnequivalent [ | | ... [-Golden | -Revised] ] [-Summary | -Verbose] (LEC Mode)

Note: This is a Conformal Ultra command. Helps identify the possible causes of non-equivalent compared points.

Parameters

Analyzes non-equivalent compared points for the specified gate.

... Analyzes non-equivalent compared points for the specified instance. -Golden

Analyzes non-equivalent compared points in the Golden design. This is the default.

-Revised

Analyzes non-equivalent compared points in the Revised design.

-Summary

Provides a summary of the analysis. This is the default.

-Verbose

Provides additional information for each individual non-equivalent compared point.

Examples The following shows an example of a report when running the ANALYZE NONEQUIVALENT command. The lines in bold indicate the cause of the problems: LEC> analyze noneq 213 //Command analyze noneq 213 Analyzing non-equivalent compared points: (G) + 213 DFF /wbs/hvlen_reg[28] (R) + 6277 DFF /wbs/hvlen_reg[28]/U$1 The clock of DFF in Golden is not gated. The clock of DFF in Revised is gated. Analysis of non-equivalent compared points: May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Gated clock of of DFF or DLAT. (Occurrence: 1) Unknown reason. (Occurrence: 1) LEC> analyze noneq 170 -revised //Command analyze noneq 170 -revised Analyzing non-equivalent compared points: (G) + 167 PO /wbm_sel_o[0] (R) + 170 PO /wbm_sel_o[0] Following constraints may be necessary: Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0] Analysis of non-equivalent compared points: Sequential constant. (Occurrence: 1) Unknown reason. (Occurrence: 1)

Clock Gating You can fix the first problem in the report: The clock of DFF in Golden is not gated. The clock of DFF in Revised is gated.

by running the following command in Setup mode: set analyze option -auto

or the following command in LEC mode: analyze setup

Sequential Constant You can fix the second problem in the report: Following constraints may be necessary: Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]

by running auto analysis in Setup mode with the following commands: set analyze option -auto set flatten model -seq_constant

or the following command in LEC mode: remodel -seq_constant

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ANALYZE POWER ASSOCIATION ANAlyze POwer Association [-Golden | -Revised] [-Module ...>] [-OUT_Dofile | -OUT_CPF ] [-REPlace] (Setup / Verify Mode)

Note: This is a Conformal Custom command. Analyzes the module’s SPICE netlist and identifies the power/ground pin for each input and output pin with which it is associated. Notes: ■

The power/ground pin definition can come from LEF or SPICE.

■

Run the SET SPICE OPTION -NOBULK command before reading in the SPICE design to maintain the connectivity of power/ground ports.

■

Each input or output pin can have only one associated power/ground pin. Multiple power/ground pin association are ignored.

Parameters -Golden

Analyze the Golden design. This is the default.

-Revised

Analyze the Revised design.

-Module ...> Specifies the module(s) to be analyzed. Without this option, all modules in the design are analyzed. This accepts wildcards. -OUT_Dofile Specifies the file to output the ADD POWER ASSOCIATION command. -OUT_CPF Specifies the output CPF file. -REPlace

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Replaces the specified -OUT_Dofile or -OUT_CPF file if it already exists.

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Related Commands READ DESIGN -spice SET SPICE OPTION

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ANALYZE RETIMING ANAlyze REtiming [-COMBinational_identical] [-PIPELINE [] [-BACKWARD] ] [-GENERAL] [-MERGE | -NOMERGE] [-DIAGNOSIS [-BACKWARD] ] [-VERBose] [-BOth | -GOLden | -REVised] (LEC Mode)

Note: This is a Conformal Ultra command. Initiates pipeline retiming, retiming for RC synthesized netlist, or retiming for designs that are combinationally equivalent. Normally, you use this command to retime a Revised design to match a referenced Golden design. If this command is successful, you can use the COMPARE command to ensure that the two designs are equivalent. If this command is unsuccessful, then the original retiming you performed is incorrect. For more guidelines and examples, see “Conformal Ultra: Advanced LEC Capabilities” in the Encounter Conformal Equivalence Checking User Guide.

Parameters -COMBinational_identical Use this option on combinationally equivalent designs. Use option when you have retimed a design and want to confirm that it is equivalent to another design. Conformal retimes its registers to match their position in the reference design. Note: If you specify this option, it must be the first option in the command line. Tip If you can replace the DFF -> Q connections with buffers and your designs are still identical, then your Golden and Revised designs are considered combinationally equivalent.

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-PIPELINE -BACKWARD Moves all registers to the primary output side of the design as much as possible, or use the option to specify one or more registers, separated by a space. The wildcard (*) is accepted. -BACKWARD moves registers backward to the primary input side of the design as much as possible. With this option, pipeline backward retiming can be performed on either all registers or a selected set of registers. -GENERAL

Retimes the Revised design to match the registers on the Golden side. Registers in the Golden design will not be retimed.

-MERGE

Specifies that equivalent registers are merged after registers are moved, including inverted-equivalent registers. This helps to reduce the unmapped register keypoints and the resulting false non-equivalences. This is the default.

-NOMERGE

Disables the merging of equivalent registers after they are moved.

-DIAGNOSIS -BACKWARD Checks that a register can be retimed a step forward or backward. If the retime movement cannot succeed, the reason for the failure is reported. By default, this diagnoses the forward retiming step. Note: This option will not change the netlist, it only provides information about the specified retiming step. -BACKWARD specifies that the backward retiming step is diagnosed. -VERbose

Prints additional information, including a list of current tasks and statistics.

-BOTh

Executes this command on both the Golden and Revised designs. This is the default.

-REVised

Executes this command on the Revised design and uses the Golden design as the reference design.

-GOLden

Executes this command on the Golden design and uses the Revised design as the reference design.

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Examples The following command initiates backward pipeline retiming for register r1 and registers whose identifiers begin with r2, such as r2a and r21, in the Revised design: analyze retiming -pipeline r1 r2* \ -revised -backward

The following demonstrates how to use the ANALYZE RETIMING -comb_identical command with other commands. 1. Read in your library. SETUP> read lib -lib matrox_test1.lib // Parsing file matrox_test1.lib ... // Note: Read Liberty library successfully

2. Read in your Golden and Revised designs. SETUP> read design -golden matrox_test1_brt.v // Parsing file matrox_test1_brt.v ... // Golden root module is set to ’hst_ssurfdes’ // Note: Read VERILOG design successfully SETUP> read design -revised matrox_test1_art.v // Parsing file matrox_test1_art.v ... // Revised root module is set to ’hst_ssurfdes’ // Note: Read VERILOG design successfully

3. Switch to LEC mode. SETUP> set system mode LEC // Processing Golden ... // Modeling Golden ... // Processing Revised ... // Modeling Revised ... // Mapping key points ... . . .

4. Use the ANALYZE RETIMING -comb_identical command and attempt to retime the Revised design to match the Golden design. LEC> analyze retiming -combinational_identical // Retimed successfully 859 registers in Revised as 141 registers // All comparison points have been deleted // All key points have been unmapped // Mapping key points ... =========================================================================== Mapped points: SYSTEM class --------------------------------------------------------------------------Mapped points PI PO DFF Total --------------------------------------------------------------------------Golden 1632 29 147 1808 --------------------------------------------------------------------------Revised 1632 29 147 1808 ===========================================================================

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 5. Add “all” mapped points, excluding primary inputs, as compare points. LEC> add comp points -all // 176 compared points added to compare list

6. Use the COMPARE command to start the equivalency checking comparison. LEC> compare =========================================================================== Compared points PO DFF Total --------------------------------------------------------------------------Equivalent 29 147 176 ===========================================================================

Related Commands ADD COMPARED POINTS ADD MODULE ATTRIBUTE COMPARE

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ANALYZE SETUP ANAlyze SEtup [-NOCUT | -CUT] [-NOLIBRARY_VERIFICATION | -LIBRARY_VERIFICATION] [-VERBose] (LEC Mode)

Note: This is a Conformal Ultra command. Automatically resolves the setup related issues so that non-equivalency due to incorrect setup can be prevented or resolved. Note: To resolve sequential constant optimization with this command, you must use the following command: set flatten model -seq_constant

Parameters -NOCUT

Does not analyze loop cutting. This is the default.

-CUT

Analyzes loop cutting. When creating flattened netlists, the Conformal software breaks all loops by inserting CUT gates, which could cause false non-equivalences. With this option, you can resolve these false non-equivalences.

-NOLIBRARY_VERIFICATION Does not perform setup analysis for library cell verification. This is the default. -LIBRARY_VERIFICATION Performs setup analysis for library cell verification. -VERBose


Related Commands ANALYZE NONEQUIVALENT SET ANALYZE OPTION

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APPLY PATCH APPly PAtch [-KEEPHierarchy] [-NETnaming ] [-INStancenaming ] [-SEQuentialnaming ] [-Golden | -Revised] (Setup Mode)

Applies the ECO change specified in the patch module, generated by the ANALYZE ECO command, to the module under ECO. The patched module can be written out with the WRITE DESIGN command. Note: The patch generated by the ANALYZE ECO command can contain unmapped primitives. You can use the synthesis tool or the MAP ECO PATCH command to map the patch.

Parameters Specifies the name of the module being changed for ECO. Specifies the name of the patch module containing the ECO changes. -KEEPHierarchy

Specifies that the ECO changes will be put in a submodule.

-NETnaming Specifies the net naming format of the ECO nets. For example, for eco_net_%d, the %d will be an integer that makes the net name unique. -INStancenaming Specifies the instance naming format of the ECO combinational cells. For example, for eco_instance_%d, the %d will be an integer that makes the instance name unique. -SEQuentialnaming Specifies the instance naming format of the ECO registers and latches. For example, eco_%s, where %s is the original register name. -Golden May 2008

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-Revised


Examples For a set of sample commands that shows this command and related commands in context, see the example for ADD BLACK BOX on page 37.

Related Commands MAP ECO PATCH OPTIMIZE PATCH

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ASSIGN PIN DIRECTION ASSign PIn Direction [-Golden | -Revised | -Both] [-FROM_DIr ] (Setup Mode)

Defines a module pin’s direction. SPICE netlist ports do not have direction, unless you supply *.pininfo : as a CDL comment and read it in as an inout. Abstraction analyzes the circuit and assigns pin direction—when determinable. In some cases, you need to assign pin direction manually to complete abstraction. Note: You can use this command instead of the ADD MOS DIRECTION command to assist abstraction. Wildcard: The wildcard (*) represents any zero or more characters in pin names.

Parameters IN

Specifies that the assigned pin direction is input.

OUT

Specifies that the assigned pin direction is output.

IO

Specifies that the assigned pin direction is I/O.

module_name

Specifies that the pin resides in the specified module.

pin_name*

Assigns a direction to the specified pin.

-Golden

Assigns the pin direction to the Golden design. This is the default.

-Revised

Assigns the pin direction to the Revised design.

-Both

Assigns the pin direction to both the Golden and Revised designs.

-FROM_DIr

Only pins which have the direction specified by this option’s argument will be redirected.

Examples assign pin direction in mux2p sela -revised assign pin direction out mux4p y -golden

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Encounter Conformal Equivalence Checking Reference Manual Command Reference assign pin direction in mux2p sela y -both //Assigns direction to pins sela and y. assign pin direction IN mod pin_* -from_type IO //Changes all IO pins whose name matches ‘pin_*’ in //module ‘mod’ to IN pins on the golden side.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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BACKWARD BACkward [integer] (LEC Mode)

Reports fanin gate information from the currently displayed flattened gate information. The fanin gate you choose with this command becomes the current flattened gate. Use this command to trace gates in place of repeatedly using the REPORT GATE command. Note: This command does not report gates at the design level.

Parameters integer

Specifies which fanin gate is reported. The value 1 denotes the first fanin. The default value is 1.

Related Commands FORWARD REPORT GATE

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BREAK BREak (Setup / LEC Mode)

Terminates the dofile script and returns you to the system mode prompt.

Related Commands CONTINUE DOFILE SET DOFILE ABORT

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CHANGE GATE TYPE CHAnge GAte Type -Type [-help] [-Golden | -Revised] (LEC Mode)

Changes the gate type of a selected object in the schematic viewer. Note: You cannot use this command on pins and nets. Note: If you invoke the Flatten Schematics window for a candidate gate (such as Corresponding Supports and Compared Points) from the Diagnosis Manager, you cannot change its gate type.

Parameters identifier

Specifies the gate ID or instance pathname. If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order.

-Type

Changes the specified gate type, where could be one of the following: ■

AND

■

NAND

■

OR

■

NOR

■

XOR

■

XNOR

■

BUF

■

INV

Note: Not all types are available for all objects

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-help

Returns a list of potential candidate gate types that can be applied.

-Golden

Specifies that the identifier is in the Golden design. This is the default.

-Revised

Specifies that the identifier is in the Revised design.

Related Commands REPORT GATE

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CHANGE NAME CHAnge NAme [-Summary |-Verbose] [-Golden |-Revised |-Both] (Setup Mode)

Converts netlist net names, port names, and cell names back to their original names. Thus, Conformal does key point mapping faster and more efficiently. The most common use of this command is to change the names in a post synthesis netlist back to their original, presynthesis forms. After Conformal reads in the file containing the original names and new names, it makes the conversion. Generally, the synthesis tool you have used generates the file describing the changes. Consult the specific vendor’s tool documentation for additional change name information. The format of the change name file is as follows: ■

The change name information is preceded by dashes. Note the dashes in the example below that separate column headers and the change name information. Conformal recognizes this file as a change name file format when it detects the dashes.

■

The “Design” column consists of module names. For example, see mod0_module in the sample Change Name file below.

■

The “Type” column consists of elements that belong to the specified design (that is, cell, port, and net).

■

The “Object” is the original name. Conformal will change the name back from the “New Name” to the original name.

■

The “New Name” is the name assigned by the synthesis tool

Sample Change Name File Design

Type

Object

New Name

---------------------------------------------------------mod0_module

port

port0_input1

port0_1

mod0_module

net

net0_output

net0_t

mod1_module

port

port1_input1a

port_1a

mod1_module

cell

net1_subinstantiation

net1_n

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Parameters filename

Specifies the file that contains name changes.

-Summary

Prints out the summary count of the number of name changes. This is the default.

-Verbose

Prints out a message for each name change.

-Golden

Changes names in the Golden design. This is the default.

-Revised

Changes names in the Revised design.

-Both

Changes names in both the Golden and Revised designs.

Related Commands ADD RENAMING RULE DELETE RENAMING RULE REPORT RENAMING RULE

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CHECK LOWPOWER CELLS CHEck LOwpower Cells (LEC Mode)

Note: This is a Conformal Low Power command. Performs low power checks for low power cell types that were specified with the SET LOWPOWER OPTION command. This check consists of the state retention technology mapping check, isolation and level-shifter cell check, and the power domain consistency check. These checks are described as follows: State Retention Cells For state retention cells, this command does the technology mapping check to ensure that the sequential elements (DFFs or DLATs) are technology mapped in accordance with the retention mapping rules during synthesis. These retention mapping rules include all the user rules added with the ADD RETENTION MAPPING command and the default rule added by the system. The following three default rules are added by the system: Note: For any sequential pairs, only one of the default rules take effect. ■

Default: Checks that the tag name used in the Golden design is mapped to a non-state retention cell in the Revised design. A non-state retention cell is a cell that does not have a power_gating_cell attribute. This rule is normally applied during RTL to gate-level checks.

■

Default1: Checks that the power_gating_cell attribute in the Golden design is exactly the same as the power_gating_cell in the Revised design. This check ensures that non-state retention cells (regular DFFs or DLATs) are mapped to non-state retention cells, or state retention cells are mapped to state retention cells. This rule is normally applied during gate-level to gate-level checks.

■

Default2: Checks that the tag name used in the Golden design is exactly the same as the tag name used in the Revised design. This rule is normally applied during RTL to RTL checks.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Isolation Cells and Level-Shifter Cells For isolation cells and level-shifter cells, this command does the technology mapping check and equivalence check. The technology mapping check ensures that for each low power cell (isolation cell or level-shifter cell) in the Golden design, there is a corresponding low power cell in the Revised design. To establish the correspondence, the Conformal software inserts key points (cut gates) at the output of low power cells and performs name-based mapping. If it does not find mapping for a low power cut gate, it sets the status of the corresponding low power cell to FAIL; otherwise, the status is set to PASS. The equivalence check (EC) ensures that for the mapped low power cell pair, the logic feeding them is equivalent in both the Golden and Revised designs. To perform EC, the Conformal software adds the low power cut gates as compare points and these are proven equivalent or non-equivalent during compare (when running the COMPARE command). Note: The CHECK LOWPOWER CELLS command performs only the technology mapping check for isolation cells and level-shifter cells. The EC checking results are received after running the COMPARE command. After performing the low power check, a status summary is printed for all low power cells. Power Domain Consistency Check Power domain consistency checking is available in the CPF flow. This checks whether the sequential mapped pair resides in the same power domain between the Golden and Revised designs. You can perform this check after reading in the CPF files for both the Golden and Revised designs. For RTL and synthesized gate netlists, the power domain of key-points can only be obtained from the CPF specification. For the physical netlist, the power domain can be obtained either from the CPF specification or by tracing the power and ground pins. The power domain consistency check sets the status of the mapped pair to FAIL if the power domains of the Golden and Revised sequential points in the mapped pair are different. In the case of merged sequential points, if the power domains of any of the merged elements are different, the power domain consistency check will set the status of the corresponding pair to FAIL. Note: The power domain consistency check is only enabled for sequential compare points. Note: Use the SET MAPPING METHOD -unreach command to allow mapping and checking the consistency of power domains for unreachable key-points.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference If the power domain cannot be obtained for sequential element in the mapped pair, the power domain consistency check sets the mapped pair status to NOT-CHECKED. The following are the scenarios where power domains cannot be obtained for a sequential element: ■

CPF is not read in.

■

CPF specification is incomplete. For example, no default power domain is specified or CPF does not have the definition of internal power and ground nets.

■

LEF file is not read in.

■

Power and Ground pins are floating in the physical netlist.

Related Commands ADD LOWPOWER CELLS ADD RETENTION MAPPING COMPARE REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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CHANGE NET TYPE CHAnge NEt Type |-Module ] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Modifies the database so that it appears that the changed net types were declared in the original Verilog netlist.

Parameters TRI

Specifies a tristate net type. This is the default.

TRI0

Specifies a net of type TRI0.

TRI1

Specifies a net of type TRI1.

TRIREG

Specifies a net of type TRIREG.

TRIAND

Specifies a net of type TRIAND.

TRIOR

Specifies a net of type TRIOR.

-Module Specifies the module name of the net to be changed. By default, this command changes the net in the root module.

Related Command ADD NET ATTRIBUTE

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CLOSE SCHEMATICS CLOse SChematics (Setup / LEC Mode)

Closes all schematic viewer windows. Note: You cannot use this command in non-GUI mode.

Related Command OPEN SCHEMATICS

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COMMIT CPF COMmit CPf [-INSERT] [-GOLden | -REVised | -BOTH] (Setup Mode)

Note: This is a Conformal Low Power command. Applies CPF low power cell information. When performing insertion, the cell types can be level shifter cells, isolation cells, and state retention cells. These low power cells can either be defined in .lib or defined in CPF files. You can only run this command after successfully reading in the CPF files.

Parameters -INSERT

Inserts low power cells, which include level shifter, isolation, and state retention cells, into the original design.

-GOLden

Inserts low power cells in the Golden design. This is the default.

-REVised

Inserts low power cells in the Revised design.

-BOTH

Inserts low power cells in both the Golden and Revised designs.

Examples The following commands show an example of the CPF equivalency checking flow, which performs low power cell insertion on the Golden side, and performs equivalency checks with physical implementation in two CPF files named rtl.cpf and my_library.cpf: read lef file my_library.lef read library -liberty my_library.lib -both read design rtl.v -verilog -golden read cpf rtl.cpf my_library.cpf commit cpf -insert read design physical.v -verilog -revised add compare point -all compare

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Related Command READ CPF REPORT CPF LOGIC

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COMPARE COMpare [-NONEQ_Stop ] [-ABORT_Stop ] [-NONEQ_Print] [-ABORT_Print] [-PARALLEL ] [-GATE_TO_GATE] [-SIngle] [-NOREPORT_BBOX_INPUT | -REPORT_BBOX_INPUT] [-NOREPORT_SINGLE_LINE_SUMMARY | -REPORT_SINGLE_LINE_SUMMARY] (LEC Mode)

Starts the equivalency checking comparison between the Golden and Revised designs on the added compared points. During the comparison, the following information is displayed: ■

Progress percentile number, which displays the completion rate

■

Running count, which displays the number of key points that have been compared along with the total number of non-equivalent key points

Each compared point results in a status drawn from the following five possibilities: ■

Equivalent

■

Inverted equivalent

■

Nonequivalent

■

Abort

■

Not compared

When Conformal completes the comparison, it displays a summary table of the number of equivalent and non-equivalent compared points. Note: If you must interrupt the comparison, the Control-C keys stop the process.

Parameters -NONEQ_Stop

Stops the comparison after finding the specified number of non-equivalent points.

-ABORT_Stop

Stops the comparison after finding the specified number of abort points.

-NONEQ_Print

Displays the non-equivalent points as they are found.

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-ABORT_Print

Displays the abort points as they are found.

-PARALLEL Note: This is a Conformal Ultra feature. Runs a comparison on multiple machines. Tip You can use the USAGE command to display the total CPU time used for all processes. For more information on creating a machine_file, see Parallel Processing in the Encounter Conformal Equivalence Checking User Guide. -GATE_TO_GATE

Enables an algorithm that might improve the run time of large gate-to-gate netlist comparisons.

-SIngle

Compares each key point as a single point. By default, the COMPARE command compares by key point groups.

-NOREPORT_BBOX_INPUT

Does not report the blackbox input pins in the compare report results. This is the default.

-REPORT_BBOX_INPUT

Reports the blackbox input pins in the compare report results (Equivalent, Non-equivalent, Abort, and Not-compared).

-NOREPORT_SINGLE_LINE_SUMMARY Does not print a single line summary of the compare results. This is the default. -REPORT_SINGLE_LINE_SUMMARY Prints a single line summary of the compare results.

Examples The following is a set of sample commands that shows this and related commands in context. The following set of commands assumes that you have read in your library, design, and have switched to the LEC mode.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 1. Use the ADD COMPARED POINTS command to add mapped points to the compare list. LEC> add compare point -all //2 compared points added to compare list

2. Use the COMPARE command to start the equivalency comparison between the Golden and Revised designs. LEC> compare ============================================================================ Compared points PO Total ---------------------------------------------------------------------------Equivalent 1 1 ---------------------------------------------------------------------------Non-equivalent 1 1 ============================================================================

3. Use the REPORT COMPARE DATA command to report the non-equivalent points. LEC> rep comp data -noneq Compared points are: Non-equivalent + 11 PO /x + 11

PO

/x

1 compared point(s) reported ============================================================================ Compared points PO Total ---------------------------------------------------------------------------Equivalent 1 1 ---------------------------------------------------------------------------Non-equivalent 1 1 ============================================================================

4. Use the ADD DYNAMIC CONSTRAINT command to add a dynamic constraint to the design. LEC> add dyn con 0 /c -gold LEC> add dyn con 0 /c -rev

5. Use the REPORT DYNAMIC CONSTRAINTS to report the dynamic constraints in the design. LEC> report dynamic constraints ============================================================================ Design ID Type Value Name ---------------------------------------------------------------------------Golden 3 PI 0 /c Revised 3 PI 0 /c ============================================================================

6. Use the PROVE command to show whether the specified gates are equivalent or not equivalent. LEC> prove /x /x //Compared points are: Non-equivalent //(G) + 11 PO /x //(R) + 11 PO /x

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 7. Use the DIAGNOSE command to diagnose the non-equivalent points. LEC> diag /x //Diagnosis for Non-equivalent key points: //(G) + 11 PO /x //(R) + 11 PO /x The diagnosis point can be corrected by changing the following gates: ============================================================================ Correction ID (R) Type Name ---------------------------------------------------------------------------DEL_INVERTER 24 INV /gextra

Related Commands ADD COMPARED POINTS DELETE COMPARED POINTS DIAGNOSE PROVE REPORT COMPARE DATA REPORT COMPARED POINTS RUN PARALLEL COMPARE SET COMPARE EFFORT USAGE

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CONTINUE CONTinue (Setup / LEC Mode)

Used in conjunction with the BREAK command in a dofile, when a dofile executes the BREAK command, Conformal issues a warning and prompts you to use the CONTINUE command. The CONTINUE command has no effect if you type it without being prompted by Conformal. The CONTINUE command supports mixed GUI and non-GUI mode. For example, you can run a dofile in non-GUI mode, encounter a break in the dofile, issue set gui on, and run continue from the GUI. The same applies when you break in the GUI mode: switch to command mode and enter continue. Conformal also supports nested breaks inside dofiles, working in a stack fashion. For example, when you type in continue from a lower-level dofile, Conformal proceeds until it encounters the next BREAK command.

Example //Warning: Break dofile ‘my_dofile’ at line 32. Use ‘continue’ command to continue. % continue

Related Commands BREAK DOFILE SET DOFILE ABORT

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COPY MODULE COPy MOdule <[-Golden | -Revised] source_module_name [-Revised | -Golden] target_module_name> [-LOGIC | -PINDIR] [-USE_RENAME_RULE | -NOUSE_RENAME_RULE] (Setup Mode)

Copies the logic or pin direction from a source module in one design to a target module in the other design. If you must copy both the logic and the pin direction, use two separate commands.

Parameters -Golden

Specifies that the source module is located in the Golden design. This is the default.

-Revised

Specifies that the source module is located in the Revised design.

source_module_name

Specifies the name of the source module to be copied.

-Revised

Specifies that the target module is located in the Revised design. This is the default.

-Golden

Specifies that the target module is located in the Golden design.

target_module_name

Specifies the name of the target module for the copy operation.

-LOGIC

Copies the logic from the source module into the target module. This is the default. If you must copy both logic and pin direction, use two separate COPY MODULE commands.

-PINDIR

Copies the pin direction from the source module into the target module. If you must copy both logic and pin direction, use two separate Copy Module commands.

-USE_RENAME_RULE

Uses renaming rules for matching pin and module names. This is the default.

-NOUSE_RENAME_RULE

Does not use renaming rules for matching pin and module names.

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Related Command ASSIGN PIN DIRECTION

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DELETE ALIAS DELete ALias (Setup / LEC Mode)

Deletes aliases created with the ADD ALIAS command. Use the REPORT ALIAS command to display a list of all aliases. Wildcard: The wildcard (*) represents any zero or more characters in alias names.

Parameters name*…

Deletes the specified aliases.

Related Commands ADD ALIAS REPORT ALIAS

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DELETE BLACK BOX DELete BLack Box [-Golden | -Revised | -Both] (Setup Mode)

Deletes specified blackboxes from the design. These blackboxes were either created with the ADD BLACK BOX command or were a part of the original design. Use the REPORT BLACK BOX command to display a list of all blackboxes. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters name*… -Module

Deletes blackboxes specified by this list. -module is the default.

name… -Instance

Specifies that the blackbox names are instance names.

-All

Deletes “all” defined blackboxes. -All applies within the given defaults.

-Golden

Deletes blackboxes from the Golden design. This is the default.

-Revised

Deletes blackboxes from the Revised design.

-Both

Deletes blackboxes from both the Golden and Revised designs.

Related Commands ADD BLACK BOX REPORT BLACK BOX

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DELETE CLOCK DELete CLock <-ALL_Pin | primary_pin…> [-Golden |-Revised] (Setup Mode)

Deletes clocks added with the ADD CLOCK command. Use the REPORT CLOCK command to display a list of all aliases.

Parameters -ALL_Pin

Deletes “all” the defined clocks. -All applies within the given defaults.

primary_pin…

Deletes the primary input pins that were defined as clocks and specified in this list.

-Golden

Deletes the clock(s) from the Golden design. This is the default.

-Revised

Deletes the clock(s) from the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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DELETE COMPARED POINTS DELete COmpared Points < -All |<… [-Golden |-Revised]> > (LEC Mode)

Deletes compared points originally added with the ADD COMPARED POINTS command. If the compared point is deleted from the Golden design, Conformal also deletes its mapped compared point from the Revised design. Alternately, if the compared point is deleted from the Revised design, Conformal also deletes its mapped compared point from the Golden design. Use the REPORT COMPARED POINTS command to display a list of all added compared points. Wildcard: The wildcard (*) represents any zero or more characters in instance and pin paths.

Parameters -All

Deletes “all” compare points. -All applies within the given defaults.

gate_id…

Deletes the specified gates as compare points. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname*… Deletes the specified instance paths as compare points. pin_pathname*…

Deletes the specified pin paths as compare points.

-Golden

Deletes the compare points from the Golden design. This is the default.

-Revised

Deletes the compare points from the Revised design.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT COMPARED POINTS

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DELETE CUT POINT DELete CUt Point <-All | pathname…> [-Net | -Pin] [-Golden | -Revised | -Both] (Setup Mode)

Deletes cut points originally added with the ADD CUT POINT command. Use the REPORT CUT POINT command to display a list of all added cut points.

Parameters -All

Deletes “all” cut points. -All applies within the given defaults.

pathname…

Deletes cut points from the specified paths.

-Net

Specifies that the named path is a net. This is the default.

-Pin

Specifies that the named path is a pin.

-Golden

Deletes the cut points from the Golden design. This is the default.

-Revised

Deletes the cut points from the Revised design.

-Both

Deletes the cut points from both the Golden and Revised designs.

Related Commands ADD CUT POINT REPORT CUT POINT REPORT PATH

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DELETE DYNAMIC CONSTRAINTS DELete DYnamic Constraints <-All | identifier…> [-INStance | -Pin | -Net | -ID] [-Golden | -Revised | -Both] (LEC Mode)

Deletes dynamic constraints originally added with the ADD DYNAMIC CONSTRAINTS command. Use the REPORT DYNAMIC CONSTRAINTS command to display a list of all added dynamic constraints.

Parameters -All

Deletes “all” dynamic constraints. -All applies within the given defaults.

identifier…

Deletes dynamic constraints from the specified identifier. If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. -INStance

Specifies the hierarchical instance path This is the default.

-Pin

Specifies the pin path, which is the module instance name concatenated with the pin name.

-Net

Specifies the net path, which is the instance name concatenated with the net name.

-ID

Specifies the identification number (ID) of a gate. The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

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-Golden

Deletes dynamic constraints from the Golden design. This is the default.

-Revised

Deletes dynamic constraints from the Revised design.

-Both

Deletes dynamic constraints from both the Golden and Revised designs.

Related Commands ADD DYNAMIC CONSTRAINTS PROVE REPORT DYNAMIC CONSTRAINTS

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DELETE ECO CELL DELete ECo Cell [-FReedcell ] [-SParecell ] [-ALL] (Setup Mode)

Deletes the spare cells or freed cells from the available cells for the MAP ECO PATCH command.

Parameters -FReedcell

Specifies the name(s) of the freed cell(s) to be deleted. This supports wildcards.

-SParecell

Specifies the name(s) of the spare cell(s) to be deleted. This supports wildcards.

-ALL

Deletes all the cells.

Related Commands ADD ECO CELL MAP ECO PATCH REPORT ECO CELL

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DELETE ECO PATCH DELete ECo PAtch [-ALL| [] ] (Setup Mode)

Deletes the ECO patch from the module list to be mapped by the MAP ECO PATCH command.

Parameters -ALL

Deletes all the added ECO patches.

Specifies the name of the module to delete Specifies the name of the patch module that contains the ECO changes.

Related Commands ADD ECO PATCH MAP ECO PATCH REPORT ECO PATCH

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DELETE ECO PIN DELete ECo PIn | ... [-Golden | -Revised] [-REPort ] (Setup Mode)

Deletes the pins from the module that were added with the ADD ECO PIN command.

Parameters

Specifies the name of the module.

Specifies the name of the pin(s).

Specifies the name of the bus(es). Note: You cannot delete only partial bits. For example, if there is a bus port OUT[1:0], the command should be: delete eco pin top OUT

not delete eco pin top OUT[1:0]

-Golden

Applies to the Golden design. This is the default.

-Revised


-REPort

Specifies the name of the report.

Related Commands ADD ECO PIN MAP ECO PATCH

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DELETE IGNORE RTLCHECK DELete IGnore Rtlcheck <-All | -Module > (Setup Mode)

Re-enables RTL (HDL) rule checking for all or specified modules. By default, rule checking is enabled. Thus, you will only use the DELETE IGNORE RTLCHECK command to reverse the effects of the ADD IGNORE RTLCHECK command. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about specific rules. Note: If you enter multiple IGNORE RTLCHECK commands, later commands replace previous commands. In the following example, Conformal enables RTL rule checking for all modules, including module abc. add ignore rtlcheck -module abc delete ignore rtlcheck -all

Parameters -All

Enables RTL rule checking for all modules.

-Module* name…

Enables RTL rule checking for the specified modules.

Related Commands ADD IGNORE RTLCHECK REPORT RULE CHECK

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DELETE IGNORED INPUTS DELete IGnored Inputs <-ALL_Pin | primary_pin*…> [-ROot |-Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes input pins originally added as ignored inputs in the Golden or Revised design with the ADD IGNORED INPUTS command. Use the REPORT IGNORED INPUTS command to display a list of all added ignored input pins. Wildcard: The wildcard (*) represents any zero or more characters in ignored input names.

Parameters -ALL_Pin

Deletes “all” previously added ignored inputs within the given defaults.

primary_pin*…

Deletes the specified pins as ignored inputs. The wildcard (*) is accepted.

-ROot

Deletes the ignored inputs in the root module. This is the default.

-Module name

Deletes the ignored inputs from the specified module.

-ALL_Module

Deletes the ignored inputs from all of the modules, including the root module.

-Golden

Deletes the specified ignored inputs from the Golden design. This is the default.

-REvised

Deletes the specified ignored inputs from the Revised design.

-Both

Deletes the specified ignored inputs from both the Golden and Revised designs.

Related Commands ADD IGNORED INPUTS REPORT IGNORED INPUTS

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DELETE IGNORED OUTPUTS DELete IGnored Outputs <-ALL_Pin | primary_pin*…> [-ROot | -Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes output or I/O pins originally added as ignored outputs with the ADD IGNORED OUTPUTS command. Use the REPORT IGNORED OUTPUTS command to display a list of all added ignored output or I/O pins. Wildcard: The wildcard (*) represents any zero or more characters in ignored output names.

Parameters -ALL_Pin

Deletes “all” added ignored outputs. “All” applies within the given defaults.

primary_pin*…

Deletes the specified pins as ignored outputs. The wildcard (*) is supported.

-ROot

Deletes the ignored outputs in the root module. This is the default.

-Module name

Deletes the ignored outputs from the specified module.

-ALL_Module

Deletes the ignored outputs from all modules, including the root module.

-Golden

Deletes the specified ignored outputs from the Golden design. This is the default.

-REvised

Deletes the specified ignored outputs from the Revised design.

-Both

Deletes the specified ignored outputs from both the Golden and Revised designs.

Related Commands ADD IGNORED OUTPUTS REPORT IGNORED OUTPUTS May 2008

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DELETE INSTANCE ATTRIBUTE DELete INstance Attribute [-Golden | -Revised] (Setup Mode)

Deletes instance attributes originally added with the ADD INSTANCE ATTRIBUTE command. Use the REPORT INSTANCE ATTRIBUTE command to display a list of all added instance attributes.


Deletes the instance attribute from the specified module.

instance_name

Deletes the instance attribute from the specified instance.

WEAK

Specifies drive strength. Note: This option applies to Conformal Custom.

-Golden

Deletes the instance attribute from the Golden design. This is the default.

-Revised

Deletes the instance attribute from the Revised design.

Related Commands ADD INSTANCE ATTRIBUTE REPORT INSTANCE ATTRIBUTE

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DELETE INSTANCE CONSTRAINTS DELete INstance Constraints < [-Module name*] | -All> [-Golden | -Revised | -BOTH] (Setup Mode)

Deletes instance constraints originally added with the ADD INSTANCE CONSTRAINTS command. Use the REPORT INSTANCE CONSTRAINTS command to display a list of all added instance constraints.

Parameters name…

Deletes constraints on the specified instance paths. Note: The names are either DFFs or D-latches.

-Module name*

Deletes the constraints from the specified module(s). The wildcard (*) is supported.

-All

Deletes “all” instance constraints. -All applies within the given defaults.

-Golden

Deletes instance constraints in the Golden design. This is the default.

-Revised

Deletes instance constraints in the Revised design.

-BOTH

Deletes instance constraints in both the Golden and Revised designs.

Related Commands ADD INSTANCE CONSTRAINTS REPORT INSTANCE CONSTRAINTS

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DELETE INSTANCE EQUIVALENCES DELete INstance Equivalences [-Golden | -Revised] (Setup Mode)

Deletes instance equivalences originally added with the ADD INSTANCE EQUIVALENCES command. Use the REPORT INSTANCE EQUIVALENCES command to display a list of all added instance equivalences.

Parameters instance_pathname…

Deletes equivalences on the specified instance paths.

-All

Deletes “all” instance equivalences. -All applies within the given defaults.

-Golden

Deletes instance equivalences in the Golden design. This is the default.

-Revised

Deletes instance equivalences in the Revised design.

Related Commands ADD INSTANCE EQUIVALENCES REPORT INSTANCE EQUIVALENCES

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DELETE LOWPOWER CELLS DELete LOwpower Cells [-Both | -Golden | -Revised] (Setup Mode)

Deletes low power cells that were originally defined for modules with the ADD LOWPOWER CELLS command. Use the REPORT LOWPOWER CELLS command to display a list of the low power cells used in the design.


Deletes previously added low power cells from the specified modules. This supports wildcards.

-ALL

Deletes previously added low power cells from “all” modules. “All” applies within the given defaults.

-Both

Deletes the low power cells in the Golden and Revised designs. This is the default.

-Golden

Deletes the low power cells in the Golden design.

-Revised

Deletes the low power cells in the Revised design.

Related Commands ADD LOWPOWER CELLS CHECK LOWPOWER CELLS REPORT LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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DELETE MAPPED POINTS DELete MApped Points <-All [-Class ] |<… [-Golden | -Revised]> |[-NONEQ] |[-UNREACH] > (LEC Mode)

Deletes mapped points that were one of the following: ■

Automatically identified

■

Added with the ADD MAPPED POINTS command.

Additionally, Conformal deletes all compared points associated with the added mapped points. Use the REPORT MAPPED POINTS command to display a list of all mapped points in the User and System classes of the Golden and Revised designs. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths of mapped points.

Parameters -All

Deletes “all” mapped points. -All applies within the given defaults.

-Class

Deletes the specified class of mapped points.

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The Full class includes mapped points from both the User and System classes. This is the default.

User

The User class includes mapped points that were previously added with the ADD MAPPED POINTS command.

System

The System class includes mapped points that were automatically identified when Conformal exited the Setup system mode or were mapped with the MAP KEY POINTS command.

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gate_id…

Deletes mapped points with these gate ID numbers. ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. The wildcard (*) is supported.

instance_pathname*… Deletes mapped points from the specified instance paths. pin_pathname*…

Deletes mapped points from the specified pin paths.

-Golden

Delete the mapped points from the Golden design. This is the default.

-Revised

Deletes the mapped points from the Revised design.

-NONEQ

Deletes all non-equivalent mapped points.

-UNREACH

Deletes all unreachable mapped points. An unreachable mapped point is one where both the Golden and Revised key points are unreachable. If the key point is the representative of the equivalence group or sequential merge group, it is considered unreachable only if all the member key points in the group are unreachable.

Related Commands ADD MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE

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DELETE MODULE ATTRIBUTE DELete MOdule Attribute <-PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit > [-Golden | -Revised] (Setup Mode)

Deletes attributes originally assigned to modules with the ADD MODULE ATTRIBUTE command. Use the REPORT MODULE ATTRIBUTE command to display a list of all added module attributes.

Parameters module_name…

Deletes previously added attributes from the specified modules.

-ALL

Deletes previously added attributes from “all” modules within the given defaults.

-PIPELINE_Retime

Deletes attributes previously added for pipeline-retiming.

-COMPARE_Effort

Deletes compare effort levels previously added to modules.

-CPU_Limit

Deletes the CPU time limit imposed with the ADD MODULE ATTRIBUTE command.

-Golden

Deletes the specified module attributes in the Golden design. This is the default.

-Revised

Deletes the specified module attributes in the Revised design.

Related Commands ADD MODULE ATTRIBUTE REPORT MODULE ATTRIBUTE WRITE HIER_COMPARE DOFILE

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DELETE MOS DIRECTION DELete MOs Direction [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Deletes the unidirection that was placed on transistor-MOS instances with the ADD MOS DIRECTION command. Use the REPORT MOS DIRECTION command to display a list of all transistor-MOS direction instances.


Deletes MOS direction for the specified module.

instance_name

Deletes MOS direction for the specified instance.

-Golden

Deletes MOS direction from the Golden design. This is the default.

-Revised

Deletes MOS direction from the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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DELETE NET ATTRIBUTE DELete NEt Attribute <-ALL_Net | net_name> [-ROot | -Module | -ALL_Module] [-Golden | -Revised | -Both] (Setup Mode)

Note: This is a Conformal Custom command. Deletes attributes that were placed on transistor-MOS nets with the ADD NET ATTRIBUTE command. Use the REPORT NET ATTRIBUTE command to display a list of all attributes placed on transistor-MOS nets.

Parameters -ALL_Net

Deletes “all” net attributes within the given defaults.

net_name

Deletes the specified transistor-MOS net attributes.

-ROot

Deletes net attributes associated with the root module, which contains the transistor-MOS. This is the default.

-Module name

Deletes net attributes associated with the specified module, which contains the transistor-MOS.

-ALL_Module

Deletes a specified net attribute for all modules, or delete all net attributes for all modules. (Refer to -all_net and -net_name to understand the two choices.)

-Golden

Deletes net attributes from the Golden design. This is the default.

-Revised

Deletes net attributes from the Revised design.

-Both

Deletes net attributes from both the Golden and Revised designs.

Related Commands ABSTRACT LOGIC ADD CLOCK

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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DELETE NET CONSTRAINTS DELete NEt Constraints [-Golden | -Revised | -Both] (Setup Mode)

Deletes either the Golden or Revised design net constraints originally added with the ADD NET CONSTRAINTS command. Use the REPORT NET CONSTRAINTS command to display a list of all added net constraints.

Parameters -Golden

Deletes net constraints from the Golden design. This is the default.

-Revised

Deletes net constraints from the Revised design.

-Both

Deletes net constraints from both the Golden and Revised designs.

Related Commands ADD NET CONSTRAINTS REPORT NET CONSTRAINTS

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DELETE NOBLACK BOX DELete NOblack Box [-Golden | -Revised | -Both] (Setup Mode)

Deletes the specified module names originally added with the ADD NOBLACK BOX command. Use the REPORT NOBLACK BOX command to display a list of all of the modules that will be resolved (flattened) to their parents’ modules during hierarchical dofile script generation. Wildcard: The wildcard (*) represents any zero or more characters in module names.


Deletes the previously added noblackbox modules.

-All

Deletes “all” previously added noblackboxes. -All applies within the given defaults.

-Golden

Deletes the specified Golden module names. This is the default.

-Revised

Deletes the specified Revised module names.

-Both

Deletes all of the specified modules from both the Golden and Revised designs.

Related Commands ADD NOBLACK BOX REPORT NOBLACK BOX WRITE HIER_COMPARE DOFILE

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DELETE NOTRANSLATE FILEPATHNAMES ADD NOtranslate Filepathnames [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Deletes the specified file pathnames originally added with the ADD NOTRANSLATE FILEPATHNAMES command. Use the REPORT NOTRANSLATE FILEPATHNAMES command to display a list of all of the library and design file pathnames. Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters filepath_name*…

Deletes the listed notranslate file pathnames.

-All

Deletes “all” previously added notranslate file pathnames. -All applies within the given defaults.

-Library

Deletes the specified library file pathnames. This is the default.

-Design

Deletes the specified design file pathnames.

-Both

Deletes the specified file pathnames from both the Golden and Revised designs. This is the default.

-Golden

Deletes the specified Golden file pathnames.

-Revised

Deletes the specified Revised file pathnames.

Related Commands ADD NOTRANSLATE FILEPATHNAMES DELETE NOTRANSLATE MODULES REPORT NOTRANSLATE FILEPATHNAMES REPORT NOTRANSLATE MODULES

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DELETE NOTRANSLATE MODULES DELete NOtranslate Modules [-Library | -Design] [-Both | -Golden | -Revised] (Setup Mode)

Deletes the specified module names originally added with the ADD NOTRANSLATE MODULES command. Use the REPORT NOTRANSLATE MODULES command to display a list of all of the library and design module names that will not be compiled. Wildcard: The wildcard (*) represents any zero or more characters in module names.


Deletes the listed modules.

-All

Deletes “all” previously added notranslate module names. -All applies within the given defaults.

-Library

Deletes the specified library module names. This is the default.

-Design

Deletes the specified design module names.

-Both

Deletes the specified modules from both the Golden and Revised designs. This is the default.

-Golden

Deletes the specified Golden module names.

-Revised

Deletes the specified Revised module names.

Related Commands ADD NOTRANSLATE MODULES READ DESIGN READ LIBRARY REPORT NOTRANSLATE MODULES

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DELETE OUTPUT EQUIVALENCES DELete OUtput Equivalences <-ALL_Pin | primary_pin*…> [-ROot | -Module | -ALL_Module] [-Golden | -Revised | -Both] (Setup Mode)

Deletes the output pin equivalences placed on output boundary module pins with the ADD OUTPUT EQUIVALENCES command. Use the REPORT OUTPUT EQUIVALENCES command to display a list of all added output pin equivalences. Wildcard: The wildcard (*) represents any zero or more characters in output boundary module pin names.

Parameters -ALL_Pin

Deletes “all” output pin equivalences within the given defaults.

primary_pin*…

Deletes output pin equivalences from the listed output boundary module pins.

-ROot

Deletes the output pin equivalences from the root module.

-Module name

Deletes the output pin equivalences from the specified module.

-ALL_Module

Deletes the output pin equivalences from all modules.

-Golden

Deletes the specified output pin equivalences in the Golden design. This is the default.

-Revised

Deletes the specified output pin equivalences in the Revised design.

-Both

Deletes the specified output pin equivalences in both the Golden and Revised designs.

Related Commands ADD OUTPUT EQUIVALENCES REPORT OUTPUT EQUIVALENCES

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DELETE OUTPUT STUCK_AT DELete OUtput Stuck_at <-ALL_Pin | primary_pin…> [-Module ] [-Golden |-Revised]

Deletes the output stuck_at values placed on output boundary module pins with the ADD OUTPUT STUCK_AT command. Use the REPORT OUTPUT STUCK_AT command to display a list of all added output stuck_at values and their pin names.

Parameters -ALL_Pin

Deletes “all” output stuck_at values within the given defaults.

primary_pin…

Deletes the output stuck_at values associated with the listed output boundary module pins.

-Module name

Deletes the output stuck_at values in the specified module.

-Golden

Deletes the output stuck_at values in the Golden design. This is the default.

-Revised

Deletes the output stuck_at values in the Revised design.

Related Commands ADD OUTPUT STUCK_AT REPORT OUTPUT STUCK_AT

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DELETE PARTITION KEY_POINT DELete PArtition Key_point (Setup Mode)

Deletes all of the specified partition key points originally added with the ADD PARTITION KEY_POINT command. Use the REPORT PARTITION KEY_POINT command to display a list of all added partition key points.

Related Commands ADD PARTITION KEY_POINT REPORT PARTITION KEY_POINT WRITE PARTITION DOFILE

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DELETE PARTITION POINTS DELete PARtition Points [-NONequivalent] [-Golden | -Revised] [-NOVerbose | -Verbose] (LEC Mode)

Note: This is a Conformal Ultra command. Deletes the partition points that were created with the ADD PARTITION POINTS command. Note: Partition points are always deleted in pairs. Tip You can get the pathname of the partition point with the REPORT PARTITION POINT command. Caution Deleting partition (CUT) points in LEC mode causes flattened netlists to change. As a result, all the gate-ids are subjected to change. Deleting cut points does not affect the existing compare points list; however, all the compare data is invalidated after deleting cut points.

Parameters pathname

Specifies the name of the path for the partition points to be deleted.

-All

Specifies that all the existing partition points will be deleted.

-BAD_cuts

Automatically deletes the bad set of partition points causing false non-equivalence.

-EFFORT

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Specifies the effort level for deleting the bad set of partition points. Increasing the effort level from Low to High will intelligently delete more partition points decreasing the probability of false non-equivalence. However, increasing the effort will result in increased time as well. The default effort level is Low. -NONequivalent

Deletes partition cut points that caused false non-equivalent points.

-Golden

Specifies that the partition point is in the Golden design. This is the default.

-Revised

Specifies that the partition point is in the revised design.

-NOVerbose

Does not provide additional information. This is the default.

-Verbose


Related Commands ADD PARTITION POINTS REPORT PARTITION POINTS

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DELETE PIN CONSTRAINTS DELete PIn Constraints <-ALL_Pin | primary_pin*…> [-Module ] [-Golden | -Revised | -Both] (Setup Mode)

Deletes constraints originally placed on named primary input pins with the ADD PIN CONSTRAINTS command. Use the REPORT PIN CONSTRAINTS command to display a list of all added pin constraints. Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters -ALL_Pin

Deletes “all” constraints placed on primary input pins within the given defaults.

primary_pin*…

Deletes constraints from the listed primary inputs.

-Module name

Deletes pin constraints from the specified module.

-Golden

Deletes the specified pin constraints from the Golden design. This is the default.

-Revised

Deletes the specified pin constraints from the Revised design.

-Both

Deletes the specified pin constraints from both the Golden and Revised designs.

Related Commands ADD PIN CONSTRAINTS REPORT PIN CONSTRAINTS

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DELETE PIN EQUIVALENCES DELete PIn Equivalences <-ALL_Pin | primary_pin*…> [-ROot | -Module | -ALL_Module] [-Golden | -REvised | -Both] (Setup Mode)

Deletes the added pin equivalences from the specified primary input pins. These equivalences were placed on primary input pins with the ADD PIN EQUIVALENCE command. Use the REPORT PIN EQUIVALENCES command to display a list of all of the added pin equivalences. Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters -ALL_Pin

Deletes “all” added pin equivalences within the given defaults.

primary_pin*…

Deletes pin equivalences from the listed primary input pins. (Pin equivalence was originally added with the ADD PIN EQUIVALENCE command.)

-ROot

Deletes pin equivalences from the root module.

-Module name

Deletes pin equivalences from the specified module.

-ALL_Module

Deletes pin equivalences from all modules.

-Golden

Deletes the specified pin equivalences from the Golden design. This is the default.

-REvised

Deletes the specified pin equivalences from the Revised design.

-Both

Deletes the specified pin equivalences from both the Golden and Revised designs.

Related Commands ADD PIN EQUIVALENCES REPORT PIN EQUIVALENCES

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DELETE PRIMARY INPUTS DELete PRimary Inputs <-All | pathname*…> [-Golden | -Revised | -Both] (Setup Mode)

Deletes specified primary inputs that were originally added with the ADD PRIMARY INPUT command. After you delete the primary input pins from either the Golden or Revised design, the associated nets become floating nets, unless there are other net drivers. Use the REPORT PRIMARY INPUTS command to display a list of all primary inputs. Wildcard: The wildcard (*) represents any zero or more characters in paths of primary inputs.

Parameters -All

Deletes “all” primary inputs within the given defaults.

pathname*…

Deletes the specified primary inputs.

-Golden

Deletes the specified primary inputs from the Golden design. This is the default.

-Revised

Deletes the specified primary inputs from the Revised design.

-Both

Deletes the specified primary inputs from both the Golden and Revised designs.

Related Commands ADD PRIMARY INPUT REPORT PRIMARY INPUTS

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DELETE PRIMARY OUTPUTS DELete PRimary Outputs <-All | pathname*…> [-Golden | -Revised | -Both] (Setup Mode)

Deletes primary outputs that were originally added with the ADD PRIMARY OUTPUT command. When you delete the primary output pins from the Golden or Revised design, the nets become floating nets, unless there are other net drivers. Use the REPORT PRIMARY OUTPUTS command to display a list of all primary outputs. Wildcard: The wildcard (*) represents any zero or more characters in paths of primary outputs.

Parameters -All

Deletes “all” primary outputs within the given defaults.

pathname*…

Deletes the specified primary outputs.

-Golden

Deletes primary outputs from the Golden design. This is the default.

-Revised

Deletes primary outputs from the Revised design.

-Both

Deletes primary outputs from both the Golden and Revised designs.

Related Commands ADD PRIMARY OUTPUT REPORT PRIMARY OUTPUTS

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DELETE RENAMING RULE DELete REnaming Rule <-All | > [-MAp | -MOdule | -PIn] (Setup / LEC Mode)

Deletes renaming rules originally added with the ADD RENAMING RULE command. Use the REPORT RENAMING RULE command to display a list of all of the renaming rules and their rule numbers.

Parameters -All

Deletes all previously added renaming rules in one of the following three categories: ■

Map

■

Module

■

Pin

If you do not specify a category, Conformal deletes all previously added renaming rules from the Map category. rule_name

Deletes the specified renaming rule.

-MAp

Deletes map renaming rules. This is the default.

-MOdule

Deletes module renaming rules.

-PIn

Deletes pin renaming rules.

Related Commands ADD RENAMING RULE CHANGE NAME MAP KEY POINTS READ DESIGN READ LIBRARY

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT RENAMING RULE SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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DELETE RETENTION MAPPING DELete REtention Mapping <-All | > (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Deletes the state retention mapping rules added using the ADD REtention_register Mapping command. Note: Use the REPORT RETENTION MAPPING command to display a list of all the state retention mapping rules. Note that the default rule added by the system can never be deleted. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 143.

Parameters -All

Deletes all the state retention register mapping rules added using the ADD RETENTION MAPPING Mapping command. This option does not delete the default rule added by the system.

rule_name

Deletes the specified state retention mapping rule. Note: The default rule added by the system cannot be deleted.

Related Commands ADD RETENTION MAPPING REPORT RETENTION MAPPING

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DELETE SEARCH PATH DELete SEarch Path <-All | pathname…> [-Design | -Library] [-Golden | -Revised] (Setup Mode)

Deletes search paths Conformal uses for the READ DESIGN and READ LIBRARY commands. Use the REPORT SEARCH PATH command to display a list of all search paths.

Parameters -All

Deletes “all” previously added search paths within the given defaults.

pathname…

Deletes the specified search paths.

-Design

Deletes search paths used by the READ DESIGN command. This is the default.

-Library

Deletes search paths used by the READ LIBRARY command.

-Golden

Deletes search paths used by the Golden design or library. This is the default.

-Revised

Deletes search paths used by the Revised design or library.

Related Commands ADD SEARCH PATH READ DESIGN READ LIBRARY REPORT SEARCH PATH

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DELETE TIED SIGNALS DELete TIed Signals <-All | name…> [-Net |-Pin] [-Module ] [-Class ] [-Golden |-Revised] (Setup Mode)

Deletes specified tied signals from the Golden or Revised design. Use the REPORT TIED SIGNALS command to display a list of all of the tied signals.

Parameters -All

Deletes “all” tied signals within the given defaults.

name…

Deletes the specified tied signals.

-Net

Specifies that the deleted tied signal is a net. This is the default.

-Pin

Specifies that the deleted tied signal is a pin.

-Module name

Specifies the name of the module where the floating net or pin resides.

-Class

Deletes tied signals of this class. Full

Tied signals from both the User and System classes. This is the default.

User

Tied signals the user previously added with the ADD TIED SIGNALS command.

System

Tied signals from the original design.

-Golden

Deletes tied signals from the Golden design. This is the default.

-Revised

Deletes tied signals from the Revised design.

Related Commands ADD TIED SIGNALS

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT TIED SIGNALS

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DIAGNOSE DIAgnose < < gate_id | instance_pathname | pin_pathname> [-Golden |-Revised][-SUPport] [-NUm ] | -SUMmary [integer][-SOrt ] |[-NOneq]> (LEC Mode)

Performs diagnosis on a specified compared point. Specify the compared point by its gate identification number, instance path, or a pin path. Use this command to determine why the software identified non-equivalence between compared points. The diagnosis displays all of the non-corresponding support key points with a list of all likely error candidates from the Revised design. The list organizes likelihood in descending order with 1.00 being the greatest possible error candidate. Use the REPORT ENVIRONMENT command to display the maximum diagnosis candidates setting.

Parameters gate_id

Diagnoses the specified gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname

Diagnoses the specified instance path.

pin_pathname

Diagnoses the specified pin path.

-Golden

Diagnoses the Golden design. This is the default.

-Revised

Diagnoses the Revised design.

-SUPport

Displays the list of corresponding and non-corresponding support points.

-NUm integer

Lists the specified number of error candidates. By default, Conformal lists all error candidates.

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-SUMmary integer

Displays a table of the non-equivalent points with their corresponding support size, non-corresponding support size, and cone size. The integer represents the number of nonequivalent points you wish to display in the table. By default, Conformal displays all nonequivalent points.

-SOrt

Sorts the summary table results by one of the following. SUpport

Sorts by corresponding support size This is the default.

SIze -NOneq

Sorts by cone size

Diagnoses every nonequivalent point.


Related Commands PROVE REPORT COMPARE DATA REPORT ENVIRONMENT REPORT TEST VECTOR

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DOFILE DOFile < [-FORCE] | -SHOW_STACK> (Setup / LEC Mode)

Executes a set of commands contained in a specified file. If there is an error while the Conformal software is executing the dofile script, it terminates the dofile execution and returns to the system mode prompt. Use the SET DOFILE ABORT command to specify how you want the Conformal software to respond when an error message occurs. You can choose to terminate, continue, or exit the session. Use the BREAK command in a dofile script to terminate the dofile script and return to the system mode prompt.

Parameters filename

Specifies a file containing a set of commands the Conformal software executes one at a time.

-FORCE

Allows a dofile to be executed multiple times, up to a limit of 16. Without this option, you will get an error if you attempt to run a dofile multiple times.

-SHOW_STACK

Specifies that if the current execution is stopped because of a break in one or more dofiles, it will display the current dofile execution stack. For example: 1:

dofile_2 break (line:2) 2: dofile_1 dofile dofile_2 (line:5)

Related Commands BREAK CONTINUE SET DOFILE ABORT

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ELABORATE DESIGN ELAborate DEsign [-ROot ] [-ROOTConfig ] [-PARAmeter [-INT | -STR | -ENUM] ] [-RAngeconstraint] [-GOlden | -REvised] (Setup Mode)

Completes the READ DESIGN command specified with the -noelaborate option. During this step, modules are synthesized and the complete design hierarchy is created. This command is typically used for mixed design flows where the Verilog modules and VHDL entity or architectures are read in separately. Then they can be elaborated using this command.

Parameters -ROot Specifies the root module to be elaborated. If this option is not specified, the Conformal software automatically select a root module. -ROOTConfig Specifies that the design includes the specified configuration for the top-level module. Note: This option applies to only VHDL designs. Use this option when the design includes multiple configurations for the top-level module. When you use the -rootconfig option, you must also use the -root module_name option (above).

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-PARAmeter [-INT | -STR | -ENUM] Assigns design parameters or replace existing design parameters. To specify multiple parameters, use the -parameter option for each parameter you want to set. For example: read design filename -parameter parm1 value1 \ -parameter -int parm2 value2

This option applies to both Verilog and VHDL files. (Combine with -root.) When using the -parameter -int command, the will be converted to integer value, which can be a positive integer (1), negative integer (-1), an integer value recognized as a string ("1"/"-1"), or a Verilog style integer ("16’h0001"). When using a Verilog style integer, the value must be specified between double-quotes (" "). When using the -parameter -str command, the will be saved as a string. When using the -parameter -enum command, the will be converted to a VHDL enumeration literal. For example, the following command sets the parameter P4 to VHDL enumeration literal GREEN: read design -root mod1 filename \ -parameter -enum P4 GREEN

Note: Any value that is not recognized as an unsigned decimal integer value is interpreted as string value. Note: If -int or -str is not specified, then the parameter value will be interpreted as an integer if it is not between double-quotes (" "), and as a string if it is between double-quotes. Therefore, if you want to specify a Verilog format value, it must be between double-quotes and used with the -int option. -RAngeconstraint

Applies range constraints during verification. If this option is not specified, all range constraints are ignored.

-Golden

Specifies to elaborate the Golden design. This is the default.

-Revised

Specifies to elaborate the Revised design.

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EXIT EXIt [-Force] (Setup / LEC Mode)

Ends the existing Conformal session and returns you to the operating system. Exit Status Codes On exiting, Conformal returns a status code. A nonzero status code means there is a potential error; that is, either no comparison was done or unmapped, abort, or nonequivalent points exist. The exit status code consists of flags that represent different conditions. Saving GUI Settings By default, Conformal does not automatically save GUI settings for future sessions. To save your preferred settings, use the GUI exit window and click the Save GUI settings check box. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about exit status codes and the procedure to save GUI settings.

Parameters -Force

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FLATTEN FLAtten <-MODule | -ALL> [-Force | -NOForce] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Removes all hierarchy on a specified module or for all modules in the database. If you do not specify one or all modules, Conformal flattens the root module by default. Thus, this command expands all of the gate primitive or transistor primitive devices into the cell that is being flattened. The following example illustrates the effects of this command: A cell that is to be flattened contains three cells. One cell has 25 gates and the other two are the same, each with 33 gates. After flattening, the cell now contains 0 cells and 91 gates (1 * 25 + 2 * 33 = 91).

Parameters -MODule name

Flattens the specified module. The default is to flatten the root module.

-ALL

Flattens “all” modules within the given defaults.

-Force

Forces flattening of specified modules in the Golden or Revised design even if those modules have not been flattened in the complementing design. (For example, force flattening for Golden modules when the Revised have not been flattened.) This is the default.

-NOForce

Does not force flattening when those modules have not been flattened in the complementing design.

-Golden

Flattens the specified module(s) from the Golden design. This is the default.

-Revised

Flattens the specified module(s) from the Revised design.

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FORWARD FORward [integer] (LEC Mode)

Reports fan-out gate information from the currently displayed flatten gate information. The fan-out gate you choose with this command becomes the current flattened gate. Use this command to trace gates in place of repeatedly using the REPORT GATE command. Note: This command does not report gates at the design level.

Parameters integer

Reports the specified fan-out gate. The value 1 denotes the first fan-out. The default is 1.

Related Commands BACKWARD REPORT GATE

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GENERATE ROM PRIMITIVE GENerate ROm Primitive <-SIM > <-CODE_FILE > [-MOD ] [-CODE_FILE_FORMAT [BIN | HEX]] [-NO_ACCESS_OUT_LOW | -NO_ACCESS_OUT_HIGH] (Setup Mode)

Note: This is a Conformal Custom command. Generates a ROM primitive model that you can use to verify against a valid ROM circuit. Conformal generates a ROM primitive that has the following interface: ■

Addr—Address bus for accessing ROM data.

■

Dout—Output data from ROM.

■

RE—Control clock for the output latch or flip-flop, when you set the -outstate option to dlat or dff. When RE is high, ROM data is sampled.

■

CK—Address decode clock for ROM read operations. ROM is read when the clock is high.

This command reads in a code file that initializes the ROM. This code file should contain one number per line, in binary format. The number of entries in the code file should match the number of words in the memory. As Conformal reads the code file, it assigns each entry to a successive word element in the memory. The following illustrates sample contents for a code file called rom.code, which initializes a 4 X 4 ROM: 0000 1111 1010 0111 Note: To perform simulation, you must define the macro SIM.

Parameters -SIM

Specifies the output file for the ROM primitive.

-CODE_FILE

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Specifies the code file that will initialize the ROM. This code file should contain initialization data in binary format. -MOD

Specifies the module name of the ROM primitive that is created.

-CODE_FILE_FORMAT [BIN | HEX] Specifies the output file format for the ROM primitive. -NO_ACCESS_OUT_LOW

Fills the memory address with ’0’ when it is not initialized. This is the default.

-NO_ACCESS_OUT_HIGH

Fills the memory address with ’1’ when it is not initialized.

Related Command READ ROM PRIMITIVE

Examples The following command generates a ROM model with a code file called rom.code. generate rom primitive -sim VROM.v -code_file rom.code -mod VROM / -code_file_format bin -no_access_out_low

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GROUP GROUP <-Module > <-Instance > <-NEWModule > <-NEWInstance > [-net_to_pin_name] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Groups defined instances together so that they become a new submodule. This command is the opposite of the RESOLVE command; it applies to submodules, latches, registers, gates, and transistors. By default, this command assigns unique and arbitrary submodule pin names. Wildcard: The wildcard (*) represents any zero or more characters in existing instance names.

Parameters -Module name

Specifies a module for which to apply the grouping.

-Instance instance_name*… Specifies the instances to group. This accepts wildcards. -NEWModule name

Specifies the name of the new module.

-NEWInstance name

Specifies the instance name for the new module.

-net_to_pin_name

Specifies that the pin names of the new modules will be the same as the nets connected to them, and not unique and arbitrary.

-Golden

Applies this command to modules and instances in the Golden design. This is the default.

-Revised

Applies this command to modules and instances in the Revised design.

Related Command RESOLVE May 2008

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HELP HELp [ | | -message] [-Verbose] [-NOSHOW_ERROR_ID | -SHOW_ERROR_ID] [-NOSHOW_EXTENDED_HELP | -SHOW_EXTENDED_HELP] [-COLOR | -NOCOLOR] [-PAGE | -NOPAGE] [] (Setup / LEC Mode)

Displays the Conformal commands and their command syntax. To display a group or set of commands, use a keyword such as ADD, DELETE, REPORT, or SET. While in the Tcl mode, the HELP command displays a list of all available Conformal Tcl mode commands.

Parameters

Displays the command syntax for a given command name. If you do not specify a command name, the Conformal Equivalence Checker displays all of the commands.

Displays help for the corresponding rule check message.

-message

Displays all rule check messages.

-Verbose

Expands information about the command, including descriptions of the parameters and related commands.

-NOSHOW_ERROR_ID

Does not display the error ID. This is the default.

-SHOW_ERROR_ID

Displays the error ID.

-NOSHOW_EXTENDED_HELP Does not display the extended help. This is the default. -SHOW_EXTENDED_HELP Displays the extended help only. This does not include error IDs. -COLOR

Displays the help text with color highlights. This is the default. Note: This option has no effect if the terminal is not an ’xterm’, as determined by the environmental variable TERM, or when running HELP in the GUI window.

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-NOCOLOR

Disables the help text with color highlight display. Use this if the text terminal does not support color.

-PAGE

Displays the help text one screenful at a time. This is the default. The output is paused for input after one screenful of text is displayed, where you can continue by pressing the following: ■

spacebar—displays the next page

■

h-key—displays a complete list of options

■

q-key—quits from the pager

Note: Output displayed with the pager is not saved to the log file specified by SET LOG FILE command. Note: The pager is not enabled if the help text is less than a screenful, when output is redirected to a file, or when running HELP in the GUI window. -NOPAGE

Disables the help text paging display feature.

Displays the error message of the specified message ID.

Example The following is an example of the Tcl mode system prompt and the HELP command: TCL_SETUP> help set_current_module

Related Command SEARCH

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INVERT MAPPED POINTS INVert MApped Points … [-Golden |-Revised] (LEC Mode)

When switching the system from Setup mode to LEC mode, Conformal automatically maps key points and places them in the System class of mapped points. Use this command to invert the mapping phase for any mapped points. This command also places the points in the User class of mapped points. In the GUI Mapping Manager and in reports, a (-) sign represents an inverted-mapped point. A (+) sign represents a non-inverted mapped point.

Parameters gate_id

Inverts the mapping phase for the specified gates (identified by number). Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname

Inverts the mapping phase for the specified instances.

pin_pathname

Inverts the mapping phase for the specified pins.

-Golden

Specifies that the point identifier refers to the Golden design. This is the default.

-Revised

Specifies that the point identifier refers to the Revised design.

Related Commands ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS

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Encounter Conformal Equivalence Checking Reference Manual Command Reference SET MAPPING METHOD SET NAMING RULE

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LICENSE LICense [] (Setup / LEC Mode)

Displays information about the currently installed Conformal license. By default, this command displays all available Conformal licenses.

Parameters

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Displays information for a specific license. You can select one of the following: ■

conformal_explorer

■

conformal_asic

■

conformal_ultra

■

conformal_custom

■

conformal_low_power

■

conformal_low_power_gxl

■

conformal_eco

■

rtl_compiler_verification

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MAP ECO PATCH MAP ECo Patch [-NOConstraint] [-REPlace] (Setup Mode)

Maps the ECO patch(es), specified by the ADD ECO PATCH command, to the available ECO cells. The available ECO cells are specified by the ADD ECO CELL command. The target technology libraries are specified by the ADD ECO LIBRARY command.

Parameters

Specifies the file name for the mapped netlist.

-NOConstraint

Specifies that the mapping process will use the cells in the ECO library to implement the patch. Use this option for a pre-mask ECO.

-REPlace


Related Commands ADD ECO CELL ADD ECO LIBRARY ADD ECO PATCH OPTIMIZE PATCH

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MAP KEY POINTS MAP KEy Points (LEC Mode)

Automatically maps all key points, then displays a summary of the mapped points in the Golden and Revised designs. In addition, if there are any unmapped points, Conformal displays a summary of the unmapped points in the Golden and Revised designs. Conformal automatically executes this command the first time you exit the Setup system mode and when the flattened gate model changes.

Related Commands ADD MAPPED POINTS ADD RENAMING RULE DELETE MAPPED POINTS DELETE RENAMING RULE REPORT MAPPED POINTS REPORT RENAMING RULE REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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MOS2BUFIF MOS2BUFIF [-MODule mod1 mod2… modn | -ALL] [-FORce | -DRIVENmos | -INStance ins1 ins2… insn] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. After abstraction for emulation and test support, this transforms all of the unidirectional NMOS devices to BUFIF1 and unidirectional PMOS devices to BUFIF0.

Parameters -MODule mod1 mod2… modn Transforms the specified list of modules. Note: If you do not specify modules, Conformal transforms the current root module. -ALL

Transforms all modules.

-FORce

Converts all [r]nmos to bufif1, [r]pmos to bufif0, [r]cmos to a bufif0 – bufif1 pair. This is the default.

-DRIVENmos

Converts only those MOS devices that are driven by a logic gate or a primary input.

-INStance ins1 ins2… insn Transforms the specified instances. You can only use this option when you have specified a single module. (Refer to the -module definition.) Note: The following options are mutually exclusive. That is, you can only use one of these options in the command: ■

-force

■

-drivenmos

■

-instance

Conformal issues a warning when the specified instances do not exist or they are not unidirectional.

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-Golden

Applies transformation in the Golden design. This is the default.

-Revised

Applies transformation in the Revised design.

Example Sample Netlist Transformation: The following is the original netlist: nmos (out, in, ctl) ; pmos (out, in, ctl) ;

The MOS2BUFIF command transforms the netlist to the following: bufif1 (out, in, ctl) ; bufif0 (out, in, ctl) ;

Related Command ABSTRACT LOGIC

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MOVE INSTANCE DOWN MOVe INstance Down -MODule -From -TO [-Golden | -Revised] (Setup Mode)

Moves instances in the same parent module.

Parameters -MODule Specifies the parent module -From Specifies the instance that is to be moved. -TO Specifies the destination instance or list of instances. -Golden

Applies in the Golden design. This is the default.

-Revised

Applies in the Revised design.

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OPEN SCHEMATICS OPEn SChematics [-Golden | -Revised] [full pathname] (Setup / LEC Mode)

Opens the schematic viewer and displays the root module schematics. This command cannot be used in the non-graphic mode.

Parameters -Golden

Specifies that the path is in the Golden design.

-Revised

Specifies that the path is in the Revised design.

full pathname

Opens a schematic for the specified path.

Related Commands CLOSE SCHEMATICS DIAGNOSE REPORT GATE

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OPTIMIZE PATCH OPTimize PAtch -WORKdir -LIBrary [-RCExec ] [-SDC ] [-VERbose] [-KEEPHierarchy] [-CLEANUP] [-AVOID *] [-USE *] [-POSTLIBscript <script_name>] [-POSTSYNscript <script_name>] [-PRESYNscript <script_name] [-NETnaming ] [-INStancenaming ] [-SEQuentialnaming ] (Setup Mode)

Writes out an RTL Compiler script (run_rc.tcl) in the working directory that will optimize the patches and execute the script. After OPTIMIZE PATCH successfully completes, the ECO design will be in memory and can be written out. The optimized patches will be in the working directory. Important Before running this command, you must run the APPLY PATCH -keephierarchy command.

Parameters -WORKdir Specifies the name of the working directory for the optimized patches. -LIBrary Specifies the name of the library files. If the library name contains a relative path, the path should be relative to the directory declared in -workdir.

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-RCExec Specifies the path to the RTL Compiler executable. If this is not specified, the software will use the rc command in your search path. -SDC Specifies the name of the SDC file. If the SDC filename contains a relative path, the path should be relative to the directory declared in -workdir. -VERbose

Outputs all RTL Compiler messages. By default, the command only outputs error messages.

-KEEPHierarchy

Specifies that the ECO changes will be put in a submodule.

-CLEANUP

Deletes the generated files.

-AVOID * Avoids the specified library cells. This accepts wildcards. -USE *

Uses the specified library cells. This accepts wildcards. Note: The order that you specify the -AVOID and -USE options is significant. For example: -avoid * -use NAND2 INV2

avoids all the library cell types except NAND2 and INV2. If these options are specified in the following order: -use NAND2 INV2 -avoid *

then no cell types will be available for mapping. -POSTLIBscript <script_name> Specifies the script to run after reading in the libraries. -POSTSYNscript <script_name> Specifies the script to run after each patch is synthesized. -PRESYNscript <script_name> Specifies the script to run before each patch is synthesized. -NETnaming Specifies the net naming format of the ECO nets. For example, for eco_net_%d, the %d will be an integer that makes the net name unique.

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-INStancenaming Specifies the instance naming format of the ECO combinational cells. For example, for eco_instance_%d, the %d will be an integer that makes the instance name unique. -SEQuentialnaming Specifies the instance naming format of the ECO registers and latches. For example, eco_%s, where %s is the original register name.

Example The following script reads in the original netlist and patch, then runs OPTIMIZE PATCH to map and optimize the ECO changes: read library typical.lib -liberty read design top.gv patch1.v apply patch mod1 mod1_eco -keephierarchy optimize patch -workdir rc_work -library ../typical.lib write design top.eco.gv -replace

Related Commands APPLY PATCH

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PIN GROUP PIN GRoup [-Golden | -Revised] [-DEScend | -ASCend] [-ADDEXPression ] [-ADDList [#:#] " ..."] [-ALL | -Module " ..."] (Setup Mode)

Note: This is a Conformal Custom command. Combines a group of single nets or pins into a bus. The Conformal software uses the following two default patterns to group pins or nets into busses: ■

Name[#]

■

Name<#>

For example, nets blb[3] blb[4] blb[5] will be grouped into bus blb[5:3], and pins wladd<1> wladd<2> wladd<3> will be grouped into bus wladd[3:1].

Parameters -DEScend

Defines the bus in descending numerical order. This is the default.

-ASCend

Defines the bus in ascending numerical order.

-ADDEXPression

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Specifies expression(s) for rules on signals to bus. You can specify your own renaming mapping of specific names to two default patterns, so that it recognizes those names as buses also. For example: -ADDexpression "mybus_%d_bar" "mybus_bar[@1]"

maps the following names into the first default bus name: mybus_12_bar mybus_13_bar mybus_14_bar => mybus_bar[12] mybus_bar[13] mybus_bar[14]

then the renamed names will be further grouped into bus mybus_bar[14:12] The renaming mapping syntax: mybus_%d_bar" "mybus_bar[@1]"

is defined in the ADD RENAMING RULE command. -AddList [#:#] “ ” Allows you to bus random signals. These nets can be single nets or mixed single nets and complete busses. The number of nets defined must be equal to the bus range. If a bus range more than the number of nets is defined a "-" character is used as a placeholder for that bit position. -ALL

Specifies that when pins of a module are converted to a bus, all instantiations of that module need to be updated. This is the default.

-Module “ ” Specifies the module that needs to be updated pins of that module are converted to a bus.

Related Command GROUP

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PRINTENV PRINTENV [] (Setup / LEC Mode)

Displays environment variable values.

Parameters

Prints the value of the specified variable. If you do not specify a variable, this command displays the value of every environment variable.

Related Command SETENV

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PROVE PROve <[-Golden | -Revised] identifier> <-ONe |-ZEro | [-Revised | -Golden] identifier> [-NOInvert | -Invert | -Both] (LEC Mode)

Starts a process that shows whether the specified gates are equivalent or nonequivalent. The proof process checks equivalency for one of the following pairs: ■

One gate in each of the Golden and Revised designs

■

Two gates in the Golden design

■

Two gates in the Revised design.

Use the ADD DYNAMIC CONSTRAINTS command to specify constraints you want to use during this proof process.

Parameters -Golden

Specifies that the first prove point is in the Golden design. This is the default.

-Revised

Specifies that the first prove point is in the Revised design.

identifier

Uses this gate from the specified design as the first prove point. The identifier will be one of the following: ■

Gate identification number

■

Instance path

■

Pin path

Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -ONe

Proves whether the specified gate is equal to a one value.

-ZEro

Proves whether the specified gate is equal to a zero value.

-Revised

Specifies that the second prove point is in the Revised design. This is the default.

-Golden

Specifies that the second prove point is in the Golden design.

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-NOInvert

Proves for equivalence. This is the default.

-Invert

Proves for inverted equivalence.

-Both

Proves for either non inverted or inverted equivalence.


Related Commands ADD DYNAMIC CONSTRAINTS DELETE DYNAMIC CONSTRAINTS DIAGNOSE REPORT COMPARE DATA REPORT DYNAMIC CONSTRAINTS

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READ CPF REAd CPf [-GOLden | -REVised | -BOTH] [-VERbose] (Setup Mode)

Note: This is a Conformal Low Power command. Reads in the Common Power Format (CPF) files. Cadence recommends reading in all the CPF files at once with this command. Any susequent runs will replace all the low power information issued by the previous READ CPF command. All READ DESIGN and READ LIBRARY commands should be run before running this command.

Parameters

Specifies the name of the Common Power Format file(s).

-GOLden

Reads in the CPF files for the Golden design. This is the default.

-REVised

Reads in the CPF files for the Revised design.

-BOTH

Reads in the CPF files for both the Golden and Revised designs.

-VERBose

Displays additional messages during execution.

Example The following command reads the lib.cpf and design.cpf files and checks that they are specified correctly: read cpf lib.cpf design.cpf

Related Commands COMMIT CPF REPORT CPF LOGIC

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READ DESIGN REAd DEsign [-ROot ] [-CONFiguration | -NOCONFiguration] [-ROOTConfig ] [-VErilog | -VERILOG2K | -SYStemverilog | -VHdl [93 | 87] | -SPice | -Ndl | -EDIF |-LIBErty] [-File ] [ | -REPlace | -APPend] [-Define ] [-Map ] [-MAPRecursive ] [-MAPFile ] [-LIBRary ] (this option is the same as -Map) [-STATEtable | -NOSTATEtable] [-BBOXUNResolve] [-BLAST_inst_port] [-RAngeconstraint | -NORAngeconstraint] [-INITial_value] [-VHDLESCaped_to_verilog] [-CONTINUOUSASSIGNment ] [-NOZPUSHing | -ZPUSHing] [-ENUMConstraint] [-VMEM_LIB] [-VMEM_ULTRA] [-SUPPLY | -NOSUPPLY] [-UNCompress ] [-UNZip ] [-PARAmeter [-INT | -STR | -ENUM] ] (combined with -ROot option) [-ARchitecture ] [-FUnctiondefault [0 | 1 | x]] [-NOKeep_unreach | -Keep_unreach] [-SEnsitive | -NOSEnsitive] [-NOELaborate] [-EXClude ] [-VERBose] [-OPTimize | -NOOPTimize] [-LAstmod] [-MErge BBox] [-Golden | -REVised] (Setup Mode)

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Reads in the Golden and Revised designs. Important Review these important reminders before using the READ DESIGN command: ■

Use the SET NAMING RULE command first if you intend to read in an RTL design that requires specific naming conventions.

■

Use the SET UNDEFINED CELL command before the READ DESIGN command if your design includes undefined cells that should be treated as blackboxes.

Note: ■

If your design includes duplicate modules, Conformal uses the first module and ignores later ones. However, you can use the -lastmod option to specify that Conformal use the last module and ignore the earlier ones.

■

Use the tilde character (~) to shorten the path of the file.

■

Use the backslash character (\) at the end of a line to show that the command you are entering continues on the next line.

Supported Options The following Verilog and VHDL considerations are offered: ■

Use the -file option with a Verilog Command file list. However, only the -v, -y, +incdir, +libext, and +define options are supported. Additionally, use the -yd option to treat library modules as design modules.

■

The VHDL option supports all VHDL constructs and all standard and IEEE packages, including synthesis packages. It has an elaboration engine and RTL logic generation that support most RTL VHDL synthesis subset constructs (see below for details). For most non-synthesizable VHDL constructs, Conformal displays warning messages.

VHDL and Verilog 2001 Library Mapping You can specify how VHDL and Verilog 2001 libraries are mapped using the READ DESIGN command’s -map, -mapfile, or -library options. The -map and -library options work the same in that they map logical library names to physical directories. You can use multiple -map commands to map multiple physical directories to one logical library. Use the -mapfile option for more specific library mapping,

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Encounter Conformal Equivalence Checking Reference Manual Command Reference such as specifying that a list of files must be compiled into a specified library. If you read in a file without specifying its library mapping, that file is stored in a default library called work. Note: You can map a file into more than one library. In this case, the file is stored in each library for which it is mapped. See the “VHDL Support” and “Verilog Support” appendices in the Encounter Conformal Equivalence Checking User Guide for additional information, including examples on library mapping.

Parameters

Reads in the specified file. (Required.)

-ROot module_name

The specified module is the top root module.

-CONFiguration

Supports VHDL configuration constructs. This is the default.

-NOCONFiguration

Does not interpret VHDL configuration.

-ROOTConfig The design includes the specified configuration for the top-level module. Note: This option applies to only VHDL designs. Use this option when the design includes multiple configurations for the top-level module. When you use the -rootconfig option, you must also use the -root module_name option (above). -VErilog

Specifies that this design is a Verilog design. (Use this option for Verilog designs that comply with IEEE 1364-1995.) This is the default.

-VERILOG2K

Specifies that this design is a Verilog2K design (Use this option for Verilog designs that comply with IEEE 1365-2001).

-SYStemverilog

Specifies that this design is a SystemVerilog design.

-VHdl

Specifies that this design is written in VHDL with the specified standard: VHDL-93 (Use this option for VHDL designs that comply with IEEE Std 1076-1993.) This is the default.

93

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VHDL-87 (Use this option for VHDL designs that comply with IEEE Std 1076-1987.)

87

Note: The Conformal software supports multiple uses the -vhdl 93 and -vhdl 87 options. See the example. -SPice

Specifies that the design is a SPICE netlist design.

-Ndl

Specifies that the design is an NDL design.

-EDIF

Specifies that the design is an EDIF design.

-LIBErty

Specifies that the design has a Liberty library format type. (Use this option to qualify the library as Liberty.)

-File Reads in the specified command file as a design. Note: This option is for Verilog or VHDL command file lists. The options for are described in Table 2-1 on page 244 for Verilog and Table 2-2 on page 245 for VHDL. -REPlace

Removes all designs that were previously read in, and replaces them with the specified design.

-APPend

Appends the design to the one that was previously read. For example, you can use this option to fix a top module and then read it in again without parsing the entire design file again: read design top.v -append -lastmod

Note: The top module cannot pass parameters to modules that are read in previously. -Define

Defines ìfdef variable names in Verilog.

-Map Reads in files for the specified from . Use this option to read in all of the VHDL or Verilog files in the specified library path for the given library name. You can also map multiple directories to a single library. For example: read design -vhdl top.vhd -map mylib /design/path1 \ -map mylib /design/path2

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-MAPRecursive This option has the same function as -Map, but it searches for all VHDL or Verilog files recursively down to the subdirectories of the . -Map searches VHDL or Verilog files under the and will not search any VHDL files under the subdirectories of . -MAPFile Reads in the specified and includes them in the . Use this option to specify the files that belong to a given library. The file list terminates with the next option or the end of the READ DESIGN command. You can also use multiple -mapfile options to specify multiple files in a library. For example, the following two commands are the same: read design -vhdl top.vhd -mapfile \ mylib x1.vhd -mapfile mylib x2.vhd read design -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd

-LIBRary Reads in the specified file in the given library and path for user-defined VHDL libraries. (This option is the same as -map.) -STATEtable

Enables support for Synopsys Liberty state tables. This is the default. Note: This option supersedes the SET STATETABLE command.

-NOSTATEtable

Disables support for Synopsys Liberty state tables.

-BBOXUNResolve

Specifies that unresolved semantics as unsupported constructs (in VHDL) will be blackboxed instead of erroring out.

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-BLAST_inst_port

Allows the cell model to have a bus pin while the instantiation is bit-blasted. By default, instantiations that contain bit-blasted connections are errored out. The Verilog standard does not allow these connections.

-RAngeconstraint

When a variable is of type integer with a value range, a value check is made against the range. If a value is out of range, it will be interpreted as don’t care. This is the default. For example: variable v : integer range 3 to 5;

With -RAngeconstraint, v will be interpreted as: ((v>=3 && v<=5)? v : 3’bx).

Note: This option applies only to VHDL designs. -NORAngeconstraint

Specifies that no value check is made against the integer value range. Note: This option applies only to VHDL designs.

-INITial_value

Specifies that the variable’s initial value will not be ignored. Note: This option applies only to VHDL designs.

-VHDLESCaped_to_verilog Specifies that if the content between ‘\’ pairs does not contain any white space, the new name is the escaped content. For example, \A_B_C_\ changes to \A_B_C_. In all other cases, the VHDL escaped name is unchanged. For example, \1 2\ is unchanged. -CONTINUOUSASSIGNment Specifies that continuous assignment in the design should be interpreted as uni-directional or bi-directional assignment. -NOZPUSHing

Does not pushes tristate toward module output. This is the default.

-ZPUSHing

Pushes tristate toward module output.

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-ENUMConstraint

When a variable is of type of enumeration, a value check is made against the enumeration range. If a value is out of range, it will be interpreted as don’t care. For example: variable v : day;

Where day is an enumeration of {sun, mon, tue} With -ENumconstraint, v will be interpreted as: ((v>=sun && v<=tue)? v : 2’bx).

-VMEM_LIB

Reads in the RTL model containing the Conformal Memory Primitive. This option is a Conformal Custom option. Note: Without the -vmem_lib option, Conformal does not recognize the Conformal Memory Primitive.

-VMEM_ULTRA

Reads in the RTL model containing the Conformal Memory Primitive for checking by Conformal Ultra. To use this option, you must have a Conformal Ultra license. This option is a Conformal Ultra option. Note: When you use this option, no debugging is allowed. Use the -vmem_lib option for memory verification.

-SUPPLY

Keeps all Verilog supply0 and supply1 type nets unchanged. This is the default.

-NOSUPPLY

Converts the Verilog supply0 and supply1 type nets to Verilog wire type nets.

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-UNCompress Reads in the specified compressed file. By default, the Conformal software uses gunzip to unzip the file into the /tmp directory. You can control the tool and directory used with UNIX variables CONFORMAL_UNCOMPRESS and CONFORMAL_TMP. -UNZip This option has the same function as -UNCompress except that it can include a list of filenames. For example: read design fileABC -UNZ zip1 zip2 zip3

The list of filenames end when a subsequent option is specified, or if it is at the end of the command line. Note: Specifying -uncompress or -unzip is optional for gunzipped files because the Conformal software can automatically recognize this file type.

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-PARAmeter [-INT | -STR | -ENUM] Assigns design parameters or replace existing design parameters. To specify multiple parameters, use the -parameter option for each parameter you want to set. For example: read design filename -parameter parm1 value1 \ -parameter -int parm2 value2

This option applies to both Verilog and VHDL files. (Combine with -root.) When using the -parameter -int command, the will be converted to integer value, which can be a positive integer (1), negative integer (-1), an integer value recognized as a string ("1"/"-1"), or a Verilog style integer ("16’h0001"). When using a Verilog style integer, the value must be specified between double-quotes (" "). When using the -parameter -str command, the will be saved as a string. When using the -parameter -enum command, the will be converted to a VHDL enumeration literal. For example, the following command sets the parameter P4 to VHDL enumeration literal GREEN: read design -root mod1 filename \ -parameter -enum P4 GREEN

Note: Any value that is not recognized as an unsigned decimal integer value is interpreted as string value. Note: If -int or -str is not specified, then the parameter value will be interpreted as an integer if it is not between double-quotes (" "), and as a string if it is between double-quotes. Therefore, if you want to specify a Verilog format value, it must be between double-quotes and used with the -int option.

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-ARchitecture architecture_name Reads in files with the specified architecture. Use this option when multiple architectures of the same root design are compiled. This option is associated with the -configuration option, otherwise only one architecture is kept for each entity. -FUnctiondefault

Specifies the default return value for unspecified or incompletely specified functions. 0

Returns zero.

1

Returns one.

x

Returns x.

-NOKeep_unreach

Remove any unreachable DFF or D-Latch in a module during RTL synthesis. This is the default.

-Keep_unreach

Keeps any unreachable DFF or D-Latch in a module during RTL synthesis.

-SEnsitive

Specifies that the design is case sensitive. This is the default.

-NOSEnsitive

Specifies that the design is not case sensitive.

-NOELaborate

Reads in multiple files of different languages.

-EXClude Specifies files to exclude when reading in the design. This accepts the wildcard. Note: You cannot use multiple wildcards with this option. -VERBose

Displays the verbose messages of parsing and translating each design module.

-OPTimize

Optimizes redundant logic (in library cells) that can affect the way Conformal interprets the design. This is the default. Note: Using this option does not always optimize all redundant logic. See the following example: read design file1 file2 file3 -nooptimize \ -optimize -nooptimize -replace

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-NOOPTimize

Preserves redundant logic in Library cells. See the example listed above (-optimize).

-LAstmod

If duplicate modules exist, the Conformal software uses the first module and ignores the later ones by default. Use this option to specify that Conformal use the last module and ignore earlier ones.

-MErge BBox

Replaces all blackboxed modules in the design space with modules in the library space.

-Golden

Designates this design “Golden.” This is the default.

-REVised

Designates this design “Revised.”

Table 2-1 Supported Verilog Command-Line Options The following table lists the Verilog command options that Conformal supports. Supported:

(Design data file)

A list of the design files.

-v

(Library file)

A list of library files.

-y

(Library directory)

A list of library directories. Conformal searches for modules not defined in the design files. Conformal reads in these modules as library modules.

+incdir+…

(Include directories)

A list of “include” directories containing design files. This option is similar to the ADD SEARCH PATH command.

+libext+ (Library extensions) …

A list of library extensions you can include when using the -y option. The default is .v.

+define+…

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(Define macros)

A list of macro names you can include in the `define statement

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-yd

(Design directory)

A list of directories. Conformal searches for modules that are not defined in the design files. Conformal reads these modules in as design modules.

-f

(another command file)

Table 2-2 Supported VHDL Command-Line Options The following table lists the VHDL command options that Conformal supports. Supported:

Individual design file

-map

Map logical library name to a directory

-mapfile

Map logical library name to a list of files

-library

Map logical library name to a directory

Examples The following example demonstrates how to use the backslash character to show that your command continues on the next line. read design tran1.spi tran2.spi tran3.spi \ -spice -revised

In the following example, only ent2.vhdl and arch2.vhdl will be parsed according to VHDL 87 syntax rules. All the other files will be parsed according to VHDL 93 syntax rules. read design ent0.vhdl arch0.vhdl \ -vhdl 93 ent1.vhdl arch1.vhdl \ -vhdl 87 ent2.vhdl arch2.vhdl \ -vhdl ent3.vhdl arch3.vhdl

Related Commands ADD NOTRANSLATE MODULES

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ADD RENAMING RULE ADD SEARCH PATH DELETE NOTRANSLATE MODULES DELETE RENAMING RULE DELETE SEARCH PATH READ LIBRARY REPORT DESIGN DATA REPORT MESSAGES REPORT MODULES REPORT NOTRANSLATE MODULES REPORT RENAMING RULE REPORT RULE CHECK REPORT SEARCH PATH SET DIRECTIVE SET NAMING RULE SET ROOT MODULE SET RULE HANDLING SET STATETABLE SET UNDEFINED CELL WRITE DESIGN WRITE HIER_COMPARE DOFILE

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READ FSM ENCODING REAd FSm Encoding [-Golden | -Revised] (Setup Mode)

Directs Conformal to read in a file that defines new Finite State Machine (FSM) encoding. By default, Conformal reads binary encoding when building an FSM. Therefore, if your gate netlist uses different encoding (for example, one-hot), you must use the READ FSM ENCODING command to specify the correct encoding. See the example of an FSM encoding file below.

Parameters

Reads in the specified file. This option is a required filename that contains the encoding differences.

-Golden

Uses this library with the Golden design. This is the default.

-Revised

Uses this library with the Revised design.

Examples The following example shows the need for the READ FSM ENCODING command. In this case, the user was alerted to encoding differences during mapping. The Golden design showed two registers, while the Revised showed four registers. The following is an example of an FSM encoding file that replaces the binary encoding with one-hot encoding: .fromstates current_state_reg[1] current_state_reg[0] .tostates current_state_reg[3] current_state_reg[2] current_state_reg[1] current_state_reg[0] .begin 00 0001 01 0010 10 0100 11 1000 .end

In this example, between .begin and .end: ■

.fromstates are the left-hand side states

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.tostates are the right-hand side states

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READ LEF FILE REAd LEf File [-GOLden | -REVised] (Setup Mode)

Reads in the LEF file. For each cell in the LEF database with matching library cell, this command will do the following: ■

Report library cell with ports that are not in the LEF file

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Report non-power or ground ports in the LEF file and not in library

■

Add all ports in the LEF file, and not in library to library cell

Parameters

Specifies the name of the LEF file.

-Golden

Reads in the LEF file for the Golden design. This is the default.

-Revised

Reads in the LEF file for the Revised design.

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READ LIBRARY REAd LIbrary [-VErilog | -VERILOG2K | -SYStemverilog | -VHdl [93|87] | -Liberty] [-SEnsitive | -NOSEnsitive] [-EXtract] [ | -REPlace | -APPend] [-Define ] [-Map ] [-MAPRecursive ] [-MAPFile ] [-CONFiguration | -NOCONFiguration] [-VERBose] [-SUPPLY | -NOSUPPLY] [-UNCompress ] [-UNZip ] [-OPTimize | -NOOPTimize] [-STATEtable | -NOSTATEtable] [-LAstmod] [-MULTIPLE_LIBraries] [-Both | -Golden | -Revised] [-NOShare] [-NOELaborate] [-EXClude ] (Setup Mode)

Reads in the library model descriptions for Verilog, VHDL, or Liberty designs. The library is either a Verilog simulation library or a Synopsys Liberty library. It is read for the Golden, Revised, or both designs. Note: For RTL to gate formal equivalence checking, use simulation libraries instead of synthesis libraries because design verification signoff happens for simulation libraries—not for synthesis libraries. The READ LIBRARY command must be used before the READ DESIGN command if the design is Verilog, VHDL, or Liberty. Note: Library in this context refers to the technology library, such as ASIC cell and memory definitions. See READ DESIGN for information on reading VHDL libraries and packages. Important

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If there are duplicate modules, the Conformal software uses the first module and ignores later ones. However, you can use the -lastmod option to specify that Conformal use the last module and ignore earlier ones.

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Use the backslash character (\) at the end of a line to show that the command you are entering continues on the next line.

■

Use the tilde character (~) to shorten the path of the file.

Parameters

Reads in the specified file(s). This option is a required filename that contains the Verilog simulation library or the Synopsys Liberty library. This accepts wildcards.

-VErilog

Contains the Verilog library model descriptions. This is the default. Note: This supports NC-Protect and Cadence encryption.

-VERILOG2K

Contains Verilog2k library model descriptions.

-SYStemverilog

Contains SystemVerilog library model descriptions.

-VHdl

Specifies that the library is written in VHDL. The VHDL file is of the specified standard: 93

VHDL-93 (Use this option for VHDL designs that comply with IEEE Std 1076-1993.) This is the default.

87

VHDL-87 (Use this option for VHDL designs that comply with IEEE Std 1076-1987.)

Note: The VITAL format is unsupported. Note: This supports NC-Protect and Cadence encryption. -Liberty

Specifies that the library filename is in the Synopsys Liberty format. Note: This supports Cadence encryption.

-SEnsitive

Specifies that the library model’s descriptions are case sensitive. This is the default.

-NOSEnsitive

This library model’s descriptions are not case sensitive.

-EXtract

Abstracts the gate information from any transistor library models. Note: This option requires a Conformal Custom license.

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-APPend

Appends this library to the one that was previously read. For example, you can use this option to fix a top module and then read it in again without parsing the entire library file again: read library top.v -append -lastmod

Note: The top module cannot pass parameters to modules that are read in previously. -Define

Defines ìfdef variable names in Verilog.

-Map Reads in files for the specified library_name from library_path. Use this option to read in all of the VHDL or Verilog files in the specified library path for the given library name. You can also map multiple directories to a single library. For example: read library -vhdl top.vhd -map mylib /design/path1 \ -map mylib /design/path2

-MAPRecursive This option has same function as -Map, but it searches for all VHDL or Verilog files recursively down to the subdirectories of the . -Map searches VHDL or Verilog files under the and will not search any VHDL or Verilog files under the subdirectories of . -MAPFile Reads in the specified files (file_name…) and include them in the library (library_name). Use this option to specify the files that belong to a given library. The file list terminates with the next option or the end of the READ LIBRARY command. You can also use multiple -mapfile options to specify multiple files in a library. For example, the following two commands are the same: read library -vhdl top.vhd -mapfile \ mylib x1.vhd -mapfile mylib x2.vhd read library -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd

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-NOCONFiguration

Does not interpret VHDL configuration.

-VERBose

Displays the verbose messages of parsing and translating each library module.

-SUPPLY

Keeps all Verilog supply0 and supply1 type nets unchanged. This is the default.

-NOSUPPLY

Converts the Verilog supply0 and supply1 type nets to Verilog wire type nets.

-UNCompress Reads in the specified compressed file. By default, the Conformal software uses gunzip to unzip the file into the /tmp directory. You can control the tool and directory used with UNIX variables CONFORMAL_UNCOMPRESS and CONFORMAL_TMP. -UNZip This option has the same function as -UNCompress except that it can include a list of filenames. For example: read design fileABC -UNZ zip1 zip2 zip3

The list of filenames end when a subsequent option is specified, or if it is at the end of the command line. Note: Specifying -uncompress or -unzip is optional for gunzipped files because the Conformal software can automatically recognize this file type. -OPTimize

Removes redundant buffers in library cells. This is the default. Note: Using this option does not always optimize all redundant logic. See the following example: read library file1 file2 file3 -nooptimize -optimize \ -nooptimize -replace

-NOOPTimize

Preserves redundant buffers in library cells. See the example listed above (-optimize).

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-STATEtable

Enables support for Synopsys Liberty state tables. This is the default. Note: This option supersedes the SET STATETABLE command.

-NOSTATEtable


-LAstmod

If duplicate modules exist, Conformal uses the first module and ignores the later ones by default. Use this option to specify that Conformal use the last module and ignore earlier ones.

-MULTIPLE_LIBraries If duplicate modules exist, Conformal uses the first modules and ignores the later ones by default. Use this option to specify that Conformal store duplicated liberty modules if they are in a different library. -Both

Uses this library for both the Golden and Revised designs. This is the default.

-Golden

Uses this library with the Golden design.

-Revised

Uses this library with the Revised design.

-NOShare

Does not share the library files for both the Golden and Revised designs, and appends the library files to both designs. When this option is used together with the default -Both option, this is the equivalent of running the following two commands: read library -golden read library -revised

By default, the Conformal software shares the library files for both the Golden and Revised designs, and does not append the library files to either design. -NOELaborate

Reads in multiple files of different languages. With this option, you can defer the binding of entity or module instantiations. This is for cases when you have mixed library files in VHDL and Verilog languages, where a VHDL entity in one library file instantiates a Verilog module, and a Verilog module in another library file instantiates a VHDL entity.

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-EXClude Specifies files to exclude when reading in the library. This accepts the wildcard. Note: You cannot use multiple wildcards with this option.

Related Commands ADD NOTRANSLATE MODULES ADD RENAMING RULE ADD SEARCH PATH DELETE NOTRANSLATE MODULES DELETE RENAMING RULE DELETE SEARCH PATH READ DESIGN REPORT DESIGN DATA REPORT MESSAGES REPORT MODULES REPORT NOTRANSLATE MODULES REPORT RENAMING RULE REPORT RULE CHECK REPORT SEARCH PATH SET DIRECTIVE SET RULE HANDLING SET STATETABLE SET UNDEFINED CELL

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Encounter Conformal Equivalence Checking Reference Manual Command Reference WRITE HIER_COMPARE DOFILE WRITE LIBRARY

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READ MAPPED POINTS REAd MApped Points [-GOLDen_prefix ] [-REVIsed_prefix ] [-EXACT_name] (LEC Mode)

Reads in the mapped point information you created with the WRITE MAPPED POINTS command. By default, Conformal automatically maps key points during the transition from Setup to LEC mode. And if the key points are already mapped, Conformal ignores any mapped point information in the file. Thus, to prevent Conformal from automatically mapping key points during the transition from Setup to LEC mode and enable Conformal to read in mapped point information completely from the file, do one of the following: ■

Use the set flatten model -nomap command before you set the system mode to LEC.

■

Use the set system mode lec -nomap command to suppress automatic mapping during the transition to LEC mode.

Use the tilde character (~) to shorten the file’s path. Note: Use the Golden and Revised prefix options to specify the hierarchy of the instance name. If a hierarchical submodule’s map point information is written to a file, it can be read in at a higher level module or the top root module with the specified hierarchical prefix string.

Parameters

Reads mapped point information from the specified file.

-GOLDen_prefix string Appends this Golden prefix string to the instance names. This option lets Conformal read the mapped point file for a higher-level module containing hierarchy. -REVIsed_prefix string Appends this revised prefix string to the instance names. This option lets Conformal read the mapped point file for a higher-level module containing hierarchy.

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-EXACT_name

Specifies an exact match for the names specified in the file. This can help speed up the process of reading files where many names are incorrect.

Related Commands SET FLATTEN MODEL WRITE MAPPED POINTS

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READ MEMORY PRIMITIVE REAd MEmory Primitive (Setup Mode)

Note: This is a Conformal Custom command. Reads in Verilog memory primitive simulation models that were created using the Conformal memory primitive generator. This command creates a memory-friendly, synthesized view that you can use for comparison with a memory circuit. Important Read in designs that use the memory primitive after you use this command.

Parameters

Specifies the files to read in.

Related Command READ DESIGN

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READ ROM PRIMITIVE REAd ROm Primitive [-CODE_FILE ] [-CODE_FILE_FORMAT ] (Setup Mode)

Note: This is a Conformal Custom command. Reads in Verilog ROM primitive simulation models that were created using the Conformal ROM primitive generator.

Parameters

Specifies the file to read in.

-CODE_FILE Specifies the code file that will initialize the ROM. -CODE_FILE_FORMAT Specifies the format of the code file. If you do not specify the -code_file_format option, the software uses the format selected during primitive generation.


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READ RULE CHECK REAd RUle Check <-EXClude |-INClude> [-Design | -Library] [-GOLden | -REVised] (Setup Mode)

Performs incremental rule checks. The first time you run a session, write the rule violations into a rule file using the write rule check -golden (or -revised) command. For later runs, exclude the violations already flagged with the read rule check -exclude command. Use the tilde character (~) to shorten the path of the file.

Parameters

Specifies the name of the file that contains rule violations from a previous session.

-EXClude

Excludes checks for violations noted in the specified file.This option works as a filter; therefore, use it after the READ DESIGN command.

-INClude

Includes checks for violations noted in the specified file. This option lets you reinstate violations that were previously excluded.

-DEsign

Reads only design rule check violations. If you do not specify -design or -library, Conformal reads rule check violations from both designs and libraries.

-LIbrary

Reads only library rule check violations. If you do not specify -design or -library, Conformal reads rule check violations from both designs and libraries.

-Golden

Applies this command to the Golden design. This is the default.

-Revised

Applies this command to the Revised design.

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Examples In the following example, the second report rule check will not report any rules. read design g.v -golden read design r.v -revised write rule check rule.g -golden -replace write rule check rule.r -revised -replace read design g.v -golden -replace read design r.v -revised -replace report rule check -verbose -both read rule check rule.g -exclude -golden read rule check rule.r -exclude -revised report rule check -verbose -both

Related Command WRITE RULE CHECK

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READ PATTERN REAd PAttern [-Verilog | -SPice ] [-Golden | -Revised | -Both] [-SEnsitive | -NOSEnsitive] [-LAstmod] (Setup Mode)

Note: This is a Conformal Custom command. Reads in the transistor description from a file that Conformal Custom applies to the Golden and Revised designs. (The file format type is either Verilog or SPICE.) The transistor description represents a pattern that Conformal Custom seeks during abstraction. When Conformal Custom detects a pattern, it substitutes a user-specified functional model. Before this command can be executed correctly, you must provide the user-specified functional model using the READ LIBRARY command. The transistor description file and functional model have the same module and port names; port direction can be different, but, neither the transistor description file nor the library database can contain submodules—every cell must be flat. Use the tilde character (~) to shorten the path of the file.

Parameters

A required filename. It contains the transistor abstraction information.

-Verilog

The transistor description file format is Verilog. This is the default.

-SPice

The transistor description file format is SPICE.

-Golden

Applies the file’s sub-circuit information to the Golden design. This is the default.

-Revised

Applies the file’s sub-circuit information to the Revised design.

-Both

Applies the file’s sub-circuit information to both the Golden and Revised designs.

-SEnsitive

The transistor description file is case-sensitive. This is the default.

-NOSEnsitive

The transistor description file is not case-sensitive.

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-LAstmod

If duplicate modules exist, Conformal uses the first module and ignores the later ones by default. Use this option to specify that Conformal use the last module and ignore earlier ones.

Examples read pattern DLTCH1.v -verilog -revised read pattern DLT2.v -verilog -both read pattern xtran.spi -spice -golden // Functional description of the transistor // pattern read library lib.v -verilog -golden // Transistor pattern description read pattern pattern.v -golden read design design.v -golden abstract logic -golden

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT PIN DIRECTION RESOLVE

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REDUCE MOS REDuce MOs [-ALL | -MODule ...] [-Golden | -Revised] [-MERGE_TRAN] [-SD_GND] [-SD_VDD] [-DIODE] [-PARALLEL] [-GATE_ON] [-GATE_OFF] [-NOVERbose] (Setup Mode)

Note: This is a Conformal Custom command. Performs varieties of reduction on MOS transistor(s) from the circuit.

Parameters -All

Reduces transistor logic from all modules. This is the default.

-MODule ... Specifies the module(s) to reduce transistor logic. -Golden

Reduces transistor logic from the Golden design. This is the default.

-Revised

Reduces transistor logic from the Revised design.

-MERGE_TRAN

Collapses the tran or rtran device into the wire.

-SD_GND

Removes MOS devices with source and drain on GND.

-SD_VDD

Remove MOS devices with the source and drain on VDD.

-DIODE

Collapses [PN]mos into the wire if the source is on [VDD|GND] and the gate and drain are on the same net.

-PARALLEL

Collapses parallel-connected MOS devices into one MOS.

-GATE_ON

Collapses non-weak MOS devices into the wire if the gate is a constant that causes current to flow.

-GATE_OFF

Removes non-weak MOS devices if the gate is a constant that does not cause the current to flow.

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-NOVERbose

Does not report detailed statistical information.

Related Commands ABSTRACT LOGIC READ DESIGN -spice

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REMODEL REMODEL <-SEQ_MERGE | -SEQ_CONSTant | -DFF_CONST_ASYNC | -UNFOLD_DFF | -BBOX_MERGE | -RED_DLAT | -GATED_CLOCK | -REVERSE_SEQ_REDundant | -SEQ2BUFfer | -SEQ_CONSTANT_GROUP | -UNREACH> <-UNMAPPED | -MAPPED | -ALL | gate_id ... | instance_pathname ...> [-MAX_UNMAP ] [-BOTH | -GOLden | -REVised] [-REPEAT] [-VERBose] (LEC Mode)

Used in LEC mode and after mapping, this takes a set of key points and attempts to remodel them. Use this command in conjunction with the SET FLATTEN MODEL command to resolve mis-compares due to key point issues. When you use this command, the Conformal software invalidates compare results (if they exist), closes schematics, and updates the Mapping Manager.

Parameters -SEQ_MERGE

Merges common groups of sequential elements into one sequential element in a logic cone of a key point. Note: This modeling can only be applied to unmapped DFFs or D-latches.

-SEQ_CONSTant

Converts a DFF or D-latch to a ONE or ZERO gate. Note: This modeling can only be applied to unmapped DFFs or D-latches.

-DFF_CONST_ASYNC

Converts a DFF to a ZERO or ONE gate due to its asynchronous set or reset condition. This can be applied to both unmapped or mapped DFFs.

-UNFOLD_DFF

Converts a DFF to 2 D-latches with a master/slave configuration. Note: For latch-based custom logic comparisons, this option might work better than set flatten model -latch_fold.

-BBOX_MERGE

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Performs automatic blackbox merging.

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-RED_DLAT

Collapses serial D-latches (even when there is logic between them) into the last latch on that clock phase. You cannot use this option with latches that have set or reset pins.

-GATED_CLOCK

Transforms the gated clock of DFF to a MUX feedback loop.

-REVERSE_SEQ_REDundant Restores the sequential redundancy to the outputs of the specified DFFs or DLATs. -SEQ2BUFfer

Remodels a DFF or DLAT to a buffer or inverter due to asynchronous connections.

-SEQ_CONSTANT_GROUP Validates and remodels a group of registers to ZERO and ONE gates, which are dependent upon each other. Note: You must specify a correct group of registers for this modeling to be effective; otherwise, any non-constant register in the group will prevent the true constant group from being recognized. -UNREACH

Determines if the specified mapped key points are functionally unreachable to primary outputs. After the key point is proved to be functionally unreachable, the fan-out nets from this key point are tied to constant zero. This analysis is useful to subsequently remove the functionally unreachable non-equivalent compared points from the compare and mapping lists. Note: This remodeling can only be performed on mapped key points and should be used after running the COMPARE command. Note: Use the DELETE MAPPED POINTS -unreach command to delete unreachable mapped points.

-UNMAPPED | -MAPPED | -ALL | gate_id | instance_pathname… Applies the specified remodeling to all unmapped key points, all mapped key points, all key points, or the specified gate or instance. By default, Conformal remodels all unmapped points. Note: -ALL only applies to the options: -gated_clock, -reverse_seq_redundant, -seq2buffer, and -seq_constant_group.

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-MAX_UNMAP Specifies an upper limit of unmapped keypoints to be remodeled. -BOTH

Applies the specified remodeling to the Golden and Revised designs. This is the default.

-GOLden

Applies the specified remodeling to the Golden design only.

-REVised

Applies the specified remodeling to the Revised design only.

-REPEAT

Repeats until no further modeling is possible. Except for sequential constant modeling, by default, the Conformal software attempts to remodel once. Note: Use Ctrl-C to interrupt remodeling.

-VERBose


Example remodel –seq_constant Q1_reg

Sample Implementation for the REMODEL Command: In the following example, the design can be mapped almost completely by name, but there are key points that have not been merged. To remodel replicated registers into a single register, use the REMODEL command. Then Conformal can remap key points and compare. … set flatten model -seq_merge set map method -name only set system mode lec remodel -seq_merge -both -unmapped set map method -name first map key points add compare points -all compare

Related Commands COMPARE DELETE MAPPED POINTS

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Encounter Conformal Equivalence Checking Reference Manual Command Reference MAP KEY POINTS SET FLATTEN MODEL

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REMOVE REMove [-Golden | -Revised] [-INSTance | -INS_Module] [-MODule | -ALL] (Setup Mode)

Removes instances from the database. Tip To report instances removed with this command, run the REPORT REMOVED INSTANCE command.

Parameters name* ...

Specifies the name(s) of the instance(s) to remove. This accepts wildcards.

-Golden

Removes instances from the Golden design. This is the default.

-Revised

Removes instances from the Revised design.

-INSTance

Indicates that the specifies the instance names. This specifies to remove all instances whose instance names match . This is the default.

-INS_Module

Indicates that the specifies the module names. This specifies to remove all instances whose module names match .

-MODule

specifies the module names. This accepts wildcards. This specifies to remove the specified instances from only the specified modules in . Note: If you do not specify , the REMOVE command removes the specified instances from only the root module. This is the default.

-ALL

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Removes the specified instances from all modules in the design.

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Example For these lines: module top (...); mod1 u01 (...); // mod2 u02 (...); // mod3 u03 (...); // endmodule module mod3 (...); mod1 u01 (...); // mod2 u02 (...); // endmodule ■

inst1 inst2 inst3

inst4 inst5

The following command removes u01 from the root module top: remove u01 -ALL

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The following command removes u01 from module mod3: remove u01 -MODULE mod3

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// remove inst4

The following command removes all mod1 instances from the root module top: remove mod1 -INS_Module

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// remove inst1, inst4

// remove inst1

The following command removes all mod1 instances from all modules: remove mod1 -INS_Module -ALL // remove inst1, inst4

Related Commands REPORT REMOVED INSTANCE

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REPORT ABSTRACT MODEL REPort ABSTract Model [-ALL | -MODule ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This is a Conformal Custom command. If you used SET ABSTRACT MODEL command to abstract transistor logic from particular modules, this reports their abstraction conditions.

Parameters -All

Reports abstraction conditions for all modules.

-MODule module_name… Reports abstraction conditions for the specified modules. -Both

Reports abstraction conditions for both the Golden and Revised designs. This is the default.

-Golden

Reports abstraction conditions for the Golden design.

-Revised

Reports abstraction conditions for the Revised design.

Related Commands ABSTRACT LOGIC RESET ABSTRACT MODEL SET ABSTRACT MODEL

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REPORT ALIAS REPort ALias [name*]… (Setup / LEC Mode)

Displays a list of all or specified aliases you created with the ADD ALIAS command. Wildcard: The wildcard (*) represents any zero or more characters in alias names.

Parameters name*…

Reports the specified alias.

Related Commands ADD ALIAS DELETE ALIAS

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REPORT BLACK BOX REPort BLack Box [-Module |-Instance] [-DETail] [-Class ] [-HIER | -NOHIER] [-HIDden | -NOHIDden] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays blackboxes from the Golden and Revised designs. The blackboxes either already existed in the design, or you previously added them with the ADD BLACK BOX command.

Parameters -Module

Reports only the blackbox modules. This is the default.

-Instance

Reports only the blackbox instances.

-DEtail

Displays details about blackboxes, where:

-Class

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USER—Indicates that the blackbox was added by the ADD BLACK BOX command.

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SYSTEM (undefined)—Indicates that the blackbox was added by the SET UNDEFINED CELL blackbox command.

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SYSTEM (unsupported)—Indicates that the module contains unsupported statements.

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SYSTEM (empty)—Indicates that the module contains no logic.

■

SYSTEM (notranslate)—Indicates that the blackbox was added by the ADD NOTRANSLATE MODULES command.

Displays the specified class of blackboxes. Full

Blackboxes from both the User and System classes. This is the default.

User

Blackboxes previously added with the ADD BLACK BOX command.

System

Blackboxes included in the original design.

UNDefined

Blackboxes for undefined modules.

UNSupported

Blackboxes for unsupported modules.

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EMPty

Blackboxes for empty modules.

NOTranslate

Blackboxes for notranslate modules.

-HIER

Displays the hierarchical blackboxes. This is the default.

-NOHIER

Does not display the hierarchical blackboxes.

-HIDden

Displays all blackbox instances in the design hierarchy including those contained within other blackboxes. This is the default.

-NOHIDden

Does not display blackbox instances that are contained within other blackboxes.

-Both

Displays blackboxes from both the Golden and Revised designs. This is the default.

-Golden

Displays blackboxes from the Golden design.

-Revised

Displays blackboxes from the Revised design.

Related Commands ADD BLACK BOX DELETE BLACK BOX

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REPORT CLOCK REPort CLock [-Both | -Golden | -Revised] (Setup / LEC Mode)

Reports all clocks from the Golden and Revised designs that were added with the ADD CLOCK command.

Parameters -Both

Displays all added clocks from both the Golden and Revised designs. This is the default.

-Golden

Displays all added clocks from the Golden design.

-Revised

Displays all added clocks from the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION

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Encounter Conformal Equivalence Checking Reference Manual Command Reference RESOLVE

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REPORT COMMAND PROFILE REPort COmmand PRofile [-Summary | -Detail] (Setup / LEC Mode)

Displays a profile of all of the commands you executed after you used SET COMMAND PROFILE with the -on option. (The default setting for SET COMMAND PROFILE is -off.) The profile report includes the order in which commands were executed and the memory use. The profile includes commands that were executed in the GUI mode.

Parameters -SUMmary

Lists a summary table of all of the commands in alphabetical order. This is the default.

-Detail

Lists all commands in order of execution.

Related Commands SET COMMAND PROFILE SET LOG FILE

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REPORT COMPARE DATA REPort COmpare Data [-CLASS …] [-Type …] [-Verbose | -SUMmary] | [-INSTance_eq |-OUTput_eq | -PIN_eq ] [-Golden |-REvised] [-noreport_bbox_input | -report_bbox_input] (LEC Mode)

Displays a list of all or specified compared points. If no options are specified, Conformal identifies all equivalent and nonequivalent compared points and displays a summary. The compared points are listed in pairs of rows with three fields in each row. The first row in each pair represents the Golden design. The second row in each pair represents the Revised design. The three fields in each row are: ■

First–the gate identification number

■

Second–the gate type

■

Third–the instance path or pin path

Parameters -CLASS class_type… Displays the specified class of compared points: EQuivalent INVequivalent Inverted-equivalent points NONEQuivalent Nonequivalent points

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ABort

Aborted points

NOTcompared

All points not compared

SYStem

Automatically mapped points

USEr

User-mapped points 281

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FULL

Both automatically-mapped and user-mapped points

INSTance_eq

Equivalent instances

OUTput_eq

Equivalent outputs

PIN_eq

Equivalent pins

-TYPE compared_points_type… Displays the specified type of compared points: PO

Primary output

DFF

D flip-flop

DLAT

D-latch

BBOX

Blackbox

CUT

Compared points with artificial gates to break combinational loops

-Verbose

Displays all compared points. This is the default.

-SUMmary

Lists a summary report of the compared points.

identifier

Lists compared points for the specified gate ID or path. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

-INSTance_eq Displays compare data for a pair of instances previously identified with the ADD INSTANCE EQUIVALENCE command. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -OUTput_eq Displays compare data for a pair of outputs previously identified with the ADD OUTPUT EQUIVALENCES command. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -PIN_eq May 2008

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Display compare data for a pair of pins previously identified with the ADD PIN EQUIVALENCE command. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Golden

The specified identifiers are from the Golden design. This is the default.

-REvised

The specified identifiers are from the Revised design.

-noreport_bbox_input Does not report the blackbox input pins in the compare report results. This is the default. -report_bbox_input

Report the blackbox input pins in the compare report results (Equivalent, Non-equivalent, Abort, and Not-compared).


Related Commands COMPARE DIAGNOSE PROVE REPORT STATISTICS REPORT COMPARE TIME

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REPORT COMPARE TIME REPort COmpare TIME [-SORT] [-MAX n] [-RTLINFO] [-ABORT_ONLY] [-GOLD g] [-REVI r] [-ENABLE] [-DISABLE] (LEC Mode)

Reports the CPU time consumed during a comparison. You must enable this feature before starting a comparison; otherwise, Conformal does not record any information. For example: compare report compare time -enable compare report compare time

In this example, Conformal records the CPU time for the second comparison only. Note: Conformal does not record compare time for trivial cones.

Parameters -SORT

Sorts the information based on the recorded CPU time.

-MAX n

Specifies the maximum number, denoted by n, of key points to report.

-RTLINFO

Reports RTL information inside the cone.

-ABORT_ONLY

Report only the abort points.

-GOLD g and -REVI r Specifies particular key points to report. If you do not specify these options, Conformal reports all key points. -ENABLE

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-DISABLE

Disables the recording of CPU time.

Examples The following demonstrates how to use this command with other commands. Note: Use these steps after you read in your library and design files. 1. Add your compare points. LEC > add compared points -all // 3113 compared points added to compare list

2. Enable the report compare time feature. LEC> report compare time -enable

3. Start your comparison. LEC> compare ================================================================================ Compared points PO DFF DLAT BBOX Total -------------------------------------------------------------------------------Equivalent 123 2983 2 5 3113 ================================================================================ // Warning: 1 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison

4. Report the compare time. In this example, Conformal sorts the information based on CPU time and only reports RTL information within the cone. LEC>report compare time -sort -rtlinfo CPU Time Used: 5.29, Result: Equivalent: (G) + 536 DFF /cpu_core/CPU/cpu_dp/alu/v_alo_1l_reg[30] (R) + 1284 DFF /cpu_core$CPU$cpu_dp$alu$v_alo_1l_reg_30_/U$1/U$1 RTL modules at Golden: RTL modules at Revised: CPU (G) (R) RTL RTL

Time Used: 4.64, Result: Equivalent: + 533 DFF /cpu_core/CPU/cpu_dp/alu/o_alvo_1l_reg + 1364 DFF /cpu_core$CPU$cpu_dp$alu$o_alvo_1l_reg/U$1/U$1 modules at Golden: modules at Revised: . . .

Related Commands ADD COMPARED POINTS COMPARE

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT COMPARE DATA

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REPORT COMPARED POINTS REPort COmpared Points [-SUMmary | -PO | -DFf | -DLat | -Bbox | -Cut] (LEC Mode)

Displays the compared points that were added with the ADD COMPARED POINTS command. Refer to the sample report shown below. The first row represents the Golden design; the second row represents the Revised design. It also shows a tabulated summary of the compared points for each design. This report includes the total number of compared points for primary outputs, D flip-flops, D-latches, blackboxes, and cut gates. If you do not specify any options, Conformal lists all added compared points, and a tabulated summary appears at the end of the list. However, if you use the -summary option, Conformal displays only the tabulated summary.

Parameters -SUMmary

Lists a summary table of all of the added compared points in the Golden and Revised designs. (Refer to the sample report given below.) This is the default.

-PO

Lists all primary output compared points.

-DFf

Lists all D flip-flop compared points.

-DLat

Lists all D-latch compared points.

-Bbox

Lists all blackbox compared points.

-Cut

Lists all compared points for artificial gates that break combinational loops.

Related Commands ADD COMPARED POINTS COMPARE DELETE COMPARED POINTS REPORT STATISTICS

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REPORT CPF LOGIC REPort CPf Logic [-ISOlation] [-Level_shifter] [-RETention] [-Verbose] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power cells that were inserted by the Conformal Low Power software.

Parameters -ISOlation

Reports the inserted isolation cells only .

-Level_shifter

Reports the inserted level-shifter cells only .

-RETention

Reports the inserted state retention cells only .

-VERbose

Reports detailed information of each defined CPF cell, including cell types and rules that triggered this cell to be inserted in the design.

Note: By default, this command reports all inserted low power cell types.

Example The following commands read the lib.cpf and design.cpf files, performs low power cell insertion, and reports only the interted isolation and level-shifter cells: read cpf lib.cpf design.cpf commit cpf -insert report cpf logic -isolation -level_shifter

Related Commands COMMIT CPF READ CPF

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REPORT CUT POINT REPort CUt Point [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all cut points from the Golden and Revised designs that were added with the ADD CUT POINT command.

Parameters -Both

Lists all cut points in both the Golden and Revised designs. This is the default.

-Golden

Lists all cut points in the Golden design.

-Revised

Lists all cut points in the Revised design.

Related Commands ADD CUT POINT DELETE CUT POINT REPORT PATH

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REPORT DATAPATH OPTION REPort DAtapath Option (Setup / LEC Mode)

Displays current data path option settings.

Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION SET FLATTEN MODEL

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REPORT DATAPATH RESOURCE REPort DATapath REsource [-Verbose] [-Analyzed] [-Type ] (LEC Mode)

Displays information about data path resources from the Golden and Revised designs.

Parameters -Verbose

Provides additional information, such as filename and line number.

-Analyzed

Provides information only for resources analyzed by ANALYZE DATAPATH command.

-Type

Provides information only for resources of the specified type. Choose one of the following: ■

MULT — multipliers

■

ADD — adders

■

SUB — subtractors

■

MERGED — merged operators

Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT DESIGN DATA

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REPORT DESIGN DATA REPort DEsign Data [module_name] [-Summary | -Verbose] [-NOKey_point | -Key_point] [-Extra ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays design data on the Golden and Revised designs. It displays the number of design modules, library cells, inputs, outputs, primitives, and one-to-one mapped state points. This report includes word-level information about the design in terms of the number of arithmetic/keyword operations. This report includes data path elements such as WMUX, WAND, WXOR and other word-level representations of Boolean logic. It displays simpler representations of data path logic that may need to be separated out for the comparison process. Use Control-C to interrupt the key point listing if you find that the report is too long.


Reports design data for the named module. By default, the Conformal software reports design data on the top root design module.

-Summary

Summarizes the design data for the total number of the following: ■

Design modules

■

Library cells

■

Inputs

■

Outputs

■

Primitives

This is the default.

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-Verbose

Reports a detailed list of the design’s total number of: ■

Design modules

■

Each different library cell

■

Inputs

■

Outputs

■

Each different primitive

-NOKey_point

Does not report the total one-to-one mapped state points. This is the default.

-Key_point

Reports the total one-to-one mapped state points. Note: If you use the -verbose option in conjunction with this option, Conformal reports all one-to-one mapped state points. Otherwise, Conformal reports the total in summary.

-Extra

Reports the extra input, output, or I/O pins for pair-able modules between the Golden and Revised designs. INPut

Specifies input pins.

Output

Specifies output pins.

INOut

Specifies inout pins.

-Both

Report design data on both the Golden and Revised designs. This is the default.

-Golden

Report design data on the Golden design.

-Revised

Report design data on the Revised design.

Report Design Data Figure 2-1 is an example of the default design data report.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Figure 2-1 Design Data Report

Related Commands READ DESIGN READ LIBRARY REPORT DATAPATH RESOURCE

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REPORT DESIGN SIMILARITY REPort DEsign SIMilarity [-INStance ] [-GOLDen | -REVised] (LEC Mode)

Displays the similarity degree of a design with reference to the other netlist. The similarity is measured by the number of corresponding points in the two designs. The value of similarity ranges from 0% to 100%. If the two designs are identical in structure, the similarity degree is 100%.

Parameters -INStance Displays the similarity degree of the netlist inside the specified instance. The similarity is evaluated with reference to the other netlist. If no instance is specified, the similarity is for the entire design. -Golden

Specifies that the similarity evaluation is performed on the Golden design. The Revised netlist is used for reference. This is the default.

-Revised

Specifies that the similarity evaluation is performed on the Revised design. The Golden netlist is used for reference.

Examples ■

The following command displays the similarity of the Golden design’s netlist. The Revised design’s netlist is used for reference. report design similarity

■

The following command displays the similarities of the instances whose name begins with mult in the Golden design’s netlist: report design similarity -instance mult*

Related Topic Reporting Design Similarities

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REPORT DYNAMIC CONSTRAINTS REPort DYnamic Constraints [-Both | -Golden | -Revised] (LEC Mode)

Displays all of the dynamic constraints you added to the Golden and Revised designs with the ADD DYNAMIC CONSTRAINTS command.

Parameters -Both

Lists all dynamic constraints in both the Golden and Revised designs. This is the default.

-Golden

Lists all dynamic constraints in the Golden design.

-Revised

Lists all dynamic constraints in the Revised design.


Related Commands ADD DYNAMIC CONSTRAINTS COMPARE DELETE DYNAMIC CONSTRAINTS PROVE

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REPORT ECO CELL REPort ECo Cell [-FReedcell] [-SParecell] (Setup Mode)

Reports the spare cells or freed cells available for the MAP ECO PATCH command.

Parameters -FReedcell

Reports only the freed cells.

-SParecell

Reports only the spare cells.

Related Commands ADD ECO CELL MAP ECO PATCH

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REPORT ECO CHANGES REPort ECo Changes [-MODule ] [-SUMmary] (Setup Mode)

Reports the ECO changes. To report the ECO change with this command, the ECOs must have been applied with the APPLY PATCH or OPTIMIZE DESIGN command.

Parameters -MODule Specifies the module to report. By default, the command reports all nets and instances that have been added and deleted. -SUMmary

Shows a summary only.

Related Commands WRITE ECO DESIGN

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REPORT ECO PATCH REPort ECo PAtch (Setup Mode)

Reports the ECO patch specified by the ADD ECO PATCH command.

Related Commands ADD ECO PATCH DELETE ECO PATCH

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REPORT ENVIRONMENT REPort ENvironment [-Setup | -MOdeling | -MApping | -COMpare | -Diagnosis | -FUnctiondefault] (Setup / LEC Mode)

Displays global settings for the Golden and Revised designs and system settings.

Parameters -Setup

Reports environment related to Setup. This is the default.

-MOdeling

Reports environment related to Modeling.

-MApping

Reports environment related to Mapping.

-COMpare

Reports environment related to Compare.

-Diagnosis

Reports environment related to Diagnosis.

-FUnctiondefault

Reports environment related to the default return value.

Environment Report Figure 2-2 is an example of the default environment report (no options were added).

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Figure 2-2 Environment Report

Related Commands SET CASE SENSITIVITY SET COMPARE EFFORT SET CPU LIMIT SET FLATTEN MODEL May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference SET GATE REPORT SET IMPLEMENTATION SET LOG FILE SET MAPPING METHOD SET NAMING RULE SET ROOT MODULE SET SCREEN DISPLAY SET SYSTEM MODE SET UNDEFINED CELL SET UNDRIVEN SIGNAL SET WIRE RESOLUTION SET X CONVERSION

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REPORT FLOATING SIGNALS REPort FLoating Signals [-ROot | -Module | -All] [-UNDriven | -UNUsed] [ |-Net | -Pin] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all floating signals in the Golden and Revised designs or in specified modules of a design. The reported floating signals are either nets or pins and are either undriven or unused. Use the SET UNDRIVEN SIGNAL command to specify the global behavior of the undriven floating signals in the Golden and Revised designs.

Parameters -ROot

Displays all of the floating signals in the root module. This is the default.

-Module name

Displays “all” the floating signals in the specified module within the given defaults.

-All

Displays “all” the floating signals in “all” design modules within the given defaults.

-UNDriven

Displays only undriven floating signals. This is the default.

-UNUsed

Displays only unused floating signals.

-Net

Displays only floating nets. If you do not specify -net or -pin, Conformal displays both floating nets and floating pins.

-Pin

Displays only floating pins. If you do not specify -net or -pin, Conformal displays both floating nets and floating pins.

-Both

Displays floating signals from both the Golden and Revised designs. This is the default.

-Golden

Displays floating signals from the Golden design.

-Revised

Displays floating signals from the Revised design.

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Related Commands ADD TIED SIGNALS SET UNDRIVEN SIGNAL

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REPORT GATE REPort GAte [ [-INStance | -Pin | -Net | -ID] [-Golden | -Revised] [-SUPport] [-FRONTIER] [-FANIn ] [-FANOut ] [-UNReach] [-SHORT_list | -NOSHORT_list] [-SOURCE] [-Collapse] [-NODYNamic | -DYNamic] [-INDent ]] [-Type ] [-RETention] [-CORRespondence] [-SUMmary] (Setup / LEC Mode)

Displays flattened gate information. By default, it reports the gate ID, type, name, and its fanins and fan-outs at the primitive level. After you specify options for the initial report, use the REPORT GATE command without options to generate a report on the same gates, or specify new options as needed. Important ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

Parameters identifier

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If you do not specify one of the following options, Conformal automatically determines if the identifier is a number or a path. In the case of a number, Conformal uses the -id option; otherwise, Conformal searches for the gate with the -instance, -pin, or -net option; in this respective order. -INStance

Instance path This is the default.

-Pin

Pin path

-Net

Net path

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Gate identification number

-ID

The identification number is an integer assigned automatically by Conformal. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Golden

The identifier is in the Golden design. This is the default.

-Revised

The identifier is in the Revised design.

-SUPport

Reports the supported key points from the fanin cone.

-FRONTIER

Reports the frontier key points from the fan-out cone.

-FANIn integer

Reports this number of levels in the fanin cone. The default value is 0.

-FANOut integer

Reports this number of levels in the fan-out cone. The default value is 0.

-UNReach

Displays diagnosis information for unmapped points that were classified as unreachable.

-SHORT_list

Lists the first and last 20 gates of a long display list. This is the default.

-NOSHORT_list

Displays the entire display list.

-SOURCE

Reports the gate information and the following location information: ■

Module name

■

Instance name

■

Filename

■

Source line

-Collapse

Does not report inverters and buffers in the fanin cone. The default is to report all inverters and buffers in the fanin/fan-out cone.

-NODYNamic

Use this option in conjunction with the -fanin option. The fanin cone does not stop at a gate with dynamic constraints. This is the default.

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-DYNamic

Use this option in conjunction with the -fanin option. The fanin cone stops at the gate with dynamic constraints.

-INDent integer

Displays this amount of whitespace when reporting the fanin and fan-out cones. The default value is 2.

-Type gate_type

Reports all gates with the specified gate type. The available gate types are as follows:

-RETention

PI

Primary inputs

0

TIE-0 gates

1

TIE-1 gates

E

TIE-E gates

Z

TIE-Z gates

BBOX

Blackboxes

DFF

D flip-flops

DLAT

D-latches

CUT


OUT

Artificial gates for the multiple outputs of blackboxes

COMB

Combinational gates

PO

Primary Outputs

Note: This is a Conformal Low Power option. If the gate is a sequential element (DFF or DLAT) and belongs to the Golden Design, this option reports the tag-name (if any) associated with the DFF or DLAT. If the gate is a sequential element (DFF or DLAT) and belongs to the Revised Design, this option reports the power gating cell attribute (if any) associated with the DFF or DLAT. For non-sequential elements, nothing is reported.

-CORRespondence

Reports the correspondence gates in the other (Golden or Revised design) netlist. The correspondence gate is potentially equivalent with the gate specified in this command. Use the PROVE command to formally prove the equivalence.

-SUMmary

Reports gate type statistics. The default is not to report the statistics.

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Related Commands BACKWARD CHANGE GATE TYPE FORWARD REPORT PATH SET GATE REPORT

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REPORT HIER_COMPARE RESULT REPort HIer_compare Result [-Summary | -Equivalent | -NONEQuivalent | -Abort | -UNcompared | -FLattened | -DYNamicflattened | -EXTRA_po | -ALL] [-USage] (Setup / LEC Mode)

Displays the results of the hierarchical comparison. If the WRITE HIER_COMPARE DOFILE command is used, this command is automatically placed at the end of the hierarchical dofile script. It lists the summary results and any modules that are nonequivalent, aborted, or uncompared.

Parameters -Summary

Displays a summary table of the hierarchical comparison results. This is the default.

-Equivalent

Displays only the hierarchical modules that are equivalent.

-NONEQuivalent

Displays only the hierarchical modules that are nonequivalent.

-Abort

Displays only the hierarchical modules that had abort key points.

-UNcompared

Displays only the hierarchical modules that are not compared.

-FLattened

Displays only the hierarchical modules that were found to be nonequivalent and, as a result, were flattened. Use this option when you have used write hier_compare dofile -conditional

-DYNamicflattened

Displays only the hierarchical modules that were either found to be non-equivalent, or were equivalent but caused non-equivalence at the parent level, and were automatically flattened. Use this option when performing hierarchical comparison with the RUN HIER_COMPARE command.

-EXTRA_po

Displays only the hierarchical modules that have extra (not-mapped) primary outputs.

-ALL

Displays the results of all of the modules.

-USage

Displays the CPU use time for each module comparison.

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Related Commands RESET HIER_COMPARE RESULT RUN HIER_COMPARE SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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REPORT IGNORED INPUTS REPort IGnored Inputs [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the input pins, which were added as ignored inputs, in the Golden and Revised designs. These pins were originally specified with the ADD IGNORED INPUTS command.

Parameters -ROot

Displays only the input pins in the root module. This is the default.

-Module name

Displays only the ignored input pins in the named module.

-All

Displays “all” ignored input pins in all modules. “All” applies within the given defaults.

-Both

Displays both the Golden and Revised added ignored inputs. This is the default.

-Golden

Displays the added ignored inputs from the Golden design.

-REvised

Displays the Revised ignored inputs.

Related Commands ADD IGNORED INPUTS DELETE IGNORED INPUTS

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REPORT IGNORED OUTPUTS REPort IGnored Outputs [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the output or I/O pins, which were added as ignored outputs, in the Golden and Revised designs. These outputs were originally specified with the ADD IGNORED OUTPUTS command.

Parameters -ROot

Displays only the input pins in the root module. This is the default.

-Module name

Displays only the ignored output or I/O pins in the specified module.

-All

Displays “all” ignored input pins in all modules. “All” applies within the given defaults.

-Both

Displays both the Golden and Revised added ignored outputs. This is the default.

-Golden

Displays only the Golden added ignored outputs.

-REvised

Displays only the Revised ignored outputs.

Related Commands ADD IGNORED OUTPUTS DELETE IGNORED OUTPUTS

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REPORT INSTANCE ATTRIBUTE REPort INstance Attribute [-ROot | -Module | -All] [-Summary | -Verbose] [-Both | -Golden | -REvised] (Setup Mode)

Displays the attributes placed on instances in the Golden and Revised designs. These attributes were originally specified with the ADD INSTANCE ATTRIBUTE command.

Parameters -ROot

Displays only the added instance attributes in the root module. This is the default.

-Module name

Displays only the added instance attributes in the specified module.

-All

Displays “all” added instance attributes within the given defaults.

-Summary

Displays a summary message of the total number of added instance attributes. This is the default.

-Verbose

Displays all added instance attributes.

-Both

Displays the added instance attributes in both the Golden and Revised designs. This is the default.

-Golden

Displays the added instance attributes in the Golden design.

-REvised

Displays the added instance attributes in the Revised design.

Related Commands ADD INSTANCE ATTRIBUTE DELETE INSTANCE ATTRIBUTE

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REPORT INSTANCE CONSTRAINTS REPort INstance Constraints [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the constraints placed on instances in the Golden and Revised designs. These constraints were originally specified with the ADD INSTANCE CONSTRAINTS command.

Parameters -Both

Displays the instance constraints in both the Golden and Revised designs. This is the default.

-Golden

Displays the instance constraints in the Golden design.

-Revised

Displays the instance constraints in the Revised design.

Related Commands ADD INSTANCE CONSTRAINTS DELETE INSTANCE CONSTRAINTS

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REPORT INSTANCE EQUIVALENCES REPort INstance Equivalences [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the equivalences placed on instances in the Golden and Revised designs. These equivalences were originally specified with the ADD INSTANCE EQUIVALENCES command.

Parameters -Both

Displays the instance equivalences in both the Golden and Revised designs. This is the default.

-Golden

Displays the instance equivalences in the Golden design.

-Revised

Displays the instance equivalences in the Revised design.

Related Commands ADD INSTANCE EQUIVALENCES DELETE INSTANCE EQUIVALENCES

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REPORT KEY POINT REPort KEy Point [[-TYpe ... | -NOTYpe ...] | -Mapped | -UNMapped | -UNReached] [-PROPerty] [-DC] [-Golden | -REVised] (Setup / LEC Mode)

Report key points in the design.

Parameters -TYpe

Displays all key points with the specified type.

-NOTYpe

Displays all key points except the specified type. The available types are as follows: PI

Primary inputs

E

TIE-E gates

Z

TIE-Z gates

DFf

D flip-flops

DLat

D-latches

CUt


BBox

Blackboxes

PO

Primary Outputs

-Mapped

Displays all mapped key points in the design.

-UNMapped

Displays all unmapped key points in the design.

-UNReached

Displays diagnosis information for unmapped key points that were classified as unreachable.

-PROPerty

Displays support and fan-out key points for each key point

-DC

Displays the number of DC gates in the compare cone

-Golden

Specifies that the report applies only to the Golden design. This is the default.

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-Revised

Specifies that the report applies only to the Revised design.

Related Commands MAP KEY POINTS

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REPORT LIBRARY DATA REPort LIbrary Data [-Source] [-SORT ] [-SKIP_Unref] [-Golden | -Revised] (Setup / LEC Mode)

Displays the following columns: ■

ID—Specifies the cell ID.

■

Name—Specifies the cell name.

■

Cost—Specifies the cost of each library cell, which is the product of the number of instances of primitive gates within each library cell (Ins) and the number of times the library cell is instantiated (Ref).

■

Ins—Displays the number of instances of primitive gates within each library cell.

■

Ref—Displays the number of times the library cell is referenced in the design.

■

TOT—Displays the total number of gates per library cell. This total is calculated by Ins times Ref. If Ins is 3 and Ref is 3, the total is 9. If Ins is 3 and Ref is 0, the total is 0.

■

DFF—Specifies whether the cell contains a D flip-flop.

■

DLAT—Specifies whether the cell contains a D-latch.

■

BUF—Specifies whether the cell contains a buffer.

■

NOT—Specifies whether the cell contains an inverter gate.

■

BBOX—Specifies whether the cell contains a blackbox.

■

UDP—Specifies whether the cell is a UDP.

By default, Conformal reports on the library for the Golden design if you do not specify options. Note: When you read in a library, you can specify whether it is for the Golden or Revised design.

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Parameters -SOURCE

Displays the source filename and line number for each cell.

-SORT

Sorts report data as specified: NAME

Sorts report data alphabetically by library cell name.

REFerence

Sorts report data according to the Reference column, in descending order.

INStance

Sorts report data according to the Instance column in descending order.

-SKIP_Unref

Does not display unreferenced library modules.

-Golden

Displays the library data for the Golden design. This is the default.

-Revised

Displays the library data for the Revised design.

Related Commands READ LIBRARY READ DESIGN REPORT DESIGN DATA

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REPORT LOWPOWER CELLS REPort LOwpower Cells [-Module | -Instance] [-Summary] (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power cells used in the design.

Parameters -Module

Reports only the modules with low power cells. This is the default.

-Instance

Reports only the instances with low power cells.

-Summary

Displays a summary of low power cells.

Related Commands ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER DATA SET LOWPOWER OPTION

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REPORT LOWPOWER DATA REPort LOwpower Data [-STatus ] [-TYpe [All | Retention_cell_check [ -Rule ] | Isolation_cell_check | Level_shifter_cell_check | POWER_domain_check] ] [-SUMmary | -Verbose] (LEC Mode)

Note: This is a Conformal Low Power command. Reports the low power data. These are the results of the low power check performed on low power cells using the CHECK LOWPOWER CELLS command. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 143.

Parameters -STatus

Specifies the status reporting. For retention-register cell types, the -STatus arguments are described as follows: -All

Reports all the sequential pairs (LEC mapped points) that passed or failed the default rule or user rule. This is the default.

-Pass

Reports all the sequential pairs that passed the default rule or user rule.

-Fail

Reports all the sequential pairs that failed the default rule or user rule.

Notcheck Reports the sequential pairs that were not checked for retention-register consistency For isolation and level-shifter cell types, the -STatus arguments are described as follows: -All

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Reports all the low power cut gates that passed or failed the technology mapping check. This is the default.

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-Pass

Reports all the low power cut gates that passed the technology mapping check.

-Fail

Reports all the low power cut gates that failed the technology mapping check.

Notcheck Reports the low power cut gates that were not checked for isolation and level-shifter consistency. For the power domain consistency check, the -STatus arguments are described as follows: All

Reports all the mapped sequential points that passed and failed the power domain consistency check

Pass

Reports the mapped sequential points that passed the power domain consistency check.

Fail

Reports the mapped sequential points that failed the power domain consistency check.

Notcheck Reports the mapped sequential points that were not checked for power domain consistency -TYpe

Specifies the module type reporting. -All

Reports on all low power cells. This is the default.

-Retention [-Rule ] Reports on only the low power state retention cells. -Rule reports all the sequential pairs that passed or failed the specified rulename. -Isolation_cells Reports on only the low power isolation cells. -Level_shifter_cells Reports on only the low power level-shifter cells. -POWER_domain_check Reports the results of power domain consistency check for the mapped sequential points.

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-SUMmary

Displays the status summary of the check performed on low power cells. This is the default.

-Verbose

For state retention cells, this reports the sequential pairs (LEC mapped points) that passed or failed the default rule or user rule. For each passed or failed sequential pair, the corresponding rule it passed or failed on is also reported. In addition, this reports any tag-name for the sequential element in the Golden Design, and any power gating cell attribute for the sequential element in the Revised Design. For isolation cells and level-shifter cells, this reports the PASS or FAIL status of low power cut gates that correspond to the isolation cells and level-shifter cells.

Related Commands ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER CELLS SET LOWPOWER OPTION

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REPORT MAPPED POINTS REPort MApped Points [< gate_id |instance_pathname* | pin_pathname*>… | [ -TYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>… | [ -NOTYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>…] [-INVert_mapped] | -SUMmary] [-LOng] [-CLass ] [-INput] [-OUTput] [-GRoup] [-REName] [-Golden | -REVised] [-RETention] [-METHOD] [-RENAME] [-UNReachable] (LEC Mode)

Displays the mapped points that were automatically identified or added with the ADD MAPPED POINTS command. Each mapped point from the Golden and Revised design is displayed along with a summary of all Golden and Revised mapped points. The summary includes the total number of primary inputs, primary outputs, D flip-flops, D-latches, TIE-Es, TIE-Zs, blackboxes, and cut gates. If no options are entered, the command default is to display both the User and System classes of mapped points. Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths of mapped points.

Parameters gate_id…

Reports the mapped points for the identified gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

instance_pathname*

Reports the mapped points for the named instance path(s). The wildcard (*) is supported.

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pin_pathname*

Reports the mapped points for the named pin path(s). The wildcard (*) is supported.

-Type mapped_point_type Displays all mapped points with the specified type. The available types are as follows: PI

Primary Inputs

E

TIE-E mapped points

Z

TIE-Z mapped points

DFF

D flip-flops

DLAT

D-latches

CUT


BBOX

Blackboxes

PO

Primary Outputs

-NOType mapped point_type Does not display mapped points with the specified type. The available types are as follows: PI

Primary Inputs

E

TIE-E mapped points

Z

TIE-Z mapped points

DFF

D flip-flops

DLAT

D-latches

CUT


BBOX

Blackboxes

PO

Primary Outputs

-INVert_mapped

Displays all mapped points with inverted mapping.

-SUMmary

Displays a table summary of the mapped points in the Golden and Revised designs.

-LOng

Displays pairs of mapped points on separate lines.

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-INput

Displays the input port mapping pairs of the specified DFF, DLAT, or blackbox gate.

-Class

Displays the following class of mapped points. Full

Mapped points from both the User and System classes. This is the default.

System

Mapped points from the original design.

User

Mapped points added with the ADD MAPPED POINTS command

-OUTput

Displays the output port mapping pairs of the specified blackbox gate.

-GRoup

Displays the mapping pairs in which either the Golden or Revised key point is a group of equivalent gates rather than a single gate. The group can be defined with the ADD INSTANCE EQUIVALENCE command or the -seq_merge option of the SET FLATTEN MODEL command. A key point group is counted as one key point.

-REName

Lists the keypoint with renaming rules applied to the names.

-Golden

The mapped points are from the Golden design. This is the default.

-REVised

The mapped points are from the Revised design.

-RETention

Note: This is a Conformal Low Power option. If the mapped point is a sequential pair (DFF or DLAT pair), this option reports the status of the mapped point (Pass, Fail, or Unknown) in accordance with the state retention mapping rules. This also reports the tag-name (if any) associated with the Golden DFF or DLAT and the power gating cell attribute (if any) associated with the Revised DFF or DLAT. For non-sequential elements, nothing is reported.

-METHOD

Shows the method used in mapping the keypoints.

-RENAME

Displays the keypoints with renaming rules applied to their names.

-UNReachable

Lists unreachable keypoints. Unreachable key points are those that do not eventually affect the primary output of the design.

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Related Commands ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT STATISTICS REPORT UNMAPPED POINTS SET MAPPING METHOD SET NAMING RULE

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REPORT MESSAGES REPort MEssages [-MOdeling | -MAPping | -Compare] [-RUle ] [-Summary | -Verbose] [-NOSORT | -SORT] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays either a summary or complete list of the warning messages that come from the modeling, mapping, or comparison process. (The modeling process occurs when Conformal exits the Setup mode.) A summary of the warning messages is always displayed when the modeling, mapping, or comparison process is in progress; however, this command displays each individual warning message for the Golden and Revised designs, according to your specifications. See “Modeling Messages” in the Encounter Conformal Equivalence Checking User Guide for information on the Modeling Messages and the commands/options that trigger them.

Parameters -MOdeling

Displays only warning messages from the processing and modeling of the Golden and Revised designs. This is the default.

-MAPping

Displays warning messages only from the automatic key point mapping process.

-Compare

Displays warning messages only from the comparison process.

-RUle rule_name

Displays only the named rule.

-Summary

Displays only a summary message for common warning messages. This is the default.

-Verbose

Displays all warning messages.

-NOSORT

Does not sort messages. This is the default.

-SORT

Sorts messages alpha-numerically. (Use this option with the -verbose option.)

-Both

Displays warning messages that come from both the Golden and Revised designs and libraries. This is the default.

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-Golden

Displays warning messages that come from the Golden design and library.

-REvised

Displays warning messages that come from the Revised design and library.

Related Commands READ DESIGN READ LIBRARY SET FLATTEN MODEL

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REPORT MODULE ATTRIBUTE REPort MOdule Attribute [-ALL | -PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit] [-Both | -Golden | -Revised] (Setup Mode)

Displays the module attributes in the Golden and Revised designs. These attributes were originally added with the ADD MODULE ATTRIBUTE command.

Parameters -ALL

Displays “all” added module attributes within the given defaults.

-PIPELINE_Retime

Displays only the modules added for pipeline-retiming.

-COMPARE_Effort

Displays only the modules that have specified compare effort levels.

-CPU_Limit

Displays the modules with a specified CPU time limit.

-Both

Displays the module attributes for both the Golden and Revised designs. This is the default.

-Golden

Displays the module attributes for the Golden design.

-Revised

Displays the module attributes for the Revised design.

Related Commands ADD MODULE ATTRIBUTE DELETE MODULE ATTRIBUTE READ DESIGN READ LIBRARY WRITE HIER_COMPARE DOFILE

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REPORT MODULES REPort MOdules [-ROot | module_name [-Up | -Down] | -All | -Top] [-Source] [-INSTantiation] [-USer] [-VHDLname] [-LEVEL ] [-Library] [-NOINTERLeave |-INTERLeave] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays module information for the Golden and Revised designs. If you specify a module, Conformal displays additional information on modules and library cells up or down the hierarchy of the given module name.

Parameters -ROot

Displays the name of the root module.

module_name

Reports module information on the specified module. An additional option lets you report on modules and library cells either up or down the hierarchy of the specified module name. The default is to report modules and library cells up the hierarchy of the specified module name. -Up

Reports on modules and library cells up the hierarchy of the specified module name. This is the default.

-Down

Reports on modules and library cells down the hierarchy of the specified module name.

-All

Displays “all” the modules within the given defaults. The top root module is denoted by (T).

-Top

Displays the top modules.

-Source

Displays the source-code information identifying where the module is located.

-Instantiation

Displays instances and modules.

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-USer

Reports only the modules defined in the design files, and skips the internal modules which are not defined in the design files. Note: Some internal modules can be created by the Conformal tools after reading the design files. These internal modules are not defined in the design files.

-VHDLname

Displays the full name, rather than just the entity name. For example: libname.entityname(architecturename).

-LEVEL value

Shows modules in a hierarchical order up to the specified level.

-Library

Displays all of the library cells that are in the module hierarchy.

-NOINTERLeave

Reports the Golden and Revised module hierarchies separately, first list Golden modules, and then list Revised modules. This is the default.

-INTERLeave

Reports the Golden and Revised module hierarchies together.

-Both

Displays information for both the Golden and Revised designs. This is the default.

-Golden

Displays module information for the Golden design.

-Revised

Displays module information for the Revised design.

Examples This example shows the difference between running the REPORT MODULES command without any options versus running the command with the -USer option. The following design file contains only one module named test. Module VDW_mult_nbw_u8_u8_16 is internal module which is not defined in this file: module test(aa, bb, oo); input [7:0] aa, bb; output oo; assign oo = aa * bb; endmodule

Running the following command: report modules

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Encounter Conformal Equivalence Checking Reference Manual Command Reference the Conformal software reports only the test module.

Related Commands REPORT MODULE ATTRIBUTE REPORT PATH

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REPORT MOS DIRECTION REPort MOs Direction [module_name] [-Summary | -Verbose] [-BIdirection | -UNidirection ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This is a Conformal Custom command. Displays the unidirectional and bidirectional transistor-MOS instances with their source and drain ports.


Reports on the named module.

-Summary

Displays a summary message of the total number of unidirectional and bidirectional transistor-MOS. This is the default.

-Verbose

Displays all of the unidirectional and bidirectional transistor-MOS.

-BIdirection

Displays only the bidirectional transistor-MOS instances. This is the default.

-UNidirection

Displays only the unidirectional transistor-MOS instances.

-Both

Displays MOS direction from both the Golden and Revised designs. This is the default.

-Golden

Displays MOS direction from the Golden design.

-Revised

Displays MOS direction from the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT NET ATTRIBUTE REPORT PIN DIRECTION RESOLVE

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REPORT MULTIPLIER OPTION REPort MUltiplier Option (Setup / LEC Mode)

Displays current multiplier option settings.

Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT DATAPATH OPTION SET DATAPATH OPTION SET MULTIPLIER OPTION SET FLATTEN MODEL

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REPORT NET ATTRIBUTE REPort NEt Attribute [-ALL | -VDD | -GND | -CLOCK0 | -CLOCK1 | -DYNSTate] [-Module ] [-Both | -Golden | -Revised]

Note: This is a Conformal Custom command. Displays attributes on transistor-MOS nets. The attributes were originally added with the ADD NET ATTRIBUTE command.

Parameters -ALL

Displays “all” added net attributes within the given defaults.

-VDD

Displays only the added VDD net attributes.

-GND

Displays only the added GND net attributes.

-CLOCK0

Displays only the added Clock-0 net attributes.

-CLOCK1

Displays only the added Clock-1 net attributes.

-DYNSTate

Displays only the added dynamic state net attributes.

-Module name

Reports net attributes from the named module.

-Both

Displays net attributes from both the Golden and Revised designs. This is the default.

-Golden

Displays net attributes from the Golden design.

-Revised

Displays net attributes from the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION

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Encounter Conformal Equivalence Checking Reference Manual Command Reference DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT PIN DIRECTION RESOLVE

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REPORT NET CONSTRAINTS REPort NEt Constraints [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all net constraints in the Golden and Revised designs that were added with the ADD NET CONSTRAINTS command.

Parameters -Both

Displays added net constraints in both the Golden and Revised designs. This is the default.

-Golden

Displays the added net constraints in the Golden design.

-Revised

Displays the added net constraints in the Revised design.

Related Commands ADD NET CONSTRAINTS DELETE NET CONSTRAINTS

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REPORT NOBLACK BOX REPort NOblack Box [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all of the modules in the Golden and Revised designs that will not be included in the hierarchical dofile script generation. These modules were originally specified with the ADD NOBLACK BOX command.

Parameters -Both

Displays added noblackboxes in both the Golden and Revised designs. This is the default.

-Golden

Displays the added noblackboxes in the Golden design.

-Revised

Displays the added noblackboxes in the Revised design.

Related Commands ADD NOBLACK BOX DELETE NOBLACK BOX WRITE HIER_COMPARE DOFILE

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REPORT NOTRANSLATE FILEPATHNAMES REPort NOtranslate Filepathnames [ | -Library | -Design] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays all of the library and design file pathnames originally added with the ADD NOTRANSLATE FILEPATHNAMES command. The Conformal software will not compile these modules defined in libraries and design files.

Parameters -Library

Displays only the added library file pathnames.

-Design

Displays only the added design file pathnames.

-Both

Displays added file pathnames in both the Golden and Revised designs. This is the default.

-Golden

Displays the added file pathnames in the Golden design.

-Revised

Displays the added file pathnames in the Revised design.

Related Commands ADD NOTRANSLATE FILEPATHNAMES ADD NOTRANSLATE MODULES DELETE NOTRANSLATE FILEPATHNAMES DELETE NOTRANSLATE MODULES REPORT NOTRANSLATE MODULES

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REPORT NOTRANSLATE MODULES REPort NOtranslate Modules (Setup / LEC Mode)

Displays all of the library and design modules originally added with the ADD NOTRANSLATE MODULES command. Conformal will not compile these modules when reading in libraries and designs.

Related Commands ADD NOTRANSLATE MODULES DELETE NOTRANSLATE MODULES READ DESIGN READ LIBRARY

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REPORT OUTPUT EQUIVALENCES REPort OUtput Equivalences [-ROot | -Module | -All ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the output pin equivalences in the Golden and Revised designs. These output pin equivalences were originally added with the ADD OUTPUT EQUIVALENCES command.

Parameters -ROot

Displays all output pin equivalences from the root module. This is the default.

-Module name

Displays the output pin equivalences in the specified module.

-All

Displays “all” output pin equivalences in all modules within the given defaults.

-Both

Displays the output pin equivalences in both the Golden and Revised designs. This is the default.

-Golden

Displays the output pin equivalences in the Revised design.

-Revised

Displays the output pin equivalences in the Golden design.

Related Commands ADD OUTPUT EQUIVALENCES DELETE OUTPUT EQUIVALENCES

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REPORT OUTPUT STUCK_AT REPort OUtput Stuck_at [-ROot |-Module | -All ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the output stuck_at values and pin names in the Golden and Revised designs. These output stuck_at values were originally added to pins with the ADD OUTPUT STUCK_AT command.

Parameters -ROot

Displays the output stuck_at values and pin names from the root module. This is the default.

-Module name

Displays the output stuck_at values and pin names from the specified module.

-All

Displays “all” output stuck_at values and pin names in “all” modules within the given defaults.

-Both

Displays the output stuck_at values and pin names in both the Golden and Revised designs. This is the default.

-Golden

Displays the output stuck_at values and pin names in the Revised design.

-Revised

Displays the output stuck_at values and pin names in the Golden design.

Related Commands ADD OUTPUT STUCK_AT DELETE OUTPUT STUCK_AT

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REPORT PARTITION KEY_POINT REPort PArtition Key_point (Setup / LEC Mode)

Displays the partition key points originally added with the ADD PARTITION KEY_POINT command.

Related Commands ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT WRITE PARTITION DOFILE

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REPORT PARTITION POINTS REPort Partition Points [-Both | -Golden | -Revised] [-Verbose | -Summary] (LEC Mode)

Note: This is a Conformal Ultra command. Displays the partition points that were created with the ADD PARTITION POINTS command.

Parameters -Both

Lists the partition points in both the Golden and Revised designs. This is the default.

-Golden

Lists the partition points in the Golden design.

-Revised

Lists the partition points in the Revised design.

-Verbose

Displays all added partition points. This is the default.

-Summary

Displays a summary message of the total number of added partition points.

Related Commands ADD PARTITION POINTS DELETE PARTITION POINTS

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REPORT PARTITION RESULT REPort PArtition Result (Setup Mode)

Displays the results after running partition dofile.

Related Commands ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT WRITE PARTITION DOFILE

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REPORT PATH REPort PAth < | -Feedback | -SELF | -SELF > [-Source] [-NET] [-SEQ_ASYNC] [-Golden | -Revised] (Setup / LEC Mode)

Displays the paths between a source gate and a destination gate. The -feedback option displays all feedback paths for all CUT gates. The source and destination gates can be: ■

Gate ID numbers

■

Instance paths

■

Pin paths

To report the feedback path on one CUT gate, use the same CUT gate ID, instance path, or pin path for both the source and the destination.

Parameters source

Specifies the gate ID number, instance path, or pin path of the source gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

destination

Specifies the gate ID number, instance path, or pin path of the destination gate. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version.

-Feedback

Reports the feedback path of “all” CUT gates. “All” applies within the given defaults.

-SELF []

Reports all loops to DFF and DLATs. If you specify a gate, it reports only loops to that gate.

-Source

Displays the file and line number location of the gate in the path.

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-NET

Displays the corresponding net of the gate in the path.

-SEQ_ASYNC

Reports DFF/DLAT to DFF/DLAT paths passing through the asynchronous set or reset of a sequential element.

-Golden

Reports the specified path in the Golden design. This is the default.

-Revised

Reports the specified path in the Revised design.

Related Commands ADD CUT POINT DELETE CUT POINT REPORT CUT POINT REPORT GATE

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REPORT PIN CONSTRAINTS REPort PIn Constraints [-ROot | -Module | -All] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the constraints placed on primary input pins in the Golden and Revised designs. These constraints were originally specified with the ADD PIN CONSTRAINTS command.

Parameters -ROot

Displays the pin constraints from the root module. This is the default.

-Module name

Displays the pin constraints from the specified module.

-All

Displays pin constraints in “all” modules. “All” applies within the given defaults.

-Both

Displays the constrained primary input pins from both the Golden and Revised designs. This is the default.

-Golden

Displays the constrained primary input pins from the Golden design.

-Revised

Displays the constrained primary input pins from the Revised design.

Related Commands ADD PIN CONSTRAINTS DELETE PIN CONSTRAINTS

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REPORT PIN DIRECTION REPort PIn Direction [-IO | -IN | -OUT] [module_name] [-Summary | -Verbose] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the assigned pin directions for each module. The default is to display only a summary message. Note: Use the ASSIGN PIN DIRECTION command to assign pin direction to module I/O pins.

Parameters -IO

Reports assigned module I/O pins. This is the default.

-IN

Reports assigned module input pins.

-OUT

Reports assigned module output pins.

module_name

Reports pin direction for the specified module. The default is to report pin direction for all modules.

-Summary

Displays only a summary message of assigned pin directions. This is the default.

-Verbose

Displays all assigned pin directions.

-Both

Reports the assigned pin directions in both the Golden and Revised designs. This is the default.

-Golden

Reports the assigned pin directions in the Golden design.

-Revised

Reports the assigned pin directions in the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK REPORT MOS DIRECTION REPORT NET ATTRIBUTE RESOLVE

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REPORT PIN EQUIVALENCES REPort PIn Equivalences [-ROot | -Module | -All] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays a list of added pin equivalences and inverted pin equivalences. These pin equivalences were originally added with the ADD PIN EQUIVALENCE command. Inverted pin equivalences are distinguished by a “-” next to the primary input pin name.

Parameters -ROot

Displays pin equivalences from the root module. This is the default.

-Module name

Displays pin equivalences from the specified module.

-All

Displays pin equivalences in “all” modules. “All” applies within the given defaults.

-Both

Displays pin equivalences from both the Golden and Revised designs. This is the default.

-Golden

Displays pin equivalences from the Golden design.

-REvised

Displays pin equivalences from the Revised design.

Related Commands ADD PIN EQUIVALENCES DELETE PIN EQUIVALENCES

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REPORT PRIMARY INPUTS REPort PRimary Inputs [-Class ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays primary input pins from the Golden and Revised designs.

Parameters -Class

Displays the following class of primary inputs. Full

Primary inputs from both the User and System classes This is the default.

System

Primary inputs from the original design

User

Primary inputs added with the ADD PRIMARY INPUT command

-Both

Displays both the Golden and Revised primary inputs. This is the default.

-Golden

Displays the Golden design primary inputs.

-Revised

Displays the Revised design primary inputs.

Related Commands ADD PRIMARY INPUT DELETE PRIMARY INPUTS

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REPORT PRIMARY OUTPUTS REPort PRimary Outputs [-Class ] [-Both |-Golden |-Revised] (Setup / LEC Mode)

Displays primary output pins from the Golden and Revised designs.

Parameters -Class

Displays the following class of primary outputs. Full

Primary outputs from both the User and System classes This is the default.

System

Primary outputs from the original design

User

Primary outputs added with the ADD PRIMARY OUTPUT command

-Both

Displays both the Golden and Revised primary outputs. This is the default.

-Golden

Displays Golden design primary outputs.

-Revised

Displays Revised design primary outputs.

Related Commands ADD PRIMARY OUTPUT DELETE PRIMARY OUTPUTS

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REPORT PULSE GENERATOR REPort PUlse Generator [-ALL | MODule ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This is a Conformal Custom command. Reports the instances that were transformed with the SET ABSTRACT MODEL -transform_pulse_generator_on command.

Parameters -ALL

Displays all instances. This is the default.

-MODule

Displays a specified module that was transformed.

-Both

Applies to both the Golden and Revised designs. This is the default.

-Golden

Applies to the Golden design.

-Revised


Related Commands SET ABSTRACT MODEL

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REPORT REMOVED INSTANCE REPort REMoved Instance [-Golden | -Revised] (Setup / LEC Mode)

Report instances removed with the REMOVE command.

Parameters -Golden

Reports instances removed from the Golden design. This is the default.

-Revised

Reports instances removed from the Revised design.

Related Command REMOVE

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REPORT RENAMING RULE REPort REnaming Rule [ |-MAp | -MOdule | -PIn] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the list of renaming rules for mapping, module, and pin renaming. These rules were originally added with the ADD RENAMING RULE command. The list displays a rule number along with a renaming rule. If you do not enter options, Conformal displays all renaming rules.

Parameters -MAp

Displays only mapping renaming rules. If you do not specify -map, -module, or -pin, Conformal reports all renaming rules.

-MOdule

Displays only module renaming rules.

-PIn

Displays only pin renaming rules.

-Both

Displays the renaming rules applied to both the Golden and Revised designs. This is the default.

-Golden

Displays the Golden design renaming rules.

-Revised

Displays the Revised design renaming rules.

Related Commands ADD RENAMING RULE DELETE RENAMING RULE READ DESIGN READ LIBRARY SET MAPPING METHOD SET NAMING RULE TEST RENAMING RULE

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REPORT RETENTION MAPPING REPort REtention Mapping (Setup / LEC Mode)

Note: This is a Conformal Low Power command. Reports the retention mapping rules. The set of rules reported include the user rules added using the ADD RETENTION MAPPING command and the default rule added by the system. For a description of the default rules that are added by the system, see CHECK LOWPOWER CELLS on page 143. Note: The default rule is always reported even if no user rule is added using the ADD RETENTION MAPPING command.

Related Commands ADD RETENTION MAPPING DELETE RETENTION MAPPING

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REPORT RULE CHECK REPort RUle Check [-All | -MODIfied | rule_name*… [-SETTING] ] [-File [linenumber]] [-MODUle ] [-Summary | -Verbose] [-HELP] [ | -Design | -Library] [-Ignore] [-Note] [-Warning] [-Error] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays the list of rule violations after the designs and libraries have been read in. Use the -summary option to display all of the violated rules. Use the SET RULE HANDLING command to change the handling of any of these reported rule violations. See the Encounter Conformal Equivalence Checking User Guide for rule definitions and sample cases. Rules with a severity of “Ignore” are not reported except with the rule_name or -ignore options.

Parameters -All

Reports “all” rule violations encountered in the designs and libraries. “All” applies within the given defaults. This is the default.

-MODIfied

Reports all the rule check violations that have a different severity level than the original default.

rule_name…

Reports specified rule violations. Wildcards are supported.

-SETTING

Displays the current severity level for the rule.

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-File filename [linenumber] Reports all rule check messages in a file. With the linenumber option, you can report all rule check messages for a specific line number. -Module modname

Reports the rule checks that are specific to the specified module.

-Summary

Display a summary of the rule violations. This is the default.

-Verbose

Displays each instance of the rule violation.

-HELP

Lists the names and numbers of all HDL rules.

-Design

Reports the design rule violations. If you do not specify -design or -library, the Conformal software reports rule violations from both designs and libraries.

-Library

Reports the library rule violations. If you do not specify -design or -library, the Conformal software reports rule violations from both designs and libraries.

-Ignore

Reports violations that have a severity level of Ignore.

-Note

Reports violations that have a severity level of Note.

-Warning

Reports violations that have a severity level of Warning.

-Error

Reports violations that have a severity level of Error.

Note: By default, rules with severity levels other than Ignore will be reported -Both

Reports the rule violations from Golden and Revised designs and libraries. This is the default.

-Golden

Reports the Golden design and library rule violations.

-Revised

Reports the Revised design and library rules violations.

Related Commands READ DESIGN READ LIBRARY SET RULE HANDLING

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REPORT SEARCH PATH REPort SEarch Path [ | -Design | -Library] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Displays the paths Conformal searches to locate filenames included in the READ DESIGN and READ LIBRARY commands.

Parameters -Design

Reports the search path used by the READ DESIGN command. If you do not specify -design or -library, Conformal reports the search path used by both the READ DESIGN command and the READ LIBRARY command.

-Library

Reports the search path used by the READ LIBRARY command. If you do not specify -design or -library, Conformal reports the search path used by both the READ DESIGN command and the READ LIBRARY command.

-Both

Reports the search path used by both the Golden and Revised designs. This is the default.

-Golden

Reports the search path used by the Golden design and library.

-Revised

Reports the search path used by the Revised design and library.

Related Commands ADD SEARCH PATH DELETE SEARCH PATH READ DESIGN READ LIBRARY

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REPORT STATISTICS REPort STatistics (LEC Mode)

Summarizes the mapping and comparison statistics for the Golden and Revised designs in a table.

Related Commands REPORT COMPARE DATA REPORT COMPARED POINTS REPORT MAPPED POINTS REPORT UNMAPPED POINTS

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REPORT TESTCASE REPort TEstcase < [-NONEQ] [-ABORT] [-Golden < | ...> ] [-Revised < | ...> ] > [-DIR_name ] [-NAME | -NONAME] [-KEYPOINT_DEPTH ] [-REPlace] (LEC Mode)

Automatically extracts testcases for selected key points and generates a dofile and a file containing mapping information. Running the generated dofile can reproduce the problem in original design, such as non-equivalences and aborts.

Parameters -NONEQ

Specifies that all non-equivalent points will be selected for the generated testcase.

-ABORT

Specifies that all abort points will be selected for the generated testcase.

-GOlden

Applies the testcase extraction to the Golden design.

-Revised

Applies the testcase extraction to the Revised design.

Specifies the gate ID of the testcase. You can specify multiple gate IDs.

Specifies the instance pathname of the testcase. You can specify multiple instance pathnames.

-DIR_name Specifies the name of the testcase directory. -NAME

Includes the names of design objects (nets, instances, ports) in the generated testcase. This is the default.

-NONAME

Does not includes the names of design objects (nets, instances, ports) in the generated testcase.

-KEYPOINT_DEPTH

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Specifies the depth of the key points to report. Starting from the selected key point, the closest key point in its fanin or fan-out cone is a depth of 1. The default is 3. -REPlace

Overwrites the existing testcase directory.

Examples ■

The following command selects all non-equivalent points, all abort points, and key points with gate id 10, with instance dlat in the Golden design netlist and the key point with instance dff in the Revised design netlist, allowing the names of design objects to be included in the generated testcase: report testcase -noneq -abort -golden 10 dlat -revised dff

■

The following command will select key point with gate id 10 in Revised design netlist for testcase extraction. The names of design objects will use generic names (gate type and a serial number) report testcase -revised 10 -noname

■

The following command will select all non-equivalent points for testcase extraction, using keypoint depth: report testcase -noneq -keypoint_depth 1

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REPORT TEST VECTOR REPort TEst Vector < gate_id | instance_pathname | pin_pathname> [ [-Index ]] [-Golden |-Revised] | [-NONEQ] (LEC Mode)

Displays error patterns for a specific nonequivalent compared point. ■

The first argument is the nonequivalent compared point. This point can be identified with a gate identification number, instance path, or a pin path.

■

The second argument, which is optional, is the diagnosis input point. These points are gates that connect directly to the input ports of the nonequivalent compared point where the logic cones are different. The display shows the diagnosis input point to the nonequivalent compared point; corresponding and non corresponding support key points with their simulation values; and final simulation result of the diagnosis input point

■

The Index option is used to specify which error pattern is displayed after you use the command. If you do not specify an index number, Conformal displays the first error pattern.

You can also use this command with the -noneq option to report error patterns for every nonequivalent compared key point.

Parameters gate_id | instance_pathname | pin_pathname Specifies the gate identification number, instance path, or pin path of the nonequivalent compared point. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. gate_id |instance_pathname | pin_pathname

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Specifies the gate identification number, instance path, or pin path of the diagnosis input point to the nonequivalent compared point. Note: These options apply only to diagnosis points for DFF, DLAT, and BBOX. If you enter a point that is not a diagnosis point, Conformal will error out. Note: ID numbers can differ from one version of Conformal to another. Always use the full path in dofiles and any time you rerun a design with a different Conformal version. -Index integer

Displays the specified error pattern. The default is to display the first error pattern.

-Golden

Specifies that the nonequivalent compared point is from the Golden design. This is the default.

-Revised

Specifies that the nonequivalent compared point is from the Revised design.

-NONEQ

Displays the error pattern for every nonequivalent point.

Related Command DIAGNOSE

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REPORT TIED SIGNALS REPort TIed Signals [-ROot | -Module ] [ | -TIE0 | -TIE1 | -TIEZ | -TIEX] [ | -Net | -Pin] [-Class ] [-Both | -Golden | -REvised] (Setup / LEC Mode)

Displays tied signals from the Golden and Revised designs.

Parameters -ROot

Displays tied signals in the root module. This is the default.

-Module name

Displays tied signals in the specified module.

-TIE0

Displays signals tied to logic 0. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X.

-TIE1

Displays signals tied to logic 1. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X.

-TIEZ

Displays signals tied to logic Z. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X.

-TIEX

Displays signals tied to logic X. If you do not specify the logic, Conformal displays signals tied to logic 0, 1, Z, and X.

-All

Displays “all” net and instance names that have tied signals assigned to them. “All” applies within the given defaults. This is the default.

-Net

Displays net names that have tied signals assigned to them.

-Pin

Displays pin names that have tied signals assigned to them.

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-Class

Displays this class of tied signals: Tied signals from both the User and System classes

Full

This is the default. System

Tied signals from the original design.

User

Tied signals added with the ADD TIED SIGNALS command.

-Both

Displays tied signals from both the Golden and Revised designs. This is the default.

-Golden

Displays tied signals from the Golden design.

-REvised

Displays tied signals from the Revised design.

Related Commands ADD TIED SIGNALS DELETE TIED SIGNALS

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REPORT UNMAPPED POINTS REPort UNmapped Points [-SUMmary| -Extra | -UNReachable | -NOTmapped | [ -TYpe … |-NOTYpe …] ] [-GRoup] [-LIBName | -NOLIBName] [-RETention] [-NODLAT_GATED_CLOCK] [-GOlden | -Revised] (LEC Mode)

This report lists unmapped points, along with a summary of all of the unmapped points in the Golden and Revised designs. Note: If you do not specify options, Conformal identifies all unmapped points and displays a summary. Furthermore, if you do not specify either Golden or Revised, Conformal reports unmapped points for both designs.

Parameters -SUMmary

Lists a summary report of all of the unmapped points in the Golden and Revised designs. This is the default.

-Extra

Lists extra points. These points are unmapped because they do not map with a counterpart in the comparison design. Extra points do not affect the circuit.

-UNReachable

Lists unreachable unmapped points. Unreachable key points are those that do not eventually affect the primary output of the design.

-NOTmapped

Lists “Not-mapped” unmapped key points. Not-mapped key points are those that failed to be mapped.

-Type

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Lists unmapped points of the specified type. Available types are as follows: PI

Primary input

E

TIE-E

Z

TIE-Z

DFf

D flip-flop

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DLat

D-latch

CUt

All unmapped points for artificial gates that break combinational loops

BBox

Blackbox

PO

Primary output

-NOType

Does not list unmapped points of the specified type.

-GRoup

Displays the unmapped groups in which either the Golden or Revised key point is a group of equivalent gates rather than a single gate. The group can be defined with the ADD INSTANCE EQUIVALENCE command or the -seq_merge option of the SET FLATTEN MODEL command. A key point group is counted as one key point.

-LIBName

When displaying unmapped points, includes suffixes. This is the default.

-NOLIBName

When displaying unmapped points, does not include suffixes.

-RETention

Note: This is a Conformal Low Power option. If the unmapped point is a sequential element (DFF or DLAT) and belongs to the Golden Design, this option reports the tag-name (if any) associated with the DFF or DLAT. If the unmapped point is a sequential element (DFF or DLAT) and belongs to the Revised Design, this option reports the power gating cell attribute (if any) associated with the DFF or DLAT. For non-sequential elements, nothing is reported. The sequential unmapped points are not written out during the CHECK RETENTION MAPPING command, but if present, they are reported as ’Not-Checked’ in the summary section.

-NODLAT_GATED_CLOCK Does not report deglitching clock-gating DLATs under the Unreachable category. -GOlden

Lists only the Golden unmapped points. This is the default.

-Revised

Lists only the Revised unmapped points.

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Related Commands ADD MAPPED POINTS DELETE MAPPED POINTS MAP KEY POINTS REPORT MAPPED POINTS REPORT STATISTICS SET MAPPING METHOD SET NAMING RULE

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REPORT VERIFICATION REPort VErification [-Verbose] [-Summary] (LEC Mode)

Reports a table of all violated checklist items for the following categories: 1. Non-standard modeling options used: ❑

Tristated output: checked/not checked

❑

Revised X signals set to E: yes|no

❑

Floating signals tied to Z: yes|no

❑

Command add clock for clock-gating used: yes|no

2. Incomplete verification: ❑

All primary outputs are mapped: yes|no

❑

All mapped points added as compare points: yes|no

❑

All compare points compared: yes|no

❑

User added black box: yes|no

❑

Black box mapped with different module name: yes|no

❑

Command add ignore outputs used: yes|no

3. Modification to design: ❑

Change gate type: yes|no

❑

Change wire: yes|no

❑

Primary inputs added: yes|no

4. Conformal extended checks recommended: ❑

FSM encoding: used|not used

❑

RTL5.1 Overlapped case items in parallel case statement: used|not used

❑

RTL5.4 Partial case items in full case statement: used|not used

❑

Multiple clocks in the design: yes|no

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 5. Design ambiguity: ❑

Duplicate module definition: yes|no

❑

Black box due to undefined cells: yes|no

6. Compare results: FAIL|ABORT|INCOMPLETE| EQ|NOT_COMPARED ❑

Number of EQ compare points:

❑

Number of NON-EQ compare points:

❑

Number of Aborted compare points:

❑

Number of Uncompared compare points:

Parameters -Verbose

Prints out each category and the count of violations.

-Summary

Prints all items for each category and the violated items are marked with an asterisk (*).

Related Command COMPARE

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RESET RESET (Setup / LEC Mode)

Resets the system to the initial state. All existing designs and libraries are deleted, and all previously issued commands are cancelled.

Related Commands RESET HIER_COMPARE RESULT EXIT

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RESET ABSTRACT MODEL REset ABSTract Model [-ALL | -MODule ] [-Both | -Golden | -Revised] (Setup / LEC Mode)

Note: This is a Conformal Custom command. Resets the abstraction conditions that you set using the SET ABSTRACT MODEL command.

Parameters -All

Resets abstraction conditions for all modules.

-MODule module_name… Resets abstraction conditions for the specified modules. -Both

Resets abstraction conditions for both the Golden and Revised designs. This is the default.

-Golden

Resets abstraction conditions for the Golden design.

-Revised

Resets abstraction conditions for the Revised design.

Related Commands ABSTRACT LOGIC REPORT ABSTRACT MODEL SET ABSTRACT MODEL

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RESET HIER_COMPARE RESULT RESet HIer_compare Result (Setup / LEC Mode)

Resets the results of the hierarchical comparison. It is useful when you do multiple hierarchical compare runs and you wish to display the results of each hierarchical compare separately.

Related Commands RUN HIER_COMPARE REPORT HIER_COMPARE RESULT RESET SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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RESOLVE RESolve [-All] [-Golden | -Revised] (Setup Mode)

Note: This is a Conformal Custom command. Ungroups a module in the Golden or Revised design hierarchy. Resolving or ungrouping is the process of eliminating a module and promoting its content up one level of the hierarchy.


Resolves hierarchy for the specified module.

-All

Resolves the specified module within all hierarchies of the specified design.

-Golden

Resolves hierarchy in the Golden design. This is the default.

-Revised

Resolves hierarchy in the Revised design.

Related Commands ABSTRACT LOGIC ADD CLOCK ADD MOS DIRECTION ADD NET ATTRIBUTE ASSIGN PIN DIRECTION DELETE CLOCK DELETE MOS DIRECTION DELETE NET ATTRIBUTE READ PATTERN REPORT CLOCK May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference REPORT MOS DIRECTION REPORT NET ATTRIBUTE REPORT PIN DIRECTION UNIQUIFY

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RESTORE SESSION REStore SEssion (Setup / LEC Mode)

Restores a session you previously initiated and saved using the SAVE SESSION command. Before entering this command, Conformal must be in its initial state. Therefore, you must either use the RESET command, or exit Conformal and restart it. Important You must run this restarted session on the same platform and same Conformal version.

Parameters session_name

Restores the specified session.

Related Commands RESET SAVE SESSION

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RUN HIER_COMPARE RUN HIer_compare [-ROOT_module ] [-DYNamic_hierarchy | -NODYNamic_hierarchy] [-NOREStart | -REStart] [-ANALYZE_abort] [-RETIMED_modules [-TOP | -NOTOP]] [-BREAK_NONEQ] [-BREAK_ABORT] [-ANALYZE_BOUNDARY_conditions | -NOANALYZE_BOUNDARY_conditions] [-VERBOSE] (Setup Mode)

Note: This is a Conformal Ultra command. Runs dynamic hierarchical comparison. This command on completion produces one of the following three statuses: ■

Equivalent—all the compared modules are equivalent.

■

Non-Equivalent—at least one of the compared module is non-equivalent.

■

Inconclusive—indicates one of the following conditions: ❑

at least one of the compared module has abort points

❑

at least one module is not-compared (for example, due to running the add module attribute -compare_effort none command)

❑

at least one module has incomplete compare result (for example, due to extra primary outputs)

Note: When the status is Inconclusive the number of abort modules, not-compared modules, or modules that have incomplete compare result are reported. For more information, see Dynamic Hierarchical Comparison in the Encounter Conformal Equivalence Checking User Guide.

Specifies the name of the hierarchical dofile that was generated with the WRITE HIER_COMPARE DOFILE command. Note: Cadence does not recommend manually editing or modifying this hierarchical dofile prior to running the RUN HIER_COMPARE command. This might lead to unexpected results. If you want to edit or modify the hierarchical dofile, use the static hierarchical comparison (dofile hier.do).

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-ROOT_module Uses the specified modules as the root modules. This is similar to the -Module option with the WRITE HIER_COMPARE DOFILE command without having to the regenerate the dofile. -DYNamic_hierarchy Auto-flattens the submodules to propagate any design errors to the top level. The flattened modules are merged to the next level in the hierarchy and compared at that level. This is the default. -NODYNamic_hierarchy Runs static hierarchical comparison without auto-flattening the submodules. Note: Do not use this option if the hierarchical dofile is generated using the WRITE HIER_COMPARE DOFILE -run_hier_compare command. -NOREStart

Continues an interrupted session, preserving the previous compare results. This is the default. You can interrupt dynamic hierarchical comparison by pressing Ctrl-c.

-REStart

Deletes the previous comparison results.

-ANALYZE_abort

Inserts the ANALYZE ABORT -compare command into each uncompared and aborted module’s compare script.

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-RETIMED_modules [-TOP | -NOTOP] Compares and blackboxes the submodules with the PIPELINE_Retime attribute. The PIPELINE_Retime attribute can be attached to a module using the ADD MODULE ATTRIBUTE command. For this option to work correctly, modules with PIPELINE_Retime attribute should exist in the hierarchical dofile script. -TOP runs the comparison of the top module such that submodules without the PIPELINE_Retime attribute are fully flattened. This is the default for -RETIMED_module. -NOTOP specifies that comparison stops after the modules with the PIPELINE_Retime attribute have been compared and blackboxed. The hierarchical result is reported as ‘Inconclusive’ because the entire design is not compared. -BREAK_NONEQ

The comparison stops when it encounters a non-equivalent module. To continue comparing from the next module in the hierarchy, use the RUN HIER_COMPARE command.

-BREAK_ABORT

The comparison stops when it encounters an abort module. To continue comparing from the next module in the hierarchy, run the RUN HIER_COMPARE command.

-ANALYZE_BOUNDARY_conditions Reduces the number of flattened modules by resolving boundary constraints. This is the default. -NOANALYZE_BOUNDARY_conditions Does not perform resolution on boundary constraints. Note: Do not use this option if the hierarchical dofile is generated using the WRITE HIER_COMPARE DOFILE -run_hier_compare command. -VERBOSE

Lists all the hierarchical constraints and additional information.

Examples ■

The following command uses the hier.do dofile for hierarchical comparison: run hier_compare hier.do

If the previous comparison run of the hier.do dofile resulted in three aborted modules, you can run a second comparison using the following command: May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference run hier_compare hier.do -analyze_abort

This command only operates on aborted modules from the previous run, and automatically runs the ANALYZE ABORT -compare command after the default COMPARE command. ■

The following command uses m4 as the root module for both the Golden and Revised designs, deleting the previous comparison results: run hier_compare hrcmod.do -root_module m4 m4

■

-restart

The following command runs hierarchical comparison on modules with the PIPELINE_Retime attribute attached: run hier_compare hier.do -retimed_modules

Related Commands ANALYZE ABORT COMPARE REPORT HIER_COMPARE RESULT RESET HIER_COMPARE RESULT SAVE HIER_COMPARE RESULT WRITE HIER_COMPARE DOFILE

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RUN PARALLEL COMPARE RUN PArallel Compare [-NONEQ_Stop ] [-ABORT_Stop ] [-NONEQ_Print] [-ABORT_Print] [-GATE_TO_GATE] [-TEST] [-SUBMIT_OPTIONs ] [-DPL] (LEC Mode)

Note: This is a Conformal Ultra command. Runs equivalency checking comparison between the Golden and Revised designs on the added compared points using parallel processing. During the comparison, the Conformal software displays following information: ■

A progress percentile number that shows the completion rate

■

A running count that shows the number of key points that have been compared along with the total number of non-equivalent key points

Parameters -NONEQ_Stop

Stops the comparison after finding the specified number of non-equivalent points.

-ABORT_Stop

Stops the comparison after finding the specified number of abort points.

-NONEQ_Print

Displays the non-equivalent points as they are found.

-ABORT_Print

Displays the abort points as they are found.

-GATE_TO_GATE

Enables an algorithm that might improve the run time of large gate-to-gate netlist comparisons.

-TEST

Launches qualification run to test if the environment is suitable for parallel processing.

-SUBMIT_OPTIONs

Specifies the options which will replace the keyword in the submit command line (see the SET PARALLEL OPTION -SUBMIT_COMMAND_LINE command).

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-DPL

Uses the Cadence Distributed Processing Library (DPL) to interface to the Load Sharing Facility (LSF) daemon. Refer to the Cadence DPL User Guide for more information.

Examples The following commands run the first parallel job in queue q1, and the second parallel run in queue q2. run parallel compare -submit_options "-q q1" run parallel compare -submit_options "-q q2"

Related Commands COMPARE SET PARALLEL OPTION

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RUN PARTITION_COMPARE RUN PArtition_compare [-Keypoint ] [-Number ] [-VERBOSE] (LEC Mode)

Note: This is a Conformal Ultra command. Runs comparisons with functional partitioning. You can specify partitioned key points in the Golden design and the number of key points for a partition. If no key points are specified, this command will automatically choose appropriate key points for the partition. Note: You do not need to switch to Setup mode to flatten the netlist in each partition iteration. With the constants assigned on the selected key points, comparison can become easier in each partition iteration. For example, when abort points are encountered in comparison, you can run this command to do functional partitioning for the abort points. -Keypoint

Specifies the partition key point in the Golden design. The key point can be specified by gate instance pathname or gate ID. If no key points are specified, this command will automatically choose appropriate key points for the partition.

-Number

Specifies the number of key points for a partition. The maximum number of compare iterations is the base-2 exponent of the partitioned key point number. The default partitioned key point number is 8.

-VERBOSE

Provides additional information in the functional partition.

Related Commands COMPARE

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SAVE DOFILE SAVe DOfile [-Replace] (Setup / LEC Mode)

Saves the commands entered during the current session to a file. Use the saved dofile later as a batch file to repeat the Conformal session. When running a Conformal session from a dofile, this command does not save individual commands included in a separate dofile (that is, Conformal saves the manually entered commands, which can include a dofile command). Note: If the filename you specify already exists, you must use either the -replace or -append option. filename

Writes the dofile to the specified file.

-Replace

Replaces the contents of the specified preexisting file.

Related Commands DOFILE SET COMMAND PROFILE SET LOG FILE

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SAVE HIER_COMPARE RESULT SAVe HIer_compare Result (LEC Mode)

Saves the hierarchical comparison results of the module comparison. If the WRITE HIER_COMPARE DOFILE command is used, this command is placed after every module compared. After the hierarchical comparison of all modules is complete, use the REPORT HIER_COMPARE RESULT command to display the results of the hierarchical comparison.

Related Commands REPORT HIER_COMPARE RESULT RESET HIER_COMPARE RESULT RUN HIER_COMPARE WRITE HIER_COMPARE DOFILE

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SAVE SESSION SAVe SEssion [-REPlace] (Setup / LEC Mode)

Saves your session up to a current point and outputs the session file in gzip format. You can then restore the session later using the RESTORE SESSION command. You can use this command if priorities demand that another session preempt your session. Important When you use the RESTORE SESSION command, you must run the restarted session on the same platform and same Conformal version.

Parameters -REPlace

Replaces the existing session. If the session already exists, it will be overwritten and no backup copy will be created. By default, backup copies are created automatically. This option is useful if you want to save disk space and only need to save your session occasionally.

session_name

Attaches this session name to the saved session.

Related Command RESTORE SESSION

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SEARCH SEArch [-USage] []… (Setup / LEC Mode)

Searches the database of commands and parameters, and displays those commands that match all of the specified strings. Strings can be specified in any order; however, every specified string must match.

Parameters -USage

Displays the commands that have parameters that match the search string. This outputs the entire command syntax for each command.

string1

Displays commands that match the specified string.

string2…

Displays commands that match additional specified strings.

Related Command HELP

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SET ABSTRACT MODEL SET ABSTract Model [-ALL |-MODule ] [-NOKEEPER2PUllup | -KEEPER2PUllup ] [-NOWEAKPULLUP | -WEAKPULLUP ] [-NOWEAKPULLDOWN | -WEAKPULLDOWN ] [-NOKEEPERSTate | -KEEPERSTate ] [-NODYNSTate | -DYNSTate ] [-NOPRE_CHARGE_KEEP_Clock | -PRE_CHARGE_KEEP_Clock ] [-NODOMINOLATch | -DOMINOLATch ] [-Bulk | -NOBulk ] [-NOMEM_BL_EQualizer | -MEM_BL_EQualizer] [-NOBUF_AMP | -BUF_AMP] [-NOMULTICLOCKPRECHARGE | -MULTICLOCKPRECHARGE] [-REPHASE_BY_NAME_POSitive ] [-REPHASE_BY_NAME_NEGative ] [-TRANSFORM_PULSE_GENERATOR_ON] [-NOIGNORE_DLAT_CONTENTION | -IGNORE_DLAT_CONTENTION] [-Both | -Golden | -Revised ] (Setup Mode)

Note: This is a Conformal Custom command. Specify certain conditions for abstracting transistor logic. Refer to the Encounter Conformal Equivalence Checking User Guide for additional information about using this command in the Conformal Custom flow.

Parameters -ALL

Abstracts transistor logic from all modules within the given defaults. This option is the default.

-MODule module_name… Abstracts transistor logic from the specified modules. -NOKEEPER2PUllup

Does not regard charge keepers as weak pull-up devices. This is the default.

-KEEPER2PUllup

Regards charge keepers as weak pull-up devices.

-NOWEAKPULLUP

Does not regard devices that are tied to PMOS as weak devices. This is the default.

-WEAKPULLUP

Regards devices that are tied to PMOS as weak devices.

-NOWEAKPULLDOWN

Does not regard devices that are tied to NMOS as weak devices. This is the default.

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-WEAKPULLDOWN

Regards devices that are tied to NMOS as weak devices.

-NOKEEPERSTate

Does not regard charge keepers as latches. This is the default.

-KEEPERSTate

Regards charge keepers as latches.

-NODYNSTate

Does not regard tristate table nets as latches. This is the default.

-DYNSTate

Regards tri-statetable nets as latches.

-NOPRE_CHARGE_KEEP_Clock In domino logic, does not regard pre-charge clocks as part of the logic function. This is the default. -PRE_CHARGE_KEEP_Clock For domino logic, regards pre-charge clocks as part of the logic function. This option includes the defined pre-charge clock in the abstracted logic function (the default behavior removes the defined pre-charge clock from the abstracted logic). This is indicated when you define a precharge clock with one of the following commands: add net attribute CLOCK0 | CLOCK1 add clock 0 | 1

When you use -pre_charge_keep_clock, the resulting logic is equivalent to RTL that explicitly models the pre-charge condition, rather than RTL that models only the evaluate function. In the latter, the output function is not defined during pre-charging. -NODOMINOLATch

Does not abstract pre-charge logic functions as a latch. This is the default.

-DOMINOLATch

Abstracts pre-charge logic functions as a latch. This assumes that data input is stable in active clocks.

-BULK

Identifies nets connected to PMOS bulk terminals as power and nets connected to NMOS bulk terminals as ground. This is the default.

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-NOBULK

By default, Conformal Custom identifies nets connected to PMOS bulk terminals as power and nets connected to NMOS bulk terminals as ground. However, this option removes that assumption and you will need to specify power and ground pins/nets by using *.GLOBAL :P for power nets and *.GLOBAL :G for ground nets or use Conformal commands to add constraints, tied signals (pins), or net attributes. Important You must use SET ABSTRACT MODEL -NOBulk before reading in the SPICE file.

-NOMEM_BL_EQualizer Does not handle bit-line pre-charge, and equalization. This is the default. -MEM_BL_EQualizer

Handles circuits that include bit-line pre-charge, and equalization.

-NOBUF_AMP

Does not handle buffered-type sense amplifiers, level shifters, pre-charge, and equalization. This is the default.

-BUF_AMP

Handles the following portions of a circuit: buffered-type sense amplifiers, level shifters, pre-charge, and equalization.

-NOMULTICLOCKPRECHARGE Does not propagate clocks through logic gates which have more than one clock input. This is the default. -MULTICLOCKPRECHARGE Propagates clocks through logic gates which have more than one clock input.

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-REPHASE_BY_NAME_POSitive Gives abstract logic a hint about the desired phase of state elements, such as D-latches and DFFs. When abstracting state elements, abstract logic will choose a phase for each state element, where specifies the net which will be driven by the ’Q’ pin, if possible. If this is not possible, then abstraction will try to choose a net for the ’Qn’ pin which has a name specified by the -REPHASE_BY_NAME_NEGative option. Note: The set mapping method command’s -phase option will allow mapping and comparison of state elements with different phases in the Golden and Revised designs. Consider running set mapping method -phase before using this option, as it requires less effort. -REPHASE_BY_NAME_NEGative Specifies the net which will be driven by the ’Qn’ pin, if possible. -TRANSFORM_PULSE_GENERATOR_ON Enables pulse transformation. -NOIGNORE_DLAT_CONTENTION Stops forming the D-Latch when contention on a net is detected. This is the default. -IGNORE_DLAT_CONTENTION Continues to form the D-Latch, even if contention on a net is detected. By default, the SET ABSTRACT MODEL command stops the execution of abstraction of latches and flip-flips (state elements) when a power to ground through a stack of active ON transistors is possible. Use this option to report the short and continue to abstract the state element. -Both

Specifies abstraction conditions for both the Golden and Revised designs. This is the default.

-Golden

Specifies abstraction conditions for the Golden design.

-Revised

Specifies abstraction conditions for the Revised design.

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Examples Sample Dofile: read design test.v -golden set abstract model -keeper2pullup -weakpullup -golden report abstract model -golden abstract logic

Related Commands ABSTRACT LOGIC ADD CLOCK ADD NET ATTRIBUTE REPORT ABSTRACT MODEL REPORT PULSE GENERATOR RESET ABSTRACT MODEL

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SET ANALYZE OPTION SET ANalyze Option [-NOAUTO | -AUTO [-ANALYZE_SETUP | -NOANALYZE_SETUP] [-ANALYZE_ABORT | -NOANALYZE_ABORT] ] (Setup Mode)

Note: This is a Conformal Ultra command. Automatically determines the best place to run the ANALYZE SETUP command. In addition, the Conformal software automatically runs the ANALYZE ABORT command whenever the comparison returns abort points but no non-equivalent points.

Parameters -NOAUTO

Disables automatic analysis. This is the default.

-AUTO

Enables automatic analysis.

-ANALYZE_SETUP

Enables automatic setup analysis. This is the default when running this command with the -AUTO option.

-NOANALYZE_SETUP

Disables automatic setup analysis.

-ANALYZE_ABORT

Enables automatic abort point analysis. This is the default.

-NOANALYZE_ABORT

Disables automatic abort point analysis.

Related Command ANALYZE ABORT ANALYZE SETUP

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SET_ATTR INPUT_PRAGMA_KEYWORD SET_ATtr INPUT_PRAGMA_Keyword (Setup Mode)

Specifies a keyword that the Conformal software must consider as an input pragma when it encounters it as the first word in a Verilog or VHDL source comment. A pragma is a comment in the Verilog or VHDL source and is set off from ordinary comments by the pragma keyword. The pragma keyword is the first word listed in a pragma, and it notifies the Conformal software that the remainder of the comment is a command and not a comment. Changing this keyword allows you to set up compatibility with other tools.

Parameters string

Specifies the name of the keyword for a tool vendor. Default: pragma, synthesis, synopsys, cadence, ambit, verplex, conformal

Examples Sample Dofile: set_attr input_pragma_keyword rtl set synthesis_off_command turn_off set synthesis_on_command turn_on

After running these three commands, the Conformal and VHDL parsers will recognize the pragmas in the VHDL and Verilog Source files. In a VHDL file, the code between -- rtl turn_off and -- rtl turn_on will not be synthesized. In a Verilog file, the code between // rtl turn_off and // rtl turn_on will not be synthesized.

Related Commands SET SYNTHESIS_OFF_COMMAND SET SYNTHESIS_ON_COMMAND May 2008

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SET CASE SENSITIVITY SET CAse Sensitivity (Setup Mode)

Specifies whether names you enter are case sensitive. The system default is no case sensitivity for both the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. Use the REPORT ENVIRONMENT command to display the case sensitivity setting.

Parameters ON

Names that are entered are case sensitive.

OFf

Names that are entered are not case sensitive. This is the system default.

Related Command REPORT ENVIRONMENT

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SET COMMAND PROFILE SET COmmand PRofile [OFF | ON] (Setup / LEC Mode)

Starts or stops recording a profile of commands executed in Conformal. This command records the order of command execution and the memory use. The profile includes commands used in the GUI mode. Use the REPORT COMMAND PROFILE command to view the profile.

Parameters OFF

Stops tracking executed commands. This is the default.

ON

Starts tracking executed commands.

Related Commands REPORT COMMAND PROFILE SET LOG FILE

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SET COMPARE EFFORT SET COmpare Effort (Setup / LEC Mode)

Specifies the amount of effort equivalency checking applies to the key points comparison. If you know your designs have many complex key points, increase the effort level. However, when you raise the effort level, you also increase the amount of time involved in checking. Hence, you increase the total CPU time. Use the REPORT ENVIRONMENT command to display the compare effort setting. The system default is set to low compare effort.

Parameters Low

Applies minimal effort to equivalency checking for each gate. This is the default.

Medium

Applies greater effort to equivalency checking for each gate.

High

Applies the maximum effort to equivalency checking for each gate.

Auto

Starts with low effort and automatically increases the compare effort when abort points are present in the design.

Related Commands COMPARE REPORT ENVIRONMENT

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SET COMPARE OPTIONS SET COmpare Options [-GENLATCH | -NOGENLATCH] [-NOALLGENLATCH | -ALLGENLATCH] [-VERIFY_Disabled_ports] (Setup / LEC Mode)

Turns on options to the comparison process.

Parameters -GENLATCH

Compares latches as generic latches by analyzing all logic cones simultaneously. The software automatically determines which latches are to be compared as generic latch, and the reset are compared by individual logic cones. This is the default. With this option, you can compare latches that are truly functionally equivalent, even though the logic cones of the separate input pins are not.

-NOGENLATCH

Specifies that no latch is compared as a generic latch. All latches are compared by individual logic cones.

-NOALLGENLATCH

Does not compare all latches as generic latches. This is the default. This option has no effect when using -NOGENLATCH. Note: The input cones compared are set cones, reset cones, clock cones, and data cones.

-ALLGENLATCH

Compares all latches as generic latches. This option has no effect when using -NOGENLATCH.

-VERIFY_Disabled_ports Compares data cones even if their clocks are disabled. By default, a data cone will not be compared if its corresponding clock port is tied to a constant (for DFFs) or to zero (for latches). Note: You should use this command option before running the first COMPARE command. If you use this after running COMPARE, this option has no effect.

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SET CPU LIMIT SET CPu Limit <-Days | -Hours | -Minutes> [-NOKill] [-WALLTIME] (Setup / LEC Mode)

Specifies the time limit for the compare effort. The system default is 525,600 minutes. Set the time limit for minutes, hours, or days. Use the REPORT ENVIRONMENT command to display the setting for the CPU time limit. Note: When the Conformal software reaches the specified CPU limit, it stops all processing and exits.

Parameters integer

Specifies a positive integer for the CPU time limit.

-Days

Specifies that the CPU time limit refers to days.

-Hours

Specifies that the CPU time limit refers to hours.

-Minutes

Specifies that the CPU time limit refers to minutes.

-NOKill

Prevents the software from exiting. This returns the command prompt.

-WALLTIME

Specifies that the time limit is in real clock time.

Example The following commands show an example of using the SET CPU LIMIT command with and without the -WALLTIME option. The time is 11:00 am and you start two Conformal sessions on the same machine, executing the same dofile, that will run more than 20 minutes. You set the time limit for session 1 in real clock time with the following command: set cpu limit 10 -minutes -walltime

You set the time for session 2 at the same limit but without using the real clock time with the following command: set cpu limit 10 -minutes.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference At 11:10, session 1 will terminate because the real clock time has elapsed 10 minutes. However, session 2 might not terminate because the real time it consumed during this 10 minutes is less than 10 minutes if some of the time is consumed by other processes running on the machine.


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SET DATAPATH OPTION SET DAtapath Option [-MERGE |-NOMERGE] [-NOAUTO |-AUTO [-MODULE [-RESOURCEFILE ]] ] [-NOSHARE | -SHARE] [-NOADDERTREE | -ADDERTREE] [-EFFort ] [-Verbose] (Setup / LEC Mode)

Specifies whether Conformal automatically analyzes data paths on switching from Setup to LEC mode and whether to apply operator merging. The results of the analysis enable Conformal Ultra to automatically resolve multipliers, operator merging, and resource sharing problems. Note: You cannot run datapath analysis without first mapping the Revised design keypoints to the Golden design keypoints.

Parameters -MERGE

Automatically applies the operator merging technique when switching from Setup to LEC mode. This is the default.

-NOMERGE

Does not automatically apply the operator merging technique when switching from Setup to LEC mode.

-NOAUTO

Does not automatically analyze data paths when switching from Setup to LEC mode. This is the default.

-AUTO

Automatically analyzes data paths when switching from Setup to LEC mode. This also performs additional carry-save adder (CSA) analysis.

-MODULE

Automatically applies analysis on the datapath modules in the Revised design netlist.

-RESOURCEFILE Specifies the resource filename to analyze the datapath modules. -NOSHARE

Does not apply the resource sharing technique. This is the default.

-SHARE

Analyzes the design for datapath resource sharing.

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-NOADDERTREE

Does not automatically add parentheses to the input operands of adder trees when switching from Setup to LEC mode. This is the default.

-ADDERTREE

Automatically adds parentheses to the input operands of adder trees when switching from Setup to LEC mode.

-EFFort Specifies the effort level. Choose MEDium (the default), or HIgh to help provide better analysis of some multipliers, but can increase the analysis runtime. -Verbose


Examples ■

The following command applies module-based datapath analysis followed by the operator-level datapath analysis when switching from Setup to LEC mode: set datapath option -auto -module -verbose set system mode lec

■

The following command applies operator-level datapath analysis when switching from Setup to LEC mode: set datapath option -auto set system mode lec

Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT DATAPATH OPTION REPORT MULTIPLIER OPTION SET MULTIPLIER OPTION SET FLATTEN MODEL

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SET DIRECTIVE SET DIrective [[synthesis | vendor_name] directives] [-file ] (Setup Mode)

Specifies whether to enable or disable the effects of the specified synthesis directives when reading in a Verilog or VHDL file. If you enter this command and do not specify any directives, this command enables (or disables) all of the directive effects. The system default enables all directives. (Thus, if you want Conformal to enable all directives, no action is necessary on your part.) Execute this command before READ LIBRARY and READ DESIGN. For each disabled directive used in the HDL source code, Conformal responds as follows: ■

If the directive is supported but disabled, Conformal returns a message stating the directive is disabled.

■

If the directive is unsupported and disabled, Conformal returns a message stating that the directive is unsupported.

Conformal Directives The following information includes short descriptions and examples of four supported Conformal directives. ■

clock_hold “…” This directive instructs Conformal to synthesize latch arrays so that the array address is placed into the clock cone of the synthesized logic. Example: // conformal clock_hold “memory_array” always @(clk or we or addr or din) begin if (clk && we) memory_array[addr] = din; end

Without this directive, the above always process results in a latch array with both clk and we in the clock logic. And addr is used to mux between din and the old state. Thus, with this directive, we move the addr into the clock logic of the array. This directive is useful for register files and memory arrays.

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infer_latch This directive instructs Conformal to use a D-latch instead of a DFF when there is an always statement with an edge-triggered clock. The default is to use a DFF. Example: always @(posedge clk) begin // conformal infer_latch qstate = din; end

In this example, the infer_latch directive tells Conformal to synthesize a latch enabled with a high clock (rather than a D flip-flop with a positive edge triggered clock) for the always process. It is similar to writing the following RTL: always @(clk or din) begin if (clk) qstate = din; end ■

multi_port This directive instructs Conformal to synthesize a multi-port latch or register when multiple, simultaneous definitions exist for the same state variable. Example: always @(clk1 or din1) if (clk1) qstate = din1; always @(clk2 or din2) if (clk2) qstate = din2; … always @(clkn or dinn) if (clkn) qstate = dinn;

This sample case results in n number of latches, each with separate clocks and data inputs and all outputs wired together. However, the implementation of a multiport cannot be compared with an n port latch. Thus, you would use the // conformal multiport “qstate” directive to synthesize an n port latch with one Q output. Internally, a primitive UDP model represents the valid function. If a simultaneous write occurs on multiple ports and the input data on those ports is not equal, the state becomes an X. This directive is generally used for multi-port memory arrays and custom designs. ■

mem_rowselect This directive supersedes the clock_hold directive. It guides memory array RTL model synthesis so that it includes the same logic in the clock and data cones as in the implementation. Thus, Conformal can complete equivalence checking. Example: // conformal mem_rowselect “mem clk addr[7:5] addr[2:0]”

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Encounter Conformal Equivalence Checking Reference Manual Command Reference always @(clk or we or addr or din) begin if (clk && we) mem[addr] = din; end

The synthesized result creates a row decoder with address bits 7, 6, 5, and 2, 1, 0, and used clk as an enable. The addr bits 3 and 4 are used to column multiplex input data when we is active. However, when we is not active or a column is selected, the array data input is in a high Z state, which is representative of memory implementation. ■

one_hot/one_cold/zero_one_hot/zero_one_cold "..." This directive instructs Conformal to adds one-hot constraints on specified net path. The one_hot and zero_one_hot constraints let only zero or one net be at a 1-state and the remaining nets be at a 0-state. The one_cold and zero_one_cold constraints let only zero or one net be at a 0-state, and the remaining nets be at a 1-state. In the following example, only zero or one of net ’aa’ and ’bb’ is constrainted to be 1-state, and the other one is constrainted to be at 0-state: // pragma one_hot "aa, bb"

Note: The wildcard (*) represents any zero or more characters in filenames.

Parameters ON

Enables the specified directives. (The initial system default enables all directives.)

OFf

Disables the specified directives. If you do not specify directives, all directives are disabled.

synthesis

Enables (or disable) the specified Synplicity synthesis directives.

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vendor_name

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Enables (or disable) the specified synthesis directives when they are used with the specified vendor_name prefix. Supported vendor_names are listed below: ■

cadence

■

synopsys

■

ambit

■

quickturn

■

verplex

■

conformal

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directives

-File file_name*

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Enables (or disables) the specified synthesis directives. If you do not specify any directives, all directives are enabled (or disabled), accordingly. Supported directives are listed below. ■

assertion_library

■

black_box

■

built_in

■

clock_hold

■

compile_off

■

compile_on

■

dc_script_begin

■

dc_script_end

■

divider

■

enum

■

full_case

■

infer_latch

■

mem_rowselect

■

multi_port

■

multiplier

■

operand

■

parallel_case

■

pragma

■

state_vector

■

synthesis_off

■

synthesis_on

■

template

■

translate_off

■

translate_on

Enables (or disables) a list of directives that are specified in a RTL file. This option supports wildcards. 412

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Examples Enabling Directives The Conformal, Synopsys, and Ambit directives are enabled by default. The Quickturn directives are disabled by default. To recognize the Quickturn directives, you must first turn on all of the directives for Quickturn using the following command: set directive on quickturn

Enabling One Directive When you employ the SET DIRECTIVE command and you do not specify a directive, the command applies to all directives. In the following example, the objective is to enable only the parallel_case directive. To do so, first disable all directives, then enable the specified directive (parallel_case). //disable all directives set directive off //enable parallel_case set directive on parallel_case

Disabling All Directives for One Vendor In the following example, the objective is to disable all Synopsys directives (synopsys translate_off, synopsys translate_on, synopsys full_case…). //disable all synopsys directives set directive off synopsys

Disabling Specified Directives for One Vendor In the following example, the objective is to disable synopsys translate_off and synopsys translate_on. This command has no effect on conformal translate_off and conformal translate_on. //disable synopsys translate_off and synopsys translate_on set directive off synopsys translate_off translate_on

Enabling a List of Directives from an RTL File In the following examples, we have 2 RTL files: test.v and test1.v. ■

In the following command, the synthesis directive parallel_case is on (enabled) in file test.v:

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Encounter Conformal Equivalence Checking Reference Manual Command Reference set directive on parallel_case -file test.v ■

In the following command, the synthesis directive parallel_case is on (enabled) in file test.v and test1.v: set directive on parallel_case -file *.v


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SET DOFILE ABORT SET DOfile Abort (Setup / LEC Mode)

Specifies how Conformal handles the dofile when an error message occurs. ■

If the dofile abort handling is set to On, the dofile terminates when an error message occurs. This is the default.

■

If the dofile abort handling is set to Off, the dofile continues even if an error message occurs.

■

If the dofile abort handling is set to Exit, the session exits when an error message occurs.

Parameters ON

Terminates the dofile if an error message occurs. This is the default.

OFf

Continues the dofile even if an error message occurs.

Exit

Exits the session if an error message occurs.

Related Commands BREAK CONTINUE DOFILE

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SET EXIT CODE SET EXit Code [-CLEAR] [-VERBOSE] [ | -INTERNAL_ERROR | -NOINTERNAL_ERROR] [ | -COMMAND_ERROR | -NOCOMMAND_ERROR] (Setup / LEC Mode)

Controls and displays the exit code for the Conformal session. This command is useful when running a complex flow, such as hierarchical comparison and iterative comparison.

Parameters -CLEAR

Clears the exit code to only reflect most current running status.

-VERBOSE

Displays a table listing the status codes.

-INTERNAL_ERROR

Sets the internal error bit.

-NOINTERNAL_ERROR

Clears the internal error bit.

-COMMAND_ERROR

Sets the command error bit.

-NOCOMMAND_ERROR

Clears the command error bit.

Examples ■

The following command displays current exit code: set exit code

■

If a failing comparison was followed by a passing comparison (after fixing some constraints), bit 4 in the exit code is still non-zero. However, the following command clears the exit code and displays a table listing the status codes and decimal exit code: set exit code -clear -verbose

■

The following command set command error bit to 1: set exit code -command_error

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SET FLATTEN MODEL SET FLatten Model [-Map | -NOMap] [-NOPin_keep | -PIN_keep] [-NOLATCH_Fold | -LATCH_Fold] [-NOLATCH_Transparent | -LATCH_Transparent] [-NOLATCH_FOLD_Master | -LATCH_FOLD_Master] [-NOLATCH_MERGE_PORT | -LATCH_MERGE_PORT] [-NOALL_SEQ_Merge | -ALL_SEQ_Merge] [-NOSEQ_Merge | -SEQ_Merge] [-NOALL_INV_SEQ_Merge | -ALL_INV_SEQ_Merge] [-NOSEQ_Redundant | -SEQ_Redundant] [-NOLIB_SEQ_Redundant | -LIB_SEQ_Redundant] [-NOSEQ_SIMPLIFY_Clock | -SEQ_SIMPLIFY_Clock] [-NOSEQ_Constant | -SEQ_Constant] [-NOGATED_Clock | -GATED_Clock] [-DFF_TO_DLAT_ZERO | -NODFF_TO_DLAT_ZERO] [-DFF_TO_DLAT_FEEDBACK | -NODFF_TO_DLAT_FEEDBACK] [-NOLOOP_AS_DLAT | -LOOP_AS_DLAT] [-SEQ_CONSTANT_FEEDBACK | -NOSEQ_CONSTANT_FEEDBACK] [-SEQ_CONSTANT_X_TO < 0 | 1 >] [-AUTO_MODELING | -NOAUTO_MODELING] [-OUTPUT_Z | -NOOUTPUT_Z] [-NOBBOX_MERGE | -BBOX_MERGE] [-SHOW_MESSAGE_NAME] [-NOKEEP_IGnored_PO | -KEEP_IGnored_PO] [-CUT_REMOVE REDUNDANT] [-NOECO | -ECO] (Setup Mode)

Specifies certain conditions for the flattened model. Refer to the arguments table for a complete list of options and their effects. Use the REPORT ENVIRONMENT command to display the settings for the flattened model, or you can run this command without any options (in either Setup or LEC mode) to report a complete list of flattened modeling options.

Parameters -Map

Does automatic key point mapping. This is the default.

-NOMap

Skips the automatic key point mapping when the system mode is changed from Setup to LEC.

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-NOPin_keep

In an effort to reduce memory use, Conformal does not keep certain gate pins. This is the default.

-PIN_keep

Keeps all gate pin information for gate reporting. Use this option when reporting gate information at the design level. It will increase memory use.

-NOLatch_fold

Does not fold a master-slave latch into a D flip-flop. This is the default.

-Latch_fold

Folds a master-slave latch into a D flip-flop.

-NOLATCH_Transparent

Does not treat latches that are always enabled as transparent. This is the default.

-LATCH_Transparent

Converts D-Latches into buffers if the clock ports of the D-latches are always enabled.

-NOLATCH_FOLD_Master

Does not convert two latches in an LSSD format into a DFF gate when the reset signal is connected only to the master.

-LATCH_FOLD_Master

Converts two latches in an LSSD format into a DFF gate when the reset signal is connected only to the master.

-NOLATCH_Merge_port

Does not collapse multi-port latches into a single-port latch. This is the default.

-LATCH_Merge_port

Collapses multi-port latches into a single-port latch.

-NOALL_SEQ_Merge

Does not merge state elements that are functionally equivalent. This is the default.

-ALL_SEQ_Merge

Merges state elements that are functionally equivalent.

-NOSEQ_Merge

Does not merge sequential elements in the clock cone of a DFF or D-latch. This is the default.

-SEQ_Merge

Merges common groups of sequential elements into one sequential element in the clock cone of a DFF or D-latch.

-NOALL_INV_SEQ_Merge

Does not merge state elements that are functionally inverted. This is the default.

-ALL_INV_SEQ_Merge

Merges state elements that are functionally inverted.

-NOSEQ_Redundant

Does not remove redundant fan-out gates from DFFs and DLATs. This is the default.

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-SEQ_Redundant

Removes redundant fan-out gates from DFFs and D-Latches.

-NOLIB_SEQ_Redundant

Retains redundant fan-out gates from DFFs and DLATs in the Library. This is the default.

-LIB_SEQ_Redundant

Removes redundant fan-out gates from DFFs and DLATs in the Library.

-NOSEQ_SIMPLIFY_Clock

Does not fold master and slave latches when there is a redundant interaction between the clock and reset signals. This is the default.

-SEQ_SIMPLIFY_Clock

Folds master and slave latches when there is a redundant interaction between the clock and reset signals.

-NOSEQ_Constant

Does not propagate constant data through latches and registers. This is the default.

-SEQ_Constant

Propagates constant data through latches and registers.

-NOGATED_Clock

Does not remodel gated-clock sequential instances. This is the default.

-GATED_Clock

Remodels the gated-clock logic of the clock port of a DFF. If the clock pin cannot be automatically determined, use the ADD CLOCK command to define the clock pin.

-DFF_TO_DLAT_ZERO

Converts a DFF to a DLAT if the clock port is zero. This is the default.

-NODFF_TO_DLAT_ZERO

Does not convert a DFF to a DLAT if the clock port is zero.

-DFF_TO_DLAT_FEEDBACK

Converts a DFF to a DLAT if the Q output feeds back to the D input. This is the default.

-NODFF_TO_DLAT_FEEDBACK

Does not convert a DFF to a DLAT if the Q output has feedbacks to the D input.

-NOLOOP_AS_DLAT

Does not use a DLAT to model a combinational loop. This is the default.

-LOOP_AS_DLAT

Uses a DLAT to model a combinational loop.

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-SEQ_CONSTANT_FEEDBACK

Remodels registers that also have feedback to constants. Use this option with -seq_constant. This is the default.

-NOSEQ_CONSTANT_FEEDBACK

Does not remodel registers that also have feedback to constants. Use this option with -seq_constant.

-SEQ_CONSTANT_X_TO

Optimizes a flop to a constant value (either zero or one) when the flop is always in a don’t care (X) state. Use this with the -seq_constant switch. 0: Optimizes a flop to a constant zero. 1: Optimizes a flop to a constant one.

-AUTO_MODELING

Enables selective modeling for designs that can be mapped mostly by name. This option applies only to sequential constants. This is the default.

-NOAUTO_MODELING

Disables the auto modeling feature.

-OUTPUT_Z

Checks for floating conditions at top-level output ports and inputs to blackboxes. This is the default.

-NOOUTPUT_Z

Does not check for floating conditions at top-level output ports and inputs to blackboxes.

-NOBBOX_MERGE

Does not perform automatic blackbox merging. This is the default.

-BBOX_MERGE

Performs automatic blackbox merging.

-SHOW_MESSAGE_NAME

Prints message names to the log as they occur.

-NOKEEP_IGnored_PO

Does not retain the ignored primary outputs (added with the ADD IGNORED OUTPUTS command) in the flattened netlist. This is the default.

-KEEP_IGnored_PO

Retains the ignored primary outputs (added with the ADD IGNORED OUTPUTS command) in the flattened netlist. These ignored primary outputs appear as unreachable unmapped points in the design.

-CUT_REMOVE_REDUNDANT

Removes as many redundant cuts as possible. Use this option if you suspect that the software inserted more cuts than necessary.

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-NOECO

Does not preserve extra circuit information for model flattening. This is the default.

-ECO

Preserves extra circuit information during model flattening for subsequent ANALYZE ECO command runs in the Conformal ECO flow.

Examples set set set set set set set set set set set

flatten flatten flatten flatten flatten flatten flatten flatten flatten flatten flatten

model model model model model model model model model model model

-latch_fold -pin -latch_transparent -nomap -seq_merge -nodff_to_dlat_zero -seq_constant -noseq_constant_feedback -gated_clock -seq_redundant -all_seq_merge -nodff_to_dlat_feedback

Related Commands READ MAPPED POINTS REMODEL REPORT ENVIRONMENT REPORT MESSAGES SET GATE REPORT

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SET FPGA TECHNOLOGY SET FPga Technology [NONE | VIRTEX | VIRTEX2] (Setup Mode)

Note: This command is an FPGA command. Turns on FPGA-specific processing. It is included in the fpgaR2G.do dofile.

Parameters NONE

Does not turn on any FPGA-specific processing. This is the default.

VIRTEX

Turns on the Xilinx Virtex processing.

VIRTEX2

Turns on Virtex2 processing.

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SET GATE REPORT SET GAte Report [-PRImitive | -DESign] [-DYNamic | -NODYNamic] [-FUNction | -STRucture] (Setup / LEC Mode)

Specifies the detail level of gate reports in the Conformal gate information display. Gate report features include the following: ■

Returns information at the design or primitive level

■

Displays the dynamic constraints

■

Displays the fanin cone of the zero/one gates

By default, this command reports gate information at the primitive level, displays the dynamic constraints, and does not display the fanin cone of the zero or one gates. Use the REPORT ENVIRONMENT command to display the gate report level settings. Note: If the gate report is set to “Design”, you must use the SET FLATTEN MODEL command with the -pin_keep option in the Setup system mode. The gate information is reported in the LEC system mode.

Parameters -PRImitive

Displays the gate report information at the primitive level. This is the default.

-DESign

Displays the gate report information at the design level.

-DYNamic

Displays the dynamic constraints in the gate report information. This is the default.

-NODYNamic

Does not display the dynamic constraints in the gate report information.

-FUNction

Does not display the fanin cone of the zero/one gates in the gate report information. This is the default.

-STRucture

Displays the fanin cone of the zero/one gates in the gate report information.

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Related Commands REPORT ENVIRONMENT REPORT GATE SET FLATTEN MODEL

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SET GUI SET GUi [ON | OFf] (Setup / LEC Mode)

Switches Conformal to the GUI mode from the non-GUI mode or to the non-GUI mode from the GUI mode.

Parameters ON

Switches to the GUI mode. This option is the initial system default.

OFf

Switches to the non-GUI mode.

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SET HDL DIAGNOSIS SET HDl Diagnosis (Setup Mode)

Enables the debugging features before reading design and libraries. By default, the source code debugging features (such as tracing drivers and loads) are off. Execute this command before READ LIBRARY and READ DESIGN.

Parameters OFf

Disables the Source Code Manager’s debugging features. This option is the initial system default.

ON

Enables the Source Code Manager’s debugging features.

Related Commands DIAGNOSE REPORT TEST VECTOR

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SET HDL OPTION SET HDl Option [-VERILOG_OUTOFBOUNDWrite ] [-VHDL_OUTOFBOUNDWrite ] [-VERILOG_OUTOFBOUNDRead ] [-VHDL_OUTOFBOUNDRead ] [-VERILOG_TRIMINDex ] [-VHDL_TRIMINDex ] (Setup Mode)

Controls the interpretation of some RTL semantics.

Parameters -VERILOG_OUTOFBOUNDWrite Controls the interpretation of Verilog bit (or part)-select of vector typed variable/signal when index is out of the defined index range. Noeffect specifies that out-of-bound writing will have no effect. This is the default. X specifies that when there is out-of-bound writing, the related part of the variable/signal is assigned value ’x’. -VHDL_OUTOFBOUNDWrite Controls the interpretation of VHDL bit (or part)-select of vector typed variable/signal when index is out of the defined index range. X specifies that when there is out-of-bound writing, the related part of the variable/signal is assigned value ’x’. This is the default. Noeffect specifies that out-of-bound writing will have no effect.

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-VERILOG_OUTOFBOUNDRead Controls the interpretation of Verilog bit (or part)-select of vector typed variable/signal when index is out of the defined index range. PARTIAL_X specifies that out-of-bound reading will have values from the valid index locations of the vector, and will have ’x’ value from the invalid (i.e. out of bound) locations of the vector. This is the default. ALL_X specifies that when there is out-of-bound reading, the selected portion of the vector will be treated as all ’x’ values. -VHDL_OUTOFBOUNDRead Controls the interpretation of VHDL bit (or part)-select of vector typed variable/signal when index is out of the defined index range. ALL_X specifies that when there is out-of-bound reading, the selected portion of the vector will be treated as all ’x’ values. This is the default. PARTIAL_X specifies that out-of-bound reading will have values from the valid index locations of the vector, and will have ’x’ value from the invalid (i.e. out of bound) locations of the vector. -VERILOG_TRIMINDex ON controls to trim the index to necessary bits for the Verilog files. OFF is the command default. Note: This option might be used to verify implementations in which indexes are intentionally trimmed. -VHDL_TRIMINDex ON controls to trim the index to necessary bits for the VHDL files. OFF is the command default. Note: This option might be used to verify implementations in which indexes are intentionally trimmed.

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Examples The following examples use the Verilog language to show how to control index out of bound handling. You can use similar VHDL command options to control the interpretations for the VHDL language designs. In the following RTL-1 example, the index range of variable mem is 0 to 2. RTL-1 wire a; reg [2:0] index; reg [2:0] mem; always @(*) mem[index] = a;

If index is greater than 2, it is out of the index range. Some synthesis tools might intentionally interpret the RTL the same as with the following RTL-2 example: RTL-2 wire a; reg[2:0] index; reg[2:0] mem; always @(*) mem[index[1:0]] = a;

But with simulation, RTL-1 and RTL-2 behave differently. With the Conformal Equivalence Checking software, when running the command: set hdl option -verilog_outofboundwrite x

then ■

index=0 : mem[0] is assigned to the value of a

■


■


■

index=3,4,5,6,7 : mem[0], mem[1], and mem[2]are assigned to the value of 1’bx.

This interpretation assumes that out-of-bound writing will not happen, and consequently ignores the behavior difference when index is greater than 2.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference When running the command: set hdl option -verilog_outofboundwrite noeffect

then ■


■


■


■

index=3,4,5,6,7 : mem[0], mem[1], and mem[2]will not be affected with their current value.

Based on this interpretation, RTL-1 and RTL-2 are considered functional non-equivalent, and consequently the implementation from RTL-2 will be non-equivalent to RTL-1. Using the same RTL-1 and RTL-2 examples, when running the command: set hdl option -verilog_trimindex on

The Conformal Equivalence Checking software will interpret RTL-1 as RTL-2 by ignoring index[2] in the expression mem[index] (RTL-1). With the -verilog_trimindex on option, RTL-1 and RTL-2 are considered equivalent.

Related Commands ELABORATE DESIGN READ DESIGN

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SET IMPLEMENTATION SET IMPlementation [-Both | -Golden | -Revised] (Setup Mode)

Specifies the multiplier and divider implementations in the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. The types of multipliers supported are: ■

Carry Save Adder (CSA)

■

Ripple Carry Adder (RCA)

■

Booth Encoded-Wallace tree (WALL)

■

Non-Booth Encoded-Wallace tree (NBW)

■

Brent-Kung Adder (BKA)

Default Multiplier Implementation Is Automatically Determined By default, Conformal automatically determines the multiplier implementation as follows: If a_width + b_width <42, Conformal chooses NBW. If a_width + b_width >=42, Conformal chooses WALL. The -auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify -csa. The types of dividers supported are: ■

Ripple Borrow (RPL)

■

Borrow Look-Ahead

■

Carry Look-Ahead

■

Carry Look-Ahead, 2-Way

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Encounter Conformal Equivalence Checking Reference Manual Command Reference Required Options With this command, you must include either the multiplier or divider option; however, Conformal permits both options, as shown below: set implementation multiplier -csa divider -bla

Specifying Multiplier Implementations with Directives Specify the multiplier implementation with a Synopsys or Conformal directive in the design. (See the Set Implementation examples below and in the Examples section of this command.) ■

Synopsys Directive: // synopsys dc_script_begin // set_implementation [instance_name] // synopsys dc_script_end

■

Conformal Directive: // conformal multiplier

Note: Use either directive for multipliers specified with operational assignments. For DesignWare instances, use only the Synopsys directive along with the instance name.

Parameters MULtiplier

By default, Conformal automatically determines the multiplier implementation as follows: If a_width + b_width < = 52, Conformal chooses NBW. If a_width + b_width > 52, Conformal chooses WALL. The multiplier type is one of the following:

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-AUTO

The -auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify -csa. This is the default.

-CSA

Carry Save Adder

-WALL

Booth Encoded, Wallace tree

-RCA

Ripple Carry Adder

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DIVider

-NBW

Non-Booth Encoded, Wallace tree

-BKA

Brent-Kung Adder

The divider type is one of the following: -RPL

Ripple Borrow, which is the initial default

-BLA

Borrow Look-Ahead

-CLA

Carry Look-Ahead

-CLA2

Carry Look-Ahead, 2-Way

The following options specify how to treat over signed division overflow, which is when a minimum negative value is divided by -1. -OVERFLOW_TRUNCATE Truncates results as defined by twos-complement arithmetic. This is the default. -OVERFLOW_SATURATE Saturates results to the largest positive value. -OVERFLOW_DONTCARE Treats overflow results as don’t cares. DIVider can be inferred from either DW_div instantation or RTL arithmetic operation (for example, ‘/’ in Verilog). The following options specify the divider class for the preceeding settings. -ALL_div

Specifies that dividers are inferred from both RTL and DW. This is the default.

-RTL_div

Specifies that dividers are only inferred from RTL operation.

-DW_div

Specifies that dividers are only inferred from DW_div instantiation.

-Both

Specifies the implementation type for both the Golden and Revised designs. This is the default.

-Golden

Specifies the implementation type for the Golden design.

-Revised

Specifies the implementation type for the Revised design.

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Examples Synopsys Directive The following examples illustrate Conformal-supported use of the Synopsys directive: // synopsys dc_script_begin // set_implementation wall // synopsys dc_script_end assign out = in1 * in2; // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out)); // synopsys dc_script_begin // set_implementation wall cla2 U1 // synopsys dc_script_end DW_div #(A_width, B_width, TC_mode, REM_mode) U1 (...);

Conformal Directive The following example illustrates the Conformal directive. Note: The directive applies to only the statement on the following line. In this example, it does not apply to assign out2…: // conformal multiplier wall assign out1 = in1 * in2; assign out2 = in3 * in4;


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SET LOG FILE SET LOg File [ [-Replace | -Append] [-PROGRESS | -NOPROGRESS] [-NOBACkup]] (Setup / LEC Mode)

Writes the transcript to a specified file. The commands and any output information write to this file. As you review the file, identify commands by the keyword: //Command:

When you want the Conformal software to stop writing to the log file, enter the command without any options. Note: If the filename you specify already exists, you must use either the -replace or -append option. If you do not include an option, the Conformal software generates an error message that the file exists. If you receive this message, reenter the command with either a new filename or the appropriate option. If the filename is not writable, the software writes it to the /tmp directory. If you are writing the transcript to a file, you might want to turn off the screen transcript display with the SET SCREEN DISPLAY command. (If you do not specify otherwise, the transcript prints to the screen.) To store log files based on the software version, use the LEC_VERSION environment variable. For example: set log file lec.$LEC_VERSION.log -replace

To verify the current log file setting, use the REPORT ENVIRONMENT command.

Parameters

Writes the transcript run to this file.

-Replace

If the specified filename already exists, overwrites the contents of that file.

-Append

Appends the transcript run to the end of the specified filename.

-PROGRESS

Writes the percentage completion progress to the log file. This is the default.

-NOPROGRESS

Does not write the percentage completion progress to the log file.

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-NOBACkup

Does not create a backup file. Note: If you do not specify this option, it will create a backup file when you replace or append a file.

Related Commands REPORT ENVIRONMENT REPORT COMMAND PROFILE SET COMMAND PROFILE SET SCREEN DISPLAY

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SET LOWPOWER OPTION SET LOwpower Option [-NOauto | -Auto | [-Retention_cells_check] [-Isolation_cells_check] [-Level_shifter_cells_check] [-POWER_domain_check [-GOLDen_power_domain [CPF | PHYsical | HYbrid]] [-REVised_power_domain [PHYsical | CPF | HYbrid]] ] [-MERge] (Setup Mode)

Note: This is a Conformal Low Power command. Enables the low power check for different types of low power cells. Low power checking includes either the technology mapping check or the equivalence check (EC), or both, depending on the low power cell type. For retention-register cells, only the technology mapping check is performed. For isolation cells and level-shifter cells, both technology mapping check and EC is performed. For more information on these low power checks and cell types, see CHECK LOWPOWER CELLS.

Parameters -NOauto

Does not automatically enable the low power check. This is the default.

-Auto

Enables the low power check for the isolation cells, level-shifter cells, and state retention cells.

-Retention_cells_check Enables the low power check for state retention cells only. -Isolation_cells_check Enables the low power check for isolation cells only. -Level_shifter_cells_check Enables the low power check for level-shifter cells only. -POWER_domain_check Enables the power domain consistency check for the sequential compare points.

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-GOLDen_power_domain [CPF | PHYsical | HYbrid] Specifies the mechanism for obtaining the power domains in the Golden design to do the power domain consistency check. ■

CPF—obtains the power domain from the CPF specification. This is default for the Golden design.

■

PHYsical—extracts the power domains by tracing the power and the ground pins.

■

HYbrid—extracts the power domains by tracing the power and the ground pins. If the power domain cannot be obtained by tracing the power and ground pins, the software obtains the power domain from the CPF specification.

-REVised_power_domain [PHYsical | CPF | HYbrid] Specifies the mechanism for obtaining the power domains in the Revised design to do the power domain consistency check.

-MERge

■

PHYsical—extracts the power domains by tracing the power and the ground pins. This is default for the Revised design.

■

CPF—obtains the power domain from the CPF specification.

■

HYbrid—extracts the power domains by tracing the power and the ground pins. If the power domain cannot be obtained by tracing the power and ground pins, the software obtains the power domain from the CPF specification.

Merges the equivalent outputs of the low power cells. This is enabled only for isolation and level-shifter cells.

Examples The following commands perform low power checking that includes both the technology mapping check and the equivalence check: set lowpower option -auto set lowpower option -retention -level_shifter

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Related Commands ADD LOWPOWER CELLS CHECK LOWPOWER CELLS DELETE LOWPOWER CELLS REPORT LOWPOWER DATA REPORT LOWPOWER DATA

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SET MAPPING METHOD SET MApping Method < [-NAme < First | Guide | Only> |-NOName] [-NOPhase | -Phase] [-NOSensitive | -Sensitive]> [-NOUNREACH | -UNREACH] [-REPORT_UNREACH | -NOREPORT_UNREACH] [-NAME_EFFORT ] [-NONETS | -NETS] [-BBOX_NAme_match | -NOBBOX_NAme_match] [-REPORT_SUMMARY_SHOW_ZERO_COUNT] [-TIMEOUT_minutes ] [-PHASEMAPMODEL] (Setup / LEC Mode)

Specifies the mapping method, phase, case sensitivity, and handling for unreachable points and blackboxes when Conformal maps the key points. With the -name option, paths of the gates indicate some type of starting point to map key points. The system default is name first. This default lets Conformal first map key points with the same paths, then map the remaining unresolved key points with a mapping algorithm. All remaining unresolved key points become unmapped points. Use the REPORT ENVIRONMENT command to display the setting of the mapping method and phase.

Parameters -NAme

-NOName

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Conformal maps the key points with the paths of the gates first. Then, Conformal uses the mapping algorithm to map the rest of the key points. This option is the system default.

Guide

Conformal maps key points with a mapping algorithm first.

Only

Conformal only maps the key points based on the paths of the gates

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-NOPhase

Does not map key points with an inverted phase. This is the default. These key points are represented with the symbol “+”. Comparison results are either equivalent or nonequivalent.

-Phase

Maps key points with an inverted phase. These key points are represented with the symbol “-”. Comparison results are either inverted-equivalent or nonequivalent.

-NOSensitive

Specifies that key point names are not case sensitive. This is the default.

-Sensitive

Specifies that key point names are case sensitive.

-NOUNREACH

Does not map unreachable key points. Unreachable key points are those that don’t eventually affect the PO of the design. This is the default.

-UNREACH

Maps unreachable key points. Unreachable key points are those that don’t eventually affect the PO of the design.

-REPORT_UNREACH

Reports unreachable key points. This is the default.

-NOREPORT_UNREACH

Does not report unreachable key points.

-NAME_EFFORT

Uses the specified amount of effort for key point mapping. This option eliminates the need for simple renaming rules such as: add renaming rule R1 “reg\[%d\]” “reg(@1)” -golden, which maps the following Golden and Revised design DFFs: Golden: DFF A/B/C_reg[5] Revised: DFF A/B/C_reg(5) This option applies to only DFFs and DLATs. HI

This option is the system default level. It eliminates the need for simple renaming rules.

LOW

Uses low effort for key point mapping

-NONETS

Does not map according to net names. This is the default.

-NETS

Maps key points according to net names.

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-BBOX_NAme_match

Maps blackboxes only if both the module names and instance names match. This is the default.

-NOBBOX_NAme_match

Maps blackboxes if instance names match.

-REPORT_SUMMARY_SHOW_ZERO_COUNT Specifies that the summary will be reported with ZERO count if there is an unmapped point of the same type either in Golden or Revised design. -TIMEOUT_minutes Specifies the number of minutes for the mapping process to continue before it is interrupted. The default value is zero (0), which disables this check. -PHASEMAPMODEL

Uses the phase information provided by the ADD MAPPING MODEL command to determine the mapping phase. Use this option when there is a phase mismatched between the simulation model and the synthesis model.

Related Commands ADD MAPPED POINTS ADD RENAMING RULE DELETE MAPPED POINTS DELETE RENAMING RULE MAP KEY POINTS REPORT ENVIRONMENT REPORT MAPPED POINTS REPORT RENAMING RULE REPORT UNMAPPED POINTS

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SET MOS MODEL SET MOs Model [Spice_model_name] (LEC Mode)

Note: This is a Conformal Custom command. Specifies the MOS model names used in SPICE. You can then re-read the SPICE netlist. When reading in SPICE netlists, the parser automatically identifies transistor model names as PMOS and NMOS types. However, if you have models that were not defined using .MODEL statements, the parser identifies them as ERROR. Instead of altering your SPICE file, you can use this command. Note: You must run this command before reading in the SPICE netlist.

Parameters NMOS

Defines the model name as an N-Channel device.

PMOS

Defines the model name as a P-Channel device.

Spice_model_name

Specifies a single or list of names for which to define models. This is necessary only if you have a P-Channel model names not starting with a ‘p,’ and N-Channel model names not starting with ‘n.’

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SET MULTIPLIER IMPLEMENTATION SET MUltiplier Implementation [-Both | -Golden | -Revised] [-Verbose] (Setup Mode)

Specifies the multiplier implementation in the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN. The types of multipliers you can specify are: ■

Carry Save Adder (CSA)

■

Ripple Carry Adder (RCA)

■

Booth Encoded-Wallace tree (WALL)

■

Non-Booth Encoded-Wallace tree (NBW) multipliers

■

Brent-Kung Adder (BKA)

The CSA multiplier implementation is the default. An alternate method for specifying the multiplier implementation is to use a Synopsys or Conformal directive in the design. See the following set multiplier implementation examples for using these directives and those shown in the “Examples” section below. Synopsys Directive: // synopsys dc_script_begin // set_implementation [instance_name] // synopsys dc_script_end

Conformal Directive: // conformal multiplier

Note: Use either directive for multipliers specified with operational assignments. However, for DesignWare instances, use only the Synopsys directive along with the instance name.

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Parameters AUTO

The system default for Conformal is that it automatically determines the multiplier implementation as follows: If a_width + b_width < = 52, Conformal chooses NBW. If a_width + b_width >

52, Conformal chooses WALL.

The auto default setting is best suited when you are using Synopsys Design Compiler with DesignWare Foundation. If you are not using DesignWare Foundation, it is probably best to specify csa. CSA

Specifies that the multiplier type is a Carry Save Adder (CSA) multiplier.

RCA

Specifies that the multiplier type is a Ripple Carry Adder (RCA) multiplier.

WALL

Specifies that the multiplier type is a Booth Encoded, Wallace tree multiplier.

NBW

Specifies that the multiplier type is a non-Booth Encoded, Wallace tree multiplier.

BKA

Specifies that the multiplier type is a Brent-Kung Adder (BKA).

-Both

Specifies the multiplier implementation type for both the Golden and Revised designs. This is the default.

-Golden

Specifies the multiplier implementation type for the Golden design.

-Revised

Specifies the multiplier implementation type for the Revised design.

-Verbose


Examples Synopsys Directive The following two examples illustrate Conformal-supported use of the Synopsys directive: // synopsys dc_script_begin // set_implementation wall

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Encounter Conformal Equivalence Checking Reference Manual Command Reference // synopsys dc_script_end assign out = in1 * in2; // synopsys dc_script_begin // set_implementation wall U1 // synopsys dc_script_end DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out));

Conformal Directive The following example illustrates the Conformal directive. Note: The directive applies to only the statement on the following line. In this example, it does not apply to assign out2…: // conformal multiplier wall assign out1 = in1 * in2; assign out2 = in3 * in4;


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SET MULTIPLIER OPTION SET MUltiplier Option [-NOAUTO | -AUTO] [-NOCDP_INFO | -CDP_INFO] [-Verbose] (Setup Mode)

Specifies whether Conformal will automatically analyze multipliers when switching from Setup to LEC mode. Additionally, use the -cdp_info option if you want Conformal to let you know when Conformal Ultra will be helpful.

Parameters -NOAUTO

Does not automatically analyze multipliers when switching from Setup to LEC mode. This is the default.

-AUTO

Automatically analyzes multipliers when switching from Setup to LEC mode.

-NOCDP_INFO

Does not display a message when Conformal Ultra can enhance multiplier analysis. This is the default.

-CDP_INFO

Displays a message when Conformal Ultra can enhance multiplier analysis.

-Verbose


Related Commands ANALYZE DATAPATH ANALYZE MULTIPLIER REPORT DATAPATH OPTION REPORT MULTIPLIER OPTION SET DATAPATH OPTION SET FLATTEN MODEL

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SET NAMING RULE SET NAming Rule << -Hierarchical_separator> | < -Tristate> | < -REGister> | < -Inverted_pin_extension> | < -Parameter> | < -Array_delimiter> | < -Field_delimiter> | < -INStance> | < -VARiable>> [-Both | -Golden | -REvised] (Setup Mode)

Specifies the naming rules for an RTL or hierarchical design. Execute this command before READ LIBRARY and READ DESIGN. Naming rules for RTL designs specify the following: ■

Hierarchical separator

■

Tristate and register names

■

Array delimiter

Naming rules for hierarchical designs specify the hierarchical separator. ■

Use the hierarchical separator string when matching key points between the Golden and Revised designs. The hierarchical separator setting has no effect on the way key points are reported (for example, when you use the REPORT GATE command).

■

Use the register, tristate, and array delimiter strings to instruct the Verilog RTL compiler how key point names (inferred flip-flop/latch instance names) are constructed.

■

Use the following example to understand the correct use of the inverted pin extension string. Golden design: pin a Revised design: inverted pin a_BAR Type the following command: set naming rule _BAR -inverted_pin_extension -golden

■

The parameter string defines the name of the new parameterized module name when new parameters are passed. When an existing module has defined parameters and it is being instantiated with new parameters, a duplicate module is created with the specified parameter string.

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The instance strings define the way instance names are generated. Different synthesis tools use different schemes to generate instance names. To facilitate the compare process, you can use this command to instruct Conformal to generate instance names in the same way as the synthesis tool.

■

The variable strings define the way variable names are generated.

Each string for all of the settings must be enclosed in double quotes (“ ”). These double quotes can be empty. Use the REPORT ENVIRONMENT command to display the settings for the naming rules for the Golden and Revised designs.

Parameters -Hierarchical_separator A character or string that specifies the hierarchical separator. The default is “/”. -Tristate

A string that specifies the tristate naming. The default is “%s_tri”. The string must contain exactly one “%s”.

-REGister

A string that specifies the register naming. The default is “%s_reg”. The string must contain exactly one “%s”.

-Inverted_pin_extension A string that specifies the inverted pin extension. This option appends the string to the Golden or Revised pin name. Refer to the example shown in “Definition”. -Parameter A string that specifies parameter naming. The default is “_%s”. -Array_delimiter Two strings that specify the left and right array delimiter. The default is “[” and “]” for the left and right string. -Field_delimiter Two strings that specify the left and right record field delimiter for VHDL designs. The default is “[” and “]” for the left and right string. label_string forgen_string instance_string -instance

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forgen_string applies to “for generate” blocks that have a name and index, label_string applies to all of the other blocks. label_string specifies how to include the block name in the instance name, where: ■

%L specifies the block name.

■

%s specifies the current instance name.

The default setting for label_string is %s. For example, instance ins1 is inside block b1, and b2 is inside b1. If you specify a label_string of %L_%s, this command generates the instance name b1_b2_ins1. If you specify a label_string of %s[%L], this command generates the instance name ins1[b1][b2]. forgen_string specifies how to use the generated block name and loop index to form an instance name, where: ■

%L specifies the block name.

■

%s specifies the current instance name.

■

%d specifies the block index.

The default setting for forgen_string is %s_%d. For example, instance ins1 is inside block b2 with a forloop index of 3, and b2 is inside block b1 with a forloop index of 0. If you specify a forgen_string of %L[%d].%s, this command generates the instance name b1[0].b2[3].ins1. instance_string denotes how to specify the instance name, where %s specifies the current instance name. For example, your current instance name is ins1. If you specify an instance_string of %s_INS, this command replaces the instance name with ins1_INS. Note: The result of this option replaces the %s in label_string and forgen_string. The default setting for instance_string is %s. label_string forgen_string variable_string -variable

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The variable naming scheme is similar to the instance naming scheme. forgen_string applies to generated blocks that have a name and index, label_string applies to all of the other blocks. label_string specifies how to include the block name in the variable name (applies to all variables inside the “for generate” block), where: ■

%L specifies the generated block name.

■

%s specifies the current variable name.

The default setting for label_string is %s. forgen_string specifies how to use the generated block name and loop index to form a variable name, where: ■

%L specifies the generated block name.

■

%s specifies the current variable name.

■

%d specifies the generated block index.

The default setting for forgen_string is %s_%d. variable_string denotes how to specify the variable name, where %s specifies the current variable name. The default setting for variable_string is %s. -Both

The naming rule applies to both the Golden and Revised designs. This is the default.

-Golden

The naming rule applies to the Golden design alone.

-REvised

The naming rule applies to the Revised design alone.

Examples set set set set

naming naming naming naming

rule rule rule rule

“:” -hierarchical_separator -golden “register_%s” -register -revised “tristate_%s” -tristate “<” “>” -array -golden

For instance name generation, consider the following sample Verilog code: generate begin: blkA for (i=0;i<=0;i=i+1) begin: forblkB or n1(a,b,c); May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference for (j=23;j<=23;j=j+1) begin: forblkC and n2(d,e,f); end begin : blkD nor n3 (g,h,i); end end end endgenerate ■

set naming rule "%s" "%s_%d" "%s" -instance This renames instances n1, n2 and n3 as n1_0, n2_0_23, and n3_0, respectively. This is also the default setting.

■

set naming rule "%s" "%L[%d].%s" "%s_INS" -instance This renames instances n1, n2 and n3 as forblkB[0].n1_INS, forblkB[0].forblkC[23].n2_INS, and forblkB[0].n3_INS, respectively.

■

set naming rule "%L_%s" "%L[%d].%s" "%s" -instance This renames instances n1, n2 and n3 as blkA_forblkB[0].n1, blkA_forblkB[0].forblkC[23].n2, and blkA_forblkB[0].blkD_n3, respectively.

Related Commands ADD MAPPED POINTS ADD RENAMING RULE DELETE MAPPED POINTS DELETE RENAMING RULE MAP KEY POINTS READ DESIGN REPORT ENVIRONMENT REPORT MAPPED POINTS REPORT RENAMING RULE REPORT UNMAPPED POINTS TEST RENAMING RULE May 2008

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Encounter Conformal Equivalence Checking Reference Manual Command Reference WRITE HIER_COMPARE DOFILE

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SET PARALLEL OPTION SET PARAllel Option [-MAX_Remote ] [-SUBMIT_COMMAND_LINE ] [-KILL_COMMAND_LINE ] [-KEEP_DIR] [-RESERVE_LICense ] (LEC / Setup Mode)

Note: This is a Conformal Ultra command. Sets the parameters for parallel processing. This command should be run immediately before the RUN PARALLEL COMPARISON command.

Parameters -MAX_Remote

Specifies the maximum number of remotes used for performing the tasks. The number of available CPUs is considered as that number of remotes. However, this is just a recommendation. The Conformal software will check the number of available licenses and might launch remote jobs less than the number specified.

-SUBMIT_COMMAND_LINE Specifies the submit command interface. The default value is: bsub -o /_LSF.log The keywords , , and are determined by the software. You can specify with the RUN PARALLEL COMPARE command. -KILL_COMMAND_LINE

Specifies the kill command interface. The default value is bkill . The keyword is determined by the software.

-KEEP_DIR

Specifies that the directory created during parallel processing will be saved.

-RESERVE_LICense

Specifies the number of XL licenses to be reserved for other use.

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Related Commands RUN PARALLEL COMPARE

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SET RETIMING OPTION SET REtiming Option [-NOAUTO | -AUTO] [-NORETIMED_MODULE | -RETIMED_MODULE] (Setup Mode)

Specifies whether the Conformal software automatically performs retiming analysis for designs when switching from Setup to LEC mode. According to the structure of the designs, the software automatically determines whether to use forward or backward pipeline retiming, or general retiming. The results of analysis enable the software to automatically resolve retiming designs. Tip Use the ADD MODULE ATTRIBUTE command to attach the PIPELINE_Retime attribute to a module.

Parameters -NOAUTO

Does not automatically analyze retiming when switching from Setup to LEC mode. This is the default.

-AUTO

Automatically analyzes retiming when switching from Setup to LEC mode.

-NORETIMED_MODULE

Performs retiming analysis on all modules with or without the PIPELINE_Retime attribute. This is the default.

-RETIMED_MODULE

Performs retiming analysis only on modules with the PIPELINE_Retime attribute.

Related Commands ADD MODULE ATTRIBUTE ANALYZE RETIMING

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SET ROOT MODULE SET ROot Module [-Golden | -Revised | -Both] (Setup Mode)

Specifies the name of the root module for the Golden and Revised designs. The system default specifies that when the design is read, Conformal automatically assigns the root module. Thus, the SET ROOT MODULE command overrides the automatic assignment. Use the REPORT ENVIRONMENT command to display the settings for the root module for the Golden and Revised designs.


This module is the root. This assignment overrides the automatic root module assignment Conformal makes when you use the READ DESIGN command.

-Golden

Assigns the root module name for the Golden design. This is the default.

-Revised

Assigns the root module name for the Revised design.

-Both

Assigns the root module name for both the Golden and Revised designs.

Related Commands READ DESIGN REPORT ENVIRONMENT

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SET RULE FILTER SET RUle Filter <-ROOT_HIER_only> [-Golden | -Revised] (Setup Mode)

Filters out rules that occur in modules outside the root hierarchy. It is a means to remove unnecessary rule reporting and focus only on the root module's hierarchy. Use the REPORT RULE CHECK command with the -summary option to display all of the rules and their settings and occurrences.

Parameters -ROOT_HIER_only

Filters out rules that occur in modules outside the root hierarchy.

-Golden

Applies the filter to the Golden design and library. This is the default.

-Revised

Applies the filter to the Revised design and library.

Related Commands READ DESIGN READ LIBRARY REPORT RULE CHECK

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SET RULE HANDLING SET RUle Handling <[ [-Warning | -Error [-CONTinue] | -Ignore | -Note]] [[-EXCLude | -INCLude] <-MODule | -DESIGN_FILE | -LIB_FILE> ]> [ |-Design | -Library] [-Both | -Golden | -Revised] (Setup Mode)

Specifies the rule handling when reading in the designs and libraries or exclude the specified module, design file, library file, or rule from rule checking. Most rules are either warnings or notes. Execute this command before READ LIBRARY and READ DESIGN. Note: Multiple SET RULE HANDLING commands can be specified, and the effects are cumulative. Use the REPORT RULE CHECK command with the -summary option to display all of the rules and their settings and occurrences. See the Encounter Conformal Equivalence Checking User Guide for rule definitions and sample cases. Note: The wildcard (*) represents any zero or more characters in rule names.

Parameters rule_name*…

Changes rule handling for the specified rules. This supports wildcards. -Warning

The rule handling will be a warning message. This is the default.

-Error [-CONTinue] The rule handling will be an error message. With the -CONTinue option, the program will continue to run instead of erroring out.

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-Ignore

The rule handling will be ignore. See REPORT RULE CHECK to see how this severity level affects reporting.

-Note

The rule handling will be a note.

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-EXCLude | -INCLude Removes the unwanted rules. All rules will be checked by default. -EXCLude removes some rules in the specified list. -INCLude removes all rules not in the specified list.

-Design

-MODule

Excludes the specified module from the RTL Rule check.

-DESign_file

Excludes the specified design file from the RTL Rule check.

-LIB_file

Excludes the specified library file from the RTL Rule check.

name*…

Specifies the name of the module, design file, or library file.

Applies the rule handling to only the designs. If you do not specify -design or -library, Conformal applies the rule handling to both designs and libraries.

-Library

Applies the rule handling to only the libraries. If you do not specify -design or -library, Conformal applies the rule handling to both designs and libraries.

-Both

Applies the rule handling to both the Golden and Revised designs and libraries. This is the default.

-Golden

Applies the rule handling to the Golden design and library.

-Revised

Applies the rule handling to the Revised design and library.

Related Commands READ DESIGN READ LIBRARY REPORT RULE CHECK

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SET SCREEN DISPLAY SET SCreen Display (Setup / LEC Mode)

Specifies whether the transcript output is displayed on the terminal screen. Tip If the screen display is set to off, use the SET LOG FILE command to save the transcript to a file. Use the REPORT ENVIRONMENT command to display the setting for the screen display. By default, screen display is on.

Parameters ON

Displays the transcript on the terminal screen. This option is the system default.

OFf

Does not display the transcript on the terminal screen.

Related Commands REPORT ENVIRONMENT SET LOG FILE

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SET SPICE OPTION SET SPIce OPTion [-BUlk | -NOBUlk] [-BBOX | -NOBBox] [-NOADDGLOBALPINs | -ADDGLOBALPINs] [-NOKEep_InstanceX | -KEep_InstanceX] (Setup Mode)

Note: This is a Conformal Custom command. Specifies options for reading the SPICE netlist design (when running the read design -spice command).

Parameters -BULK

Identifies nets connected to PMOS bulk terminals as power and nets connected to NMOS bulk terminals as ground. This is the default.

-NOBULK

By default, Conformal Custom identifies nets connected to PMOS bulk terminals as power and nets connected to NMOS bulk terminals as ground. However, this option removes that assumption and you will need to specify power and ground pins/nets by using *.GLOBAL :P for power nets and *.GLOBAL :G for ground nets or use Conformal commands to add constraints, tied signals (pins), or net attributes.

-BBOX

Specifies that SUBCKT contains no transistors and will be treated as a blackbox. This is the default.

-NOBBox

Specifies that SUBCKT contains no transistors and will be removed along with all of its instantiations.

-NOADDGLOBALPINs

Specifies that no extra ports for GLOBAL signals will be created for SUBCKT. This is the default.

-ADDGLOBALPINs

Specifies that extra ports for GLOBAL signals will be created for SUBCKT.

-NOKEep_InstanceX

Specifies that the first character ’X’ of the name of instance will not be retained. This is the default.

-KEep_InstanceX

Specifies that the first character ’X’ of the name of instance will not be retained.

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Examples Sample Dofile: set spice option -nobulk -nobbox -addglobalpins -keep_instanceX read design -spice library.spi -golden abstract logic

Related Commands ABSTRACT LOGIC READ DESIGN

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SET STATETABLE SET STATEtable (Setup Mode)

Controls the global setting of the Synopsys Liberty state table support. Note: This command must be used before READ DESIGN and READ LIBRARY. Note: Using the READ DESIGN and READ LIBRARY command’s -STATEtable option supersedes these settings (it also supersedes the global setting).

Parameters ON

Enables support for Synopsys Liberty state tables. This option is the system default.

OFf


Related Commands READ DESIGN -statetable READ LIBRARY -statetable

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SET SYNTHESIS_OFF_COMMAND SET SYNTHESIS_OFF_Command (Setup Mode)

Specifies the pragma that is used to indicate the beginning of non-synthesizable constructs in the source code or in the generated generic netlist. Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to running this command, the default is translate_off. Note: If this command is run multiple times, only the last value is used.

Parameters string

Specifies the action. Default: translate_off synthesis_off



Related Commands SET_ATTR INPUT_PRAGMA_KEYWORD SET SYNTHESIS_ON_COMMAND

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SET SYNTHESIS_ON_COMMAND SET SYNTHESIS_ON_Command (Setup Mode)

Specifies the pragma that is used to indicate the end of non synthesizeable constructs in the source code or in the generated generic netlist. Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to running this command, the default is translate_on. Note: If this command is run multiple times, only the last value is used.

Parameters string

Specifies the action. Default: translate_on synthesis_on



Related Commands SET_ATTR INPUT_PRAGMA_KEYWORD SET SYNTHESIS_OFF_COMMAND

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SET SYSTEM MODE SET SYstem Mode (Setup / LEC / Explorer Mode)

Switches system modes between the Setup mode and the LEC mode. ■

Setup mode: While in this mode, you read in the design and set all of the necessary constraints and environment variables.

■

LEC mode: While in this mode, Conformal does the comparison and diagnosis.

■

Explorer mode: While in this mode, you can cross-link from a timing report to an RTL design or a gate-level design through a schematic viewer or source code browser. Note: This mode requires the Conformal Explorer license.

When you exit the Setup mode, Conformal attempts to map all key points in the Golden and Revised designs. A summary is given for the mapped points in the Golden and Revised designs. An additional summary is given if Conformal identifies any unmapped key points. Use the REPORT ENVIRONMENT command to display the current system mode.

Parameters Setup

Switches the system mode to Setup.

LEc

Switches the system mode to LEC.

-Map

Maps key points when entering the LEC system mode. This is the default.

-Nomap

Does not map key points when entering the LEC system mode.

-PRESERVE

Preserves the netlist modeling. You can use this option for netlists created with the REPORT TESTCASE command only.

EXPlorer

Switches the system mode to Conformal Explorer.

Related Command REPORT ENVIRONMENT REPORT TESTCASE

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SET UDP PIN SET UDp Pin ...> [-Golden | -Revised | -Both] (Setup Mode)

Sets the pin inputs of the user-defined primitive (UDP) to constant values, which are propagated into the UDP. Some inactive entries will be removed. The constant set to inputs simplifies the state table of the UDP, which will sometimes eliminate some ambiguity in the UDP description. Note: This must be used before running the READ DESIGN command.

Parameters udpname

Specifies the name of the UDP.

pin_name <0 | 1>

Specifies the name of the pin and its input value. Choose 0 or 1.

-Golden

Sets the UDP inputs in the Golden design. This is the default.

-Revised

Sets the UDP inputs in the Revised design.

-Both

Sets the UDP inputs in both the Golden and Revised designs.

Example In this example, pins in1 and in2 of the UDP named udp_1 are set to 0 and 1, respectively: set udp pin udp_1 in1 0 in2 1


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SET UNDEFINED CELL SET UNDEfined Cell [-AUTO_Assign | -NOAUTO_Assign] [-ASCEND | -NOASCEND]> [-Both | -Golden | -Revised] (Setup Mode)

Specifies how Conformal handles undefined cells it encounters when reading in the Golden and Revised designs. The system default is to give an error message if there are any undefined cells. Use the REPORT ENVIRONMENT command to display the settings for the undefined cells handling for the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN.

Parameters Error

When reading the designs, undefined cells trigger an error message. This is the default.

Black_box

When reading the designs, regards undefined cells as blackboxes. This option takes Verilog parameter values to construct the module name for the created blackbox module.

Generic_BBox

When reading the designs, regards undefined cells as blackboxes. This option ignores Verilog parameter values and uses the object bit widths to construct the module name for the created blackbox module.

-AUTO_Assign

Automatically determines and assign directions to all blackbox pins. This is the default. Note: If Conformal cannot determine the direction of a pin as “input” or “output”, it assigns I/O direction.

-NOAUTO_Assign

Assigns I/O direction to all blackbox pins. Note: You must manually reassign all pin directions according to the design.

-ASCEND

Arranges bits of bus pins in ascending order; that is, in1 (0 to 7). This is the default.

-NOASCEND

Arranges bits of bus pins in descending order; that is, out1 (7 down to 0).

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-Both

The specified handling for undefined cells applies in both the Golden and Revised designs. This is the default.

-Golden

The specified handling for undefined cells applies in only the Golden design.

-Revised

The specified handling for undefined cells applies in only the Revised design.

Related Commands ADD BLACK BOX ADD NOTRANSLATE MODULES READ DESIGN READ LIBRARY REPORT ENVIRONMENT

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SET UNDEFINED PORT SET UNDEfined Port [-Both | -Golden | -Revised] (Setup Mode)

Specifies how Conformal handles undefined ports it encounters when reading in the Golden and Revised libraries and designs. The system default is to report an error message if there are any undefined ports referenced by the module instance. Use the REPORT ENVIRONMENT command to display the settings for the undefined ports handling for the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN.

Parameters Error

Displays an error message for undefined ports.

Ignore

Ignores undefined ports.

-Both

Applies the specified handling for undefined ports in both the Golden and Revised designs. This is the default.

-Golden

Applies the specified handling for undefined ports to the Golden design.

-Revised

Applies the specified handling for undefined ports to the Revised design.

Related Commands READ DESIGN READ LIBRARY REPORT ENVIRONMENT

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SET UNDRIVEN SIGNAL SET UNDRiven Signal < Z | 0 | 1 | X > [-Both | -Golden | -Revised] (Setup Mode)

Specifies globally how Conformal treats undriven signals in the Golden and Revised designs. The system default specifies that undriven signals are classified as high-impedance (always driven by Z) in the Golden and Revised designs. Use the REPORT ENVIRONMENT command to display the settings for the undriven signals for both the Golden and Revised designs. Execute this command before READ LIBRARY and READ DESIGN.

Parameters Z

Specifies undriven signals as high impedance (always driven by Z). This option is the system default.

0

Specifies undriven signals as Logic 0.

1

Specifies undriven signals as Logic 1.

X

Specifies undriven signals as unknown (X).

-Both

Applies the state of the undriven signal to both the Golden and Revised designs. This is the default.

-Golden

Applies the state of the undriven signal to the Golden design.

-Revised

Applies the state of the undriven signal to the Revised design.


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SET WIRE RESOLUTION SET WIre Resolution [-Both | -Golden | -Revised] (Setup Mode)

Specifies how Conformal treats the output behavior of multi-driven nets. The system default for both the Golden and Revised designs specifies that multi-driven nets are treated as a wire-AND behavior. When you use the wire option and Conformal encounters a multi-driven net (that is, bus contention) in a design, Conformal models this multi-driven net as TIE-X. Note: This TIE-X is a pseudo input, not a “don’t care”. Use the REPORT ENVIRONMENT command to display the settings of the wire resolution for the Golden and Revised designs.

Parameters And

Assigns a wire-AND behavior to multi-driven nets. This option is the system default.

Or

Assigns a wire-OR behavior to multi-driven nets.

Wire

Assigns a TIEX behavior to multi-driven nets.

-Both

Applies the specified behavior of multi-driven nets to both the Golden and Revised designs. This is the default.

-Golden

Applies the specified behavior of multi-driven nets to the Golden design.

-Revised

Applies the specified behavior of multi-driven nets to the Revised design.


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SET X CONVERSION SET X COnversion [-Both | -Golden | -Revised] (Setup Mode)

Specifies how Conformal handles X assignments when modeling the design. It takes effect when changing from the Setup mode to the LEC mode. The system defaults specify that X assignments are treated as “Don’t Cares” for the Golden and “Error (E) Gates” for the Revised design. If the X assignment space of the Revised design is within the X assignment space of the Golden design, then the E gate is marked as an extra unmapped point (redundant gate) after comparison. Tip The Revised X Handling feature enhances RTL-to-RTL comparisons. It ensures that the Revised Xs are in the Golden Don't Care space. To turn off this feature, use set x conversion dc -revised. This feature has been available since version 4.3. However, use this option only if you are certain that the X assignment space of the Revised design is within the X assignment space of the Golden design; otherwise, potential errors might be masked. Use the REPORT ENVIRONMENT command to display the settings of the X assignment for the Golden and Revised designs.

Parameters DC

Assigns “Don’t Care” handling to X.

E

Assigns “Error Gate” handling to X. E is a pseudo input.

0

Assigns Zero logic handling to X: 1’b0.

1

Assigns One logic handling to X: 1’b1.

-Both

Applies the specified behavior of X assignments to both the Golden and Revised designs. This is the default.

-Golden

Applies the specified behavior of X assignments to the Golden design.

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-Revised

Applies the specified behavior of X assignments to the Revised design.


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SET XC SET XC (Setup Mode)

Note: This is a Conformal Custom command. Analyzes switch and primitive drive strength to achieve the most accurate logic function result. This technique can be applied to complex custom macros such as RAM and ROM and is essential to accurate verification of circuits with complex layer switch nets.

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SETENV SETENV (Setup / LEC Mode)

Assigns a value to an environment variable name.

Parameters variable

Adds the specified variable to the environment.

value

Assigns the specified value to the variable.

Examples setenv LM_LICENSE_FILE 5280@host

where host is the license server host name.

Related Command PRINTENV

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SUBSTITUTE BLACKBOX MODELS SUBStitute BLackbox Models [-Golden | -Revised] [-NO_RENAME_RULE] (Setup Mode)

Replaces all blackboxed modules in the design space with modules in the library space. Use this command after running the READ DESIGN and READ LIBRARY commands.

Parameters -Golden

Applies to all blackboxed modules in the Golden design. This is the default.

-Revised

Applies to all blackboxed modules in the Revised design.

-NO_RENAME_RULE

Does not use renaming rules for matching pin and module names.

Related Command ADD BLACK BOX

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SUBSTITUTE BLACKBOX WRAPPER SUBStitute BLackbox Wrapper (Setup Mode)

Searches for each blackbox instance in your design whose module name matches those in a specified pattern list, and replaces them with new, fully-defined modules. Use this module in conjunction with the WRITE BLACKBOX WRAPPER command.

Parameters pattern_list

Searches for blackbox instances whose module name matches the specified pattern(s). This option accepts the “*” wildcard.

Example The following is a set of sample commands that show this and related commands in context. Sample module: <<< gol.v>>> module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst, cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout; DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs), .wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );

1. Specify that Conformal treat undefined cells as blackboxes. > set undefined cell black_box

2. Read in the Golden design, which contains our sample module. > read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module DW_ram_r_w_s_dff_5_8_0. write blackbox wrapper DW* -directory dir break

Note: This command also generates synthesis script template files dir/dc.tcl and dir/rc.tcl.

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 4. Use the dir/dc.tcl script with your own synthesis tool to generate dir/_DW_ram_r_w_s_dff_5_8_0.g.v. 5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v file into the design. > read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module _DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w _s_dff_5_8_0.g.v:229). > substitute blackbox wrapper DW*

Related Command WRITE BLACKBOX WRAPPER

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SYSTEM SYSTEM (Setup / LEC Mode)

Enables any command your UNIX operating system recognizes. Note: In GUI mode, the Conformal software prints the return in the transcript window. You can substitute the exclamation mark (!) for the word “System”, as shown in the “Example” section, below.

Parameters string_command

Any valid UNIX command.

Example system ls system pwd !pwd

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TCLMODE TCLMODE (Setup / LEC Mode)

Switches from native Conformal command entry mode (VPX mode) to Tcl command entry mode. VPX mode is the default command mode. There are two types of Tcl mode commands: ■

Native Tcl commands

■

Conformal Tcl commands

Note: When issuing commands in Tcl mode mode, you must type them in lowercase. For more information about native Tcl commands, refer to the public Tcl manual, which is widely available online. Conformal Tcl commands are discussed in detail in the Encounter Conformal Equivalence Checking User Guide. Tip To start the Conformal software in Tcl mode without executing any initialization script, run the following command at a UNIX system prompt: UNIX% lec -tclmode

Tip In the Tcl command entry mode, you can save report data to a file using the redirection command. For example, the following command saves the gate report data to a file named gate.out: TCL_SETUP> report_gate -type dff > gate.out

Related Command VPXMODE

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TEST RENAMING RULE TESt REnaming Rule <-Design [-NOprint | -Print ] | |-GATE_id > [-All | -NEw_rule ] [-MAp [-TYpe … |-NOTYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>…] |-MOdule |-PIn [-BBox ]] [-RULE_USAGE | -NORULE_USAGE] [-Both | -Golden | -Revised] [-SORTNAme] [-File [-REPlace]] [-VErbose] (LEC Mode)

Displays the results of the key point matching based on the user-specified renaming rules. Use this command to obtain a quick summary of how well the key points will be mapped based on the specified renaming rules. Test new and existing rules.

Parameters -Design

Tests the renaming rules on the entire design. This argument instructs Conformal to display a summary of the Golden and Revised pairs and groups and Golden and Revised single un-grouped key points for the entire design.

-NOprint

Does not display the key point pairs, un-grouped single key points, or grouped key points. This is the default.

-Print

Displays key points as follows: Single

Un-grouped single key points

Pair

Key point pairs

Group

Grouped key points

string

A string that the renaming rule uses as an example.

-GATE_id gate_id

Tests renaming rules on the specified gate.

-All

Tests all renaming rules. This is the default. “All” applies within the given defaults.

-NEw_rule string string

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A new renaming rule: The first string is the pattern to be matched; the second string is the substitution pattern. -MAp

Tests the renaming rules on key points that will be mapped. This is the default.

-TYpe

Tests renaming rules for all key points of the specified type. This is the default. The available types are as follows:

-NOTYpe

PI

Primary Inputs

E

TIE-E gates

Z

TIE-Z gates

DFF

D flip-flops

DLAT

D-latches

CUT


BBOX

Blackboxes

PO

Primary Outputs

Tests renaming rules for all key points except the specified types. The available types are as follows: PI

Primary Inputs

E

TIE-E gates

Z

TIE-Z gates

DFF

D flip-flops

DLAT

D-latches

CUT


BBOX

Blackboxes

PO

Primary Outputs

-MOdule

Tests the renaming rules on the modules in the design.

-PIn

Tests the renaming rules on pin names of blackboxes.

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-RULE_USAGE

Displays the number of matches for the specified string. This option is turned on by default.

-NORULE_USAGE

Does not display the number of matches for the specified renaming rule.

-BBox module_name

Tests the pin renaming rule on the specified blackbox module. The default is to test all blackboxes.

-Both

Tests the renaming rules on both the Golden and Revised designs. This is the default.

-Golden

Tests the renaming rules on the Golden design.

-Revised

Tests the renaming rules on the Revised design.

-SORTNAme

When this option is used with the -print option, the results appear in alphabetical order by name.

-File filename

Writes the results to the specified file.

-REPlace

Replaces the above file, if it exists.

-VErbose

Displays both the original key point name and the renamed key point.

Examples ■

The following command displays the summary results of the renaming rules on the designs: test renaming rule -design -all

■

The following command displays a list of all Golden/Revised un-grouped single key points: test renaming rule -design -print single

■

The following command displays a list of all Golden/Revised grouped key points: test renaming rule -design -print group

■

The following command displays a list of all Golden/Revised pair key points: test renaming rule -design -print pair

■

The following command writes a list of all Golden/Revised grouped key points to a file: test renaming rule -design -print group -file group_list

■

The following command displays the summary results of the renaming rule on the designs with a new rule: test renaming rule -design -new_rule

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The following command displays the summary results of the renaming rules applied to a sample string: test renaming rule -all

■

The following command displays the summary results of the new renaming rule applied to a sample string: test renaming rule -new_rule

Related Commands ADD RENAMING RULE DELETE RENAMING RULE MAP KEY POINTS REPORT RENAMING RULE SET NAMING RULE

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UNIQUIFY UNIQuify [-Force] [-USE_RENaming_rules] [-Summary | -Verbose] [-Golden | -Revised] (Setup Mode)

Makes the specified module, which has multiple instances, unique. This command lets you remedy the “incompatible” instantiations warnings during hierarchical script generation. If Conformal does not make the modules unique, they are not included in the hierarchical dofile. When using hierarchical compare for abort resolution, this command allows you to include more modules in the hierarchical dofile, therfore reducing the compare complexity of helping resolve aborts. For more information, see Hierarchical Comparison for Abort Resolution in the Encounter Conformal Equivalence Checking User Guide.

Parameters module_name…

Makes the specified module(s) unique.

-ALL

Makes all modules in the specified design unique. “All” applies within the given defaults.

-Library

Makes all modules in designs and libraries unique. This is the default.

-NOLibrary

Makes all modules in designs unique.

-Force

Forcibly makes specified modules in the Golden or Revised design unique, even if those modules have not been made unique in the complementing design. (For example, forcibly make Golden modules unique when the Revised modules have not been made unique.)

-USE_RENaming_rules Considers renaming rules for instances. When adding renaming rules, the software renames the Golden design instances to be same as in the Revised design, so running a subsequent UNIQUIFY command with this option will make the Golden modules that have matching instance names in the Revised design unique. May 2008

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-Summary

Summarizes the outcome of making modules unique. This is the default.

-Verbose

Provides expanded information about the modules that were made unique.

-Golden

The specified modules are in the Golden design. This is the default.

-Revised

The specified modules are in the Revised design.

Example The following command example creates a hierarchical dofile script named hier.do containing the compare script for the sub-modules and the root module, then runs hierarchical compare. This is can help in resolving aborts. ... uniquify -all write hier_compare dofile hier.do run hier_compare hier do

Related Commands RESOLVE RUN HIER_COMPARE WRITE HIER_COMPARE DOFILE

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USAGE USAge [-Elapse | -Delta ] (Setup / LEC Mode)

Displays the total CPU run time and peak memory use since you started Conformal.

Parameters -Elapse

Displays the elapsed time of a process.

-Delta

Displays the difference, in seconds, between the current CPU run time and CPU run time when you last issued the usage command.


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VALIDATE CIRCUIT VALidate CIrcuit [-Revised | -Golden] [-BBOXSCRipt ] [-MODule ] [-DOfile …] [-POWERPINs … ] [-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs] [-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput] [-ASM | -NOASM] (Setup Mode)

Note: This is a Conformal Ultra command. Checks circuit libraries and custom blocks (when applicable), and enables equivalence checking on the full integrated circuit design. Use this command at the integrated-circuit level for RTL or Gate to final circuit. This application is for checking the consistency of pre-defined libraries during design verification. Important Do not use this command for validating the library itself. To validate library itself, use the VALIDATE LIBRARY command instead. For both the Golden and Revised designs, refer to the same library so that any inconsistencies at the library cell level will not affect the equivalence checking on design level. After which, all the library cells under this checking will be replaced by their counterpart reference cells. Note: Conformal Ultra users can use this to check a verified circuit. However, you need a Conformal Custom license to diagnose logic abstraction and errors that relate to library comparisons.

Parameters -Revised

Validates the Revised database. This is the default.

-Golden

Validates the Golden database.

-BBOXSCRipt Creates a dofile with the specified name that blackboxes all validated cells for structural verification, which is more accurate than logical verification.

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-MODule Validates the specified module. By default, Conformal Ultra validates the root module. Use this option to validate a module other than the root module. Note: Conformal Ultra validates only the topmost library and custom cells (that exist in the reference side) that are used by the specified module. -DOfile … Specifies the name of the dofile that was used to verify all custom blocks so that they can be re-checked. If a custom module has not been verified yet, blackbox it before running the VALIDATE CIRCUIT command. VALIDATE CIRCUIT can check for consistency in custom blocks, but it cannot verify custom blocks. Use Conformal Custom to verify custom blocks. -POWERPINs ... Defines names for the pin(s) that are used as extraneous power pins, which are ignored during cell verification. For multiple power pins, each pin name must be separated by a space. Cadence recommends that you use the ADD PIN CONSTRAINT command to tie power pins to 1 and ground pins to 0. -PRESERVE_MODEL_OPTIONs

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Preserves any user-defined settings made prior to this command. This is the default. This option disables any flattening options that VALIDATE CIRCUIT sets by default. By default, the following flatten model options are set when VALIDATE CIRCUIT compares two modules: -seq_redundant -latch_fold -all_inv_seq_merge -all_seq_merge -seq_const See the SET FLATTEN MODEL command for an explanation of these options. With -PRESERVE_MODEL_OPTIONs, the comparison is done without changing any flatten model options. Any options that were set prior to running validate circuit are used instead. -NO_PRESERVE_MODEL_OPTIONs Does not disable any flattening options that VALIDATE CIRCUIT sets by default. -POWERPIN_TO_INput Specifies that if there are power pins that are input/output pins, they will be changed to input pins before validation. This is the default. -NO_POWERPIN_TO_INput Specifies that power pins that are input/output pins will NOT be changed to input pins before validation. -ASM

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-NOASM


Related Commands READ DESIGN READ LIBRARY SET FLATTEN MODEL

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VALIDATE LIBRARY VALidate LIbrary [-Revised | -Golden] [-NOSPIce | -SPIce] [-NOGOLPINDir | -GOLPINDir] [-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs] [-POWERPINs … ] [-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput] [-ASM | -NOASM] (Setup Mode)

Note: This is a Conformal Ultra and Conformal Custom command. Compares all top-level cells with matching names. Conformal abstracts the modules on the SPICE side before comparison. This application is for library verification during library design. Important To abstract SPICE modules, you must have a Conformal Custom license.

Parameters -Revised

Validates the Revised database. This is the default.

-Golden

Validates the Golden database.

-NOSPIce

Abstracts and validates the modules that are not SPICE. This is the default. Note: This option requires a Custom license.

-SPIce

Abstracts and validates the SPICE modules. Note: This option requires a Custom license.

-NOGOLPINDir

Does not copy the pin directions from the Golden design to the Revised design. This is the default.

-GOLPINDir

Copies the pin directions from the Golden design to the Revised design. This is for all pins within the library cells being validated.

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-PRESERVE_MODEL_OPTIONs Preserves any user-defined settings made prior to this command. This is the default. This option disables any flattening options that VALIDATE LIBRARY sets by default. -NO_PRESERVE_MODEL_OPTIONs Does not disable any flattening options that VALIDATE LIBRARY sets by default. -POWERPINs ... Defines names for the pin(s) that are used as extraneous power pins, which are ignored during cell verification. For multiple power pins, each pin name must be separated by a space. Cadence recommends that you use the ADD PIN CONSTRAINT command to tie power pins to 1 and ground pins to 0. -POWERPIN_TO_INput

Specifies that if there are power pins that are input/output pins, they will be changed to input pins before validation. This is the default.

-NO_POWERPIN_TO_INput Specifies that power pins that are input/output pins will NOT be changed to input pins before validation. -ASM


-NOASM


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Related Command VALIDATE CIRCUIT

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VERSION VERsion (Setup / LEC Mode)

Displays the current version release number of Conformal. You can use this command after the SET LOG FILE command so the version becomes a part of the transcript log. In this way, you record the Conformal version that created your results. This command is also helpful when you use the SAVE SESSION and RESTORE SESSION commands, because you must use the same Conformal version when you restore a session.

Related Commands RESTORE SESSION SAVE SESSION SET LOG FILE

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VPXMODE VPXMODE (Setup / LEC Mode)

Switches from Tcl mode to native Conformal command entry mode (VPX mode). VPX is the default command mode. Important When issuing this command in the Tcl command interpreter, you must type this in lowercase. For example: TCL_LEC> vpxmode

Tip In VPX mode, you can save report data to a file using the redirection command. For example, the following command saves the gate report data to a file named gate.out: SETUP> report gate -type dff > gate.out

Related Command TCLMODE

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WRITE BLACKBOX WRAPPER WRIte BLackbox Wrapper -DIRectory (Setup Mode)

Creates a wrapper for each blackbox instance in your design whose module name matches those in a specified pattern list. Use this command to help complete equivalency checking for designs that contain DesignWare or ChipWare blackboxed modules. This command produces a module instantiation wrapper file for each blackboxed module wrapper, and synthesis script templates that you can use with your own synthesis tool to synthesize the modules that Conformal blackboxed. Synthesize the wrapper modules using the outputted scripts. Then, read in the newly-synthesized files using the READ DESIGN -append command. Finally, use the SUBSTITUTE BLACKBOX WRAPPER command to substitute the old blackboxed modules with the newly synthesized modules. Note: When specifying the cells that Conformal will treat as blackboxes, use the set undefined cell black_box command instead of the add notranslate modules command.

Parameters -DIRectory

Writes out the module instantiation wrapper file and the scripts to this directory.

pattern_list

Writes out module wrappers for blackbox instances whose module name matches the specified pattern(s). This option accepts the “*” wildcard.

Examples The following is a set of sample commands that show this and related commands in context. Sample module: <<< gol.v>>> module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst, cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout; DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs), .wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );

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Encounter Conformal Equivalence Checking Reference Manual Command Reference 1. Specify that Conformal treat undefined cells as blackboxes. > set undefined cell black_box

2. Read in the Golden design, which contains our sample module. > read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox module DW_ram_r_w_s_dff_5_8_0. write blackbox wrapper DW* -directory dir break

Note: This command also generates synthesis script template files dir/dc.tcl and dir/rc.tcl. 4. Use the dir/dc.tcl script with your own synthesis tool to generate dir/_DW_ram_r_w_s_dff_5_8_0.g.v. 5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v file into the design. > read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module _DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w _s_dff_5_8_0.g.v:229). > substitute blackbox wrapper DW*

Related Command SUBSTITUTE BLACKBOX WRAPPER

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WRITE COMPARED POINTS WRIte COmpared Points [-CLass ] [-TYpe ] [-File ] [-Replace] (LEC Mode)

Writes compared points information to a file. You can use this file to add a specific class and type of compared points to a compare list.

Parameters -CLass

Writes out the class of compared points. By default, the command writes out all classes. All

Writes all compared point classes. This is the default if you do not specify the -CLass option.

Eq

Writes compared points that are equivalent.

INVequivalent Writes the compared points that are inverted equivalent.

-TYpe

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NONeq

Writes the compared points that are non-equivalent.

ABort

Writes the aborted compared points.

NOTcompared

Writes the compared points that are not compared.

Writes out the type of compared points. By default, the command writes out all types. All

Writes all compared point types. This is the default if you do not specify the -TYpe option.

PO

Writes the compared points of the primary outputs.

DFf

Writes the compared points of the D flip-flops.

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DLat

Writes the compared points of the D-latches.

Bbox

Writes the compared points of the blackboxes.

Cut

Writes the compared points for artificial gates that break combinational loops.

-File

Specifies the filename.

-Replace


Related Commands ADD COMPARED POINTS

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WRITE DESIGN WRIte DEsign [ | -ALL | -BBOX] [-Used] [-Library] [-REPlace] [-RTL] [-TEST_VIEW] [-Golden | -REVised] (Setup / LEC Mode)

Writes out the Golden or Revised design in Verilog format to examine how Conformal abstracts RTL descriptions into gate-level descriptions. Use the tilde character (~) to shorten the path of the file.

Parameters filename

Writes the design to this file.

-ALL

Writes out all modules that are stored in the design space.

-BBOX

Writes out all of the empty module descriptions of blackboxes in the design. By default, the command writes out the design tree of the root module, excluding modules in the library space.

-Used

Writes out the specified modules and all the referenced modules, including modules in the design space.

-Library

Writes out the library information.

-REPlace


-RTL

Outputs word-level operator expressions such as *, +, and -. By default, the command writes out the design without using the word-level operators. Without this option, the command writes out the design in Verilog primitive gates.

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-TEST_VIEW

Writes out the abstraction result of ABSTRACT LOGIC -test_view. The result might include Encounter Test primitives. To read the netlist back, use the READ DESIGN command’s -define option for ET_EC_MODEL. For example: read design -define ET_EC_MODEL

-Golden

Writes out the Golden design only. This is the default.

-REVised

Writes out the Revised design only.


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WRITE ECO DESIGN WRIte ECo Design [-OVERWrite | -NEWFILE [filename_fmt] | -REVIEWonly] [-BACKup [filename_fmt]] [-REPORT [filename]] [-REPlace] (Setup Mode)

Writes out the ECO netlist and attempts to reduce the number of text differences between the original netlist file and the ECO netlist file. This will reduce the number of differences reported by the UNIX diff command between the two files.

Limitations ■

Does not work with VHDL netlists.

■

Does not work if you flatten the design during the ECO process.

Parameters -OVERWrite

Overwrites the original files. This is the default.

-NEWFILE [filename_fmt] Writes the design into new files. The default format for the new files is %s.eco, where %s is the original filename. -REVIEWonly

Reviews the changes only and does not write out the design

-BACKup [filename_fmt] Creates a back up original files if using the -OVERWrite option. The default format for the backup files is %s.bak, where %s is the original file name. -REPORT [filename] Generates a report showing the differences between the original design and the ECO design. If the filename is not provided, the report will print to the screen. -REPlace

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Replaces the file if it already exists when using the -NEWFILE and -REPORT options.

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Example The following is a sample script that writes out the a.v.eco and b.v.eco files after running the Conformal ECO commands: read design a.v b.v -golden // ECO process analyze eco ... optimize patch ... write eco design -newfile -replace

Related Commands REPORT ECO CHANGES

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WRITE HIER_COMPARE DOFILE WRIte HIer_compare Dofile [-MODULE [-HIERarchical | -FLATten]] [-Black_box | -NOBlack_box] [-CONDitional] [-Exact_pin_match | -NOExact_pin_match] [-NOConstraint | -Constraint [-EXTRACT_Clock] [-INPUT_OUTPUT_Pin_equivalence] [-RUN_HIER_compare] ] [-PREPEND_String ] [-APPEND_String ] [-COMPARE_String ] [-CONDitional] [-Threshold ] [-LEVEL ] [-All] [-Usage] [-Replace] [-RETIMED_modules] [-IGNORE_MISMATCH_ports] [-VERBOSE] (Setup Mode)

Writes out a hierarchical dofile script that verifies the two hierarchical designs starting from the lower-level modules and progressing to the top root module. Use options to specify one of the following actions: ■

Blackbox modules after comparison

■

Write modules with different numbers of pins to the dofile script

■

Propagate the constraints to lower-level modules and apply them to the dofile script

■

Change the minimum number of module primitives considered for hierarchical comparison

Use the tilde character (~) to shorten the path of the file. This command also generates a dofile script to compare two libraries, such as a Liberty and Verilog library. Use the -all option to write all library models to the dofile script for comparison. Note: Hierarchical comparison is also useful in resolving aborts. See the UNIQUIFY command for more information.

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Parameters

Specifies the name of the dofile script that verifies design hierarchy.

-MODULE Writes the specified Golden module and Revised module to the hierarchical dofile script. -HIERarchical

Includes all of the submodules of the specified module in the hierarchical dofile script. This is the default.

-FLATten

Flattens all of the submodules of the specified module.

-Black_box

Blackboxes each module after comparison. This is the default.

-NOBlack_box

Does not blackbox each module after comparison.

-CONDitional

Automatically merges the module to the next level in the hierarchy if the comparison at the current level was unsuccessful.

-Exact_pin_match

Writes only those modules with matching pin names to the hierarchical dofile script. This is the default.

-NOExact_pin_match

Writes all modules to the hierarchical dofile script.

-NOConstraint

Does not apply the root module constraints and equivalences to the hierarchical dofile script. This is the default.

-Constraint

Propagates root module constraints and equivalences and applies them to the hierarchical dofile script.

-EXTRACT_Clock

Extracts the clock pins in the Golden and Revised designs, and automatically adds the renaming rules to hierarchical dofile script to map the clock ports in the two designs. This can be used when the design has undergone Clock-Tree-Synthesis (CTS).

-INPUT_OUTPUT_Pin_equivalence Extracts input-output pin equivalences within a module and applies them to hierarchical dofile script. This can be used when the design has feedthroughs or feedback buffers.

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-RUN_HIER_compare

Writes out more modules in the hierarchical dofile script by performing less stringent constraint checking. The resulting dofile must only be processed by the RUN HIER_COMPARE command and its default options.

-PREPEND_String Appends any string of commands to the hierarchical dofile script before key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each prepended command (see “Examples”). -APPEND_String Appends any string of commands to the hierarchical dofile script after key point comparison for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each appended command (see Examples). -COMPARE_String Replaces the default compare command with a string of compare commands in the hierarchical dofile script generation for each module. Use the semi-colon character (;) to separate commands. Use double quotes to surround each compare command (see Examples). -CONDitional

Skips blackboxing for nonequivalent submodules during the hierarchical comparison. (The end result is that Conformal flattens these submodules.) To report the flattened modules, use the report hier_compare result -flattened command.

-Threshold integer

This threshold is the minimum number of primitives within a module that will be written to the hierarchical dofile script. The minimum default number is 50 primitives.

-LEVEL integer

Writes all modules to the hierarchical dofile script up to the specified hierarchical level.

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-All

Writes “all” library modules to the hierarchical dofile script. “All” applies within the given defaults. Use this option for library verification.

-Usage

Executes the USAGE command after each comparison and at the end of the hierarchical comparison.

-Replace


-RETIMED_modules

Writes out only those modules which have the PIPELINE_RETIME attribute attached to them. Use the ADD MODULE ATTRIBUTE command to attach the PIPELINE_RETIME attribute to a module.

-IGNORE_MISMATCH_ports Forces all modules with mismatched ports to be written out in a hierarchical dofile. -VERBOSE

Provides additional information when writing out the hierarchical dofile script.

Examples write hier_compare dofile hier.do -replace write hier_compare dofile lec.do -replace write hier_compare dofile hier.do -append_string “usage” -prepend_string “report unmapped points -notmapped” -replace ■

The following is a sample dofile that reads in the two hierarchical designs, writes out the hierarchical dofile script, and compares design hierarchies: read library golden.lib -verilog -golden read design golden.v -verilog -golden read library revised.lib -verilog -revised read design revised.v -verilog -revised write hier_compare dofile hier.do -replace set log file hier.log -replace dofile hier.do exit -force

■

The following is a sample dofile that reads in a synthesis library and simulation library, writes out all of the library models, and compares library hierarchies: read design syn.lib -liberty -golden read design simulation.v -verilog -revised write hier_compare dofile lib_ver.do -replace -all

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Encounter Conformal Equivalence Checking Reference Manual Command Reference set log file lib_ver.log -replace dofile lib_ver.do exit -force ■

In the following command, the default compare command is replaced with two commands during each module comparison, set compare effort low and compare -abort_stop 1 -noneq_stop 1: write hier_compare dofile -compare_string \ “set compare effort low; compare -abort_stop 1 -noneq_stop 1”

■

The following command example creates a hierarchical dofile script named hier.do containing the compare script for the sub-modules and the root module, then runs hierarchical compare. This is can help in resolving aborts. ... uniquify -all write hier_compare dofile hier.do run hier_compare hier do

Related Commands ADD NOBLACK BOX DELETE NOBLACK BOX READ DESIGN READ LIBRARY REPORT HIER_COMPARE RESULT REPORT NOBLACK BOX RESET HIER_COMPARE RESULT RUN HIER_COMPARE SAVE HIER_COMPARE RESULT SET NAMING RULE UNIQUIFY

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WRITE LIBRARY WRIte LIbrary [-Verilog] [-REPlace] [-Golden | -REVised] (Setup / LEC Mode)

Writes out the Golden or Revised library to a Verilog file. The default is to write out the library as functional Verilog model descriptions. Use this command to examine how Conformal abstracts complex UDP library models. Use the tilde character (~) to shorten the path of the file.

Parameters filename

Specifies the library filename.

-Verilog

Writes out the library in Verilog format. This is the default.

-REPlace


-Golden

Writes out only the Golden library. This is the default.

-REVised

Writes out only the Revised library.

Related Command READ LIBRARY

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WRITE MAPPED POINTS WRIte MApped Points [-CLass < Full | System | User> [-TYpe …] [-NOTYpe …] [-REPlace] (LEC Mode)

Writes the mapped point information to a file. If the comparison needs to be done at a later time, you can use this command to accelerate the mapping process. Use the READ MAPPED POINTS command to read the file. Use the tilde character (~) to shorten the file’s path.

Parameters filename


-CLass

Writes out the System, User, or Full classes of mapped points. Full

Both the User and System class. This is the default.

System

Key points that are mapped automatically.

User

User class: key points that are manually mapped with the ADD MAPPED POINTS command.

-TYpe mapped_keypoint_type Writes only the mapped key points of the specified type. Available types are as follows:

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Primary input

E

TIE-E

Z

TIE-Z

DFf

D flip-flop

DLat

D-latch

CUt


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BBox

Blackbox

PO

Primary output

-NOTYpe mapped_keypoint_type Does not write the mapped key points of the specified type. Available types are as follows:

-REPlace

PI

Primary input

E

TIE-E

Z

TIE-Z

DFf

D flip-flop

DLat

D-latch

CUt


BBox

Blackbox

PO

Primary output


Related Commands READ MAPPED POINTS WRITE PARTITION DOFILE

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WRITE MEMORY PRIMITIVE WRIte MEmory Primitive [-Module | -All] [-REPlace] [-OPTionsdef ] [-COMmondef ] (LEC Mode)

Note: This is a Conformal Custom command. Writes memory primitives to a file. Use this command to retrieve information for simulation. For additional information about memory primitives, refer to the “Memory Primitive Data Sheet” located at /doc/MEM_datasheet.pdf. Use the tilde character (~) to shorten the path of the file. Note: The wildcard (*) represents any zero or more characters in module names.

Parameters filename


-Module name*

Writes only the memory primitives for the specified module. The wildcard (*) is supported.

-All

Writes out memory primitives for all modules.

-REPlace


-OPTionsdef Writes parameter option definitions to a separate file. This will write the ‘define statements, which are options to available parameters, from the memory primitives to a separate file. -COMmondef Writes the common module called Vpx_wireOrlatOrff_data to a separate file. This module is common to all memory primitives. You can write common memory primitive definitions to a separate file during each call to WRITE MEMORY PRIMITIVE, or you can use an existing file using the -rep option.

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WRITE PARTITION DOFILE WRIte PArtition Dofile [-Map filename] [-Usage] [-Replace] [-PREPEND_String ] [-APPEND_String ] [-COMPARE_String ] (Setup / LEC Mode)

Writes out a partition dofile script based on the key point names specified with the ADD PARTITION KEY_POINT command. The number of compare iterations is based on whether the key point names have all-pattern, one-hot, or one-cold constraints. Use the tilde character (~) to shorten the path of the file.

Parameters filename

The partition dofile is written to this file.

-Map filename

Uses the specified file for key point mapping. (You must use the WRITE MAPPED POINTS command before using this option.)

-Usage

Executes the USAGE command after each comparison and at the end of the partition dofile.

-Replace


-PREPEND_String Appends any string of commands to the partition dofile script before key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each prepended command (see “Examples” below). -APPEND_String Appends any string of commands to the partition dofile script after key point comparison for each module. Use “;” to separate commands. Use double quotes to surround each appended command (see “Examples” below). May 2008

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-COMPARE_String string Replaces the default compare command with a string of compare commands in the partition dofile script generation for each module. Use “;” to separate commands. Use double quotes to surround each compare command (see “Examples”).

Example write partition dofile partition.do -replace write partition dofile ptn.do -append_string “usage” -prepend_string “report unmapped points -notmapped” -replace

In the following command, the default compare command is replaced with two commands during each module comparison, set compare effort low and compare -abort_stop 1 -noneq_stop 1: write partition dofile -compare_string “set compare effort low; compare -abort_stop 1 -noneq_stop 1”

Related Commands ADD PARTITION KEY_POINT DELETE PARTITION KEY_POINT REPORT PARTITION KEY_POINT WRITE MAPPED POINTS

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WRITE RULE CHECK WRIte RUle Check [-DEsign | -LIbrary] [-Golden | -REVIsed] [-Replace] (Setup Mode)

Writes the rule violations into a rule file. Use this command the first time you run a session. For later runs, exclude the violations already flagged with the read rule check -exclude command. Use the tilde character (~) to shorten the path of the file.

Parameters filename

Writes rule check violations to the specified file.

-DEsign

Writes only design rule check violations. If you do not specify -design or -library, Conformal writes rule check violations from both designs and libraries.

-LIbrary

Writes only library rule check violations. If you do not specify -design or -library, Conformal writes rule check violations from both designs and libraries.

-Golden

Writes rule check violations from the Golden design. This is the default.

-Revised

Writes rule check violations from the Revised design.

-REPlace

Replaces the previously saved file.

Examples In the following example, the second report rule check will not report any rules. read design g.v -golden read design r.v -revised write rule check rule.g -golden -replace write rule check rule.r -revised -replace read design g.v -golden -replace read design r.v -revised -replace report rule check -verbose -both

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Encounter Conformal Equivalence Checking Reference Manual Command Reference read rule check rule.g -exclude -golden read rule check rule.r -exclude -revised report rule check -verbose -both

Related Command READ RULE CHECK

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3 HDL Rule Check Messages This chapter is organized into sections by HDL rule categories. Each section lists all of the rules and messages for the specified category. Each rule message is defined and followed by a sample case that can cause the message. The examples include a brief explanation that direct you to the pertinent lines of code, which appear in bold type. The rule categories included in this chapter are listed below. Register Transfer Level messages are a super-set of rules that apply to both Verilog and VHDL. However, rules included in the Verilog category apply to Verilog, only. ■

Directive on page 522

■

File on page 549

■

Hierarchy on page 551

■

Ignored on page 584

■

Register Transfer Level on page 603

■

SPICE Netlist Format on page 720

■

System Verilog on page 733

■

User-Defined Primitive on page 752

■

Verilog on page 764

Within each category, rules are grouped in sets according to their relationship to each other. For example, DIR1.1 and DIR1.2 both relate to pragmas. Likewise, IGN3.1 and IGN3.2 are grouped because they both address how the checker handles duplications.

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Encounter Conformal Equivalence Checking Reference Manual HDL Rule Check Messages

Directive This category of rules applies to designs that include directives or pragmas. The following table lists the Directive (DIR) rule check numbers and messages. Rule Number

Message

DIR1.1

built_in pragma applied to function

DIR1.2

map_to_operator pragma applied to function

DIR1.3

return_port_name pragma applied to function

DIR2.1

full_case directive is detected

DIR2.2

parallel_case directive is detected

DIR3.1

synthesis/translate/compile on/off directive is detected

DIR3.2

dc_script_begin and dc_script_end directives is detected

DIR4.1

HDL directive/pragma is unsupported

DIR4.2

HDL directive/pragma is supported

DIR4.3

HDL directive/pragma is disabled

DIR4.4

HDL directive/pragma is ignored

DIR5.1

Conformal multi_port directive is detected

DIR5.2

Conformal multi_port directive is detected

DIR5.3

Conformal mem_rowselect directive is detected

DIR5.4

Conformal conformal cutpoint directive is supported

DIR6.1

Ignored compiler directive is detected

DIR6.2

Supported compiler directive is detected

DIR7.1

Unsupported synthesis attribute is detected

DIR7.2

Supported synthesis attribute is detected

DIR8.1

‘protected/‘endprotected pragma is used

DIR9.1

Verilog ‘celldefine is for timing simulation. Use the LIBERTY library instead

DIR9.2

Illegal to redefine a Verilog compiler directive as a macro

DIR9.3

Verilog compiler directive is redefined as a macro

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DIR1.1 Message built_in pragma applied to function

Default Severity Warning Description The design applies the built_in pragma to a function. If the checker supports the specified pragma, it also displays the rule DIR4.2 message. Example In the following example, pragma built_in is inserted in function my_or. See line 4 (in bold). ARCHITECTURE arch OF test IS FUNCTION my_or ( l, r : bit ) RETURN bit IS -- pragma built_in SYN_OR BEGIN RETURN '0'; END my_or; BEGIN proc2 : PROCESS BEGIN out0 <= my_or (in1,in2); END PROCESS; END arch;

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DIR1.2 Message map_to_operator pragma applied to function

Default Severity Warning Description The design applies the map_to_operator pragma to a function. If the checker supports the specified pragma, it also displays the rule DIR4.2 message. Example In the following example, the map_to_operator pragma is inserted in function my_leq. See line 5 (in bold). ARCHITECTURE arch OF test IS FUNCTION my_leq ( l, r : bit_vector (3 downto 0) ) RETURN boolean IS -- pragma map_to_operator LEQ_TC_OP BEGIN RETURN false; END my_leq; BEGIN proc2 : PROCESS BEGIN out0 <= my_leq (in1,in2); END PROCESS; END arch;

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DIR1.3 Message return_port_name pragma applied to function

Default Severity Warning Description The design applies the return_port_name pragma to a function that contains this pragma. If the checker supports the specified pragma, it also displays the rule DIR4.2 message. Example In the following example, the return_port_name pragma on line 8 (in bold) is inserted in function DWF_div_uns. module test; parameter a_width = 16; parameter b_width = 16; function [a_width-1 : 0] DWF_div_uns; // Function to compute the unsigned quotient // pragma map_to_operator DIV_UNS_OP // pragma return_port_name QUOTIENT input [a_width-1 : 0] A; input [b_width-1 : 0] B; begin // pragma translate_off return 0; // pragma translate_on end endfunction endmodule

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DIR2.1 Message full_case directive is detected

Default Severity Warning Description The design includes a full_case directive in a case statement. If the checker supports the specified directive, it also displays the rule DIR4.2 message. Example The following example uses the synopsys full_case directive in line 7 (in bold). module test ( a, e, sel, out0); input a, e; input sel; output out0; reg out0; always @(sel or a or e) begin case(sel) // synopsys full_case 1'b1 : out0 = a; default: out0 = e; endcase end endmodule

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DIR2.2 Message parallel_case directive is detected

Default Severity Warning Description The design includes a parallel_case directive used in a case statement. If the checker supports the specified directive, it also displays the rule DIR4.2 message. Example The following example includes the synopsys parallel_case directive on line 7 (in bold). module test ( a, e, sel, out0); input a, e; input sel; output out0; reg out0; always @(sel or a or e) begin case(sel) // synopsys parallel_case 1'b1 : out0 = a; default: out0 = e; endcase end endmodule

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DIR3.1 Message synthesis/translate/compile on/off directive is detected

Default Severity Warning Description The design includes a directive belonging to one of the following classes: ■

synthesis on/off

■

translate on/off

■

compile on/off

If the checker supports this directive, it also displays the rule DIR4.2 message. In the Conformal Equivalency Checker, you can also define your own directive to turn synthesis on and off with the following commands: ■

SET_ATTR INPUT_PRAGMA_KEYWORD

■

SET SYNTHESIS_OFF_COMMAND

■

SET SYNTHESIS_ON_COMMAND

Example The following example includes the synopsys translate_off and synopsys translate_on directives. See lines 5 and 7 (in bold). module test ( clk, din, dout ); input clk, din; output dout; reg dout; // synopsys translate_off reg [0:0] mem [1:0]; // synopsys translate_on always @(posedge clk) dout <= din; endmodule

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DIR3.2 Message dc_script_begin and dc_script_end directives is detected

Default Severity Warning Description The design includes the dc_script_begin and dc_script_end directives. If the checker supports the specified directives, it also displays the rule DIR4.2 message.. Example In the following example, the design includes the dc_script_begin and dc_script_end directives. See lines 5 and 7 (in bold). module test ( clk, din, dout ); input clk, din; output dout; reg dout; // synopsys dc_script_begin // set_implementation wall MPYDW // synopsys dc_script_end always @(posedge clk) dout <= din; endmodule

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DIR4.1 Message HDL directive/pragma is unsupported

Default Severity Warning Description The design includes one or more HDL directives or pragmas that the checker does not support. Example In the following example, the checker does not support the synopsys not_defined_or_not_supported directive. See line 6 (in bold). module test ( clk, in0, out0 ); input clk, in0; output out0; reg out0; always @( posedge clk ) // synopsys not_defined_or_not_supported out0 <= in0; endmodule

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DIR4.2 Message HDL directive/pragma is supported

Default Severity Warning Description The design includes one or more HDL directives or pragmas that the checker supports. Example In the following example, the checker supports the synopsys full_case directive. See line 7 (in bold). module test ( a, e, sel, out0); input a, e; input sel; output out0; reg out0; always @(sel or a or e) begin case(sel) // synopsys full_case 1'b1 : out0 = a; default: out0 = e; endcase end endmodule

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DIR4.3 Message HDL directive/pragma is disabled

Default Severity Warning Description The design includes one or more HDL directives or pragmas that were disabled by the user. The command used to disable a directive or pragma is: set directive off

Example In the following example, the design includes the conformal assertion_library directive on line 5 (in bold). However, we disabled it with the SET DIRECTIVE OFF command. (Shown below the test case.) module test (a, b, q); input [3:0] a, b; output [3:0] q; reg [3:0] q; // conformal assertion_library always @ (a or b ) begin q = a & b; end endmodule

Input: SETUP>set directive off assertion_library SETUP>read design test.v -verilog

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DIR4.4 Message HDL directive/pragma is ignored

Default Severity Warning Description The specified HDL directive or pragma is not supported and will be ignored. Example In the following example, if the dofile contains the following line: set directive off

translate_on translate_off unknown_pragma

The unknown_pragma is not a supported directive or pragma and will be ignored.

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DIR5.1 Message Conformal multi_port directive is detected

Default Severity Warning Description The checker generates this message when the design includes the Conformal multi_port directive. This directive specifies that the checker will model the specified register with multiple clock ports, multiple data ports, and a single output port. Note: If you do not include the multi_port directive, by default, the checker creates multiple registers with outputs wired together. Example In the following example, the design includes the conformal multi_port directive in line 5 (in bold). module test ( clk1, clk2, in0, out0 ); input clk1, clk2, in0; output out0; reg out0; // conformal multi_port “out0” always @( posedge clk1 ) out0 <= 1'b0; always @( posedge clk2 ) out0 <= in0; endmodule

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DIR5.2 Message Conformal multi_port directive is detected

Default Severity Warning Description The checker generates this message when the design includes the Conformal clock_hold directive. This directive specifies that the checker will model the selected registers as gated-clock registers. Example In the following example, the design includes the conformal clock_hold directive on line 5 (in bold). module test ( clk, din, adr, out0 ); input clk, din, adr; output out0; reg [0:0] mem [1:0]; // conformal clock_hold mem always @(posedge clk) begin mem[adr] <= din; end assign out0 = mem[adr]; endmodule

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DIR5.3 Message Conformal mem_rowselect directive is detected

Default Severity Warning Description The checker generates this message when the design includes the Conformal mem_rowselect directive. This directive specifies that the checker will model the following type of RTL into a structure that lets you define the signals that are synthesized as part of the decoded word line of the ram_array, while all other signals on the sensitivity list are synthesized into the logic cone of the input bit line. always @(clk or we or din or addr) begin if (clk && we) ram_array(addr) = din; end

Example In the following example, the design includes the conformal mem_rowselect directive on line 7 (in bold). module test(clk, en, addr, din, dout); input clk, en; input [1:0] addr; input [0:0] din; output [0:0] dout; reg [0:0] ram [3:0]; // conformal mem_rowselect “ram clk en addr[1]” always @(clk or en or addr or din) begin if (clk && en) ram[addr[1:0]] = din; end assign dout = ram[addr[1:0]]; endmodule

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DIR5.4 Message Conformal conformal cutpoint directive is supported

Default Severity Warning Description The variable defined by the pragma is the cut point in the design. Example In the following example, ram is defined as the cutpoint. module test(clk, en, addr, din, dout); input clk, en; input [1:0] addr; input [0:0] din; output [0:0] dout; reg [0:0] ram [3:0]; // pragma cutpoint "ram” always @(clk or en or addr or din) begin if (clk && en & ram[0] ) ram[addr[1:0]] = din; end assign dout = ram[addr[1:0]]; endmodule

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DIR6.1 Message Ignored compiler directive is detected

Default Severity Warning Description The checker detected the use of an ignored compiler directive. Below is a full list of ignored compiler directives: 1. ‘accelerate 2. ‘autoexpand_vectornets 3. ‘default_decay_time 4. ‘default_strength 5. ‘delay_mode 6. ‘delay_mode_distributed 7. ‘delay_mode_unit 8. ‘delay_mode_zero 9. ‘end_pre_16a_paths 10. ‘expand_vectornets 11. ‘line 12. ‘noaccelerate 13. ‘noexpand_vectornets 14. ‘noremove_gatenames 15. ‘nounconnected_drive 16. ‘pre_16a_paths 17. ‘remove_gatenames May 2008

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Encounter Conformal Equivalence Checking Reference Manual HDL Rule Check Messages 18. ‘remove_names 19. ‘switch 20. ‘timescale 21. ‘unconnected_drive 22. ‘unprotected 23. ‘uselib Example In the following example, the Verilog RTL accepts compiler directives ‘celldefine and ‘endcelldefine on lines 1 and 8. All modules declared after ‘celldefine and before ‘endcelldefine are marked as ASIC library cells. Currently only Conformal Constraint Designer uses this marking for finding timing paths. ‘celldefine module cell1 (a, b); input a; output b; buf (b, a); endmodule ‘endcelldefine

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DIR6.2 Message Supported compiler directive is detected

Default Severity Warning Description The checker detected a supported compiler directive. Below is a full list of supported compiler directives: 1. ‘celldefine and ‘endcelldefine 2. ‘define 3. ‘ifdef, ‘ifndef, ‘elsif, ‘endif 4. ‘undef 5. ‘include “” 6. ‘protect

and ‘endprotect

7. ‘protected and ‘endprotected 8. ‘default_nettype net_type 9. ‘resetall Example In the following example, the checker supports compiler directive ‘default_nettype wire on line 1 (in bold). ‘default_nettype wire module test (din, dout); input din; output dout; assign dout = din; endmodule

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DIR7.1 Message Unsupported synthesis attribute is detected

Default Severity Warning Description The checker detected a synthesis attribute that it does not support. Example In the following example, the checker ignores the attribute MAX_DELAY, rendering it ineffective (see lines 9 and 10). entity TEST is port( IN1 : in integer; OUT1 : out bit ); end test; architecture RTL of TEST is attribute MAX_DELAY : string; attribute MAX_DELAY of TEST: entity is “1431”; begin OUT1 <= ’1’ when IN1 > 329 else ’0’; end RTL;

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DIR7.2 Message Supported synthesis attribute is detected

Default Severity Warning Description The design includes a synthesis attribute that the checker supports. Example The following example defines the attribute ENUM_ENCODING to specify the encoding of the enumeration type (see lines 10 and 11). entity TEST is port( SEL : in bit_vector(2 downto 0); OUT1 : out bit ); end test; architecture RTL of TEST is type ET is (ET1, ET2, ET3); attribute ENUM_ENCODING : string; attribute ENUM_ENCODING of ET : type is “00 01 11"; signal SIG1 : ET; begin process (SEL) begin if (SEL = "000") then SIG1 <= ET1; elsif (SEL = "111") then SIG1 <= ET2; else SIG1 <= ET3; end if; end process; OUT1 <= ’1’ when (SIG1 = ET3) else ’0’; end RTL;

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DIR8.1 Message ‘protected/‘endprotected pragma is used

Default Severity Warning Description The content after the pragma is protected. Example In the following example, line 3 is protected because it is between the ‘protected and ‘endprotected directives: Pragma `protected/èndprotected used primitive FOO_P `protected SOME98098jlkajdGOO èndprotected endprimitive

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DIR9.1 Message Verilog ‘celldefine is for timing simulation. Use the LIBERTY library instead

Default Severity Ignore Description A Verilog module enclosed between ‘celldefine and ‘endcelldefine is recognized as a technology library cell. Conformal Constraint Designer prefers using technology cells in the LIBERTY format, and reports a rule check violation. The default severity for this rule check is ERROR. You can override the severity with the SET RULE HANDLING command. Example If the following module is read using READ DESIGN or READ LIBRARY command, the Conformal software reports this rule check error by default. ‘celldefine module TECH_CELL_BUF (Y, A); output Y; input A; buf I0(Y, A); specify specparam tplh$A$Y = 1.0, tphl$A$Y = 1.0; (A *> Y) = (tplh$A$Y, tphl$A$Y); endspecify endmodule // TECH_CELL_BUF ‘endcelldefine

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DIR9.2 Message Illegal to redefine a Verilog compiler directive as a macro

Default Severity Warning Description You have attempted to redefine a Verilog compiler directives that is one of the following: ‘celldefine ‘default_nettype ‘define ‘else ‘endcelldefine ‘endif ‘ifdef ‘ifndef ‘include ‘nounconnected_drive ‘resetall ‘timescale ‘unconnected_drive ‘undef

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Encounter Conformal Equivalence Checking Reference Manual HDL Rule Check Messages Example The following ‘define statement (see line 1) causes a DIR9.2 rule violation: ‘define timescale 1’b0 module test (in,out); input in; output out; assign out = in; endmodule

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DIR9.3 Message Verilog compiler directive is redefined as a macro

Default Severity Warning Description You have attempted to redefine other Verilog compiler directives that are not as follows: ‘celldefine ‘default_nettype ‘define ‘else ‘endcelldefine ‘endif ‘ifdef ‘ifndef ‘include ‘nounconnected_drive ‘resetall ‘timescale ‘unconnected_drive ‘undef

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Encounter Conformal Equivalence Checking Reference Manual HDL Rule Check Messages Example The following ‘define statement (see line 1) causes a DIR9.3 rule violation: ‘define switch 1’b1 module test (in,out); input in; output out; assign out = in; endmodule

The above statement causes the ‘switch directive to be deleted and replaced by a userdefined macro.

May 2008

548

Product Version 7.2


File This category of rules applies to designs that include file issues. The following table lists the File issue (FIL) rule numbers and their messages. Rule Number

Message

FIL1.1

Input file recursion detected

May 2008

549

Product Version 7.2


FIL1.1 Message Input file recursion detected

Default Severity Error Description This detects that input files are included recursively. Example The two files in the following example are recursively included: In file file1.v, has ’‘include "file2.v"’. In file file2.v, has ’‘include "file1.v"’.

May 2008

550

Product Version 7.2


Hierarchy This category of rules applies to designs that are comprised of hierarchical modules. The following table lists the Hierarchy (HRC) rule check numbers and messages. Rule Number

Message

HRC1.1

Module/entity is not loaded due to unsupported construct (blackboxed)

HRC1.2

Module/entity is not translated (blackboxed)

HRC1.3

Module/entity is undefined and created (blackboxed)

HRC1.4

Module/entity is empty (blackboxed)

HRC1.5

Module/entity is referenced recursively (blackboxed)

HRC2.1

Module/entity instantiated from un-imported library

HRC2.2

Module/entity exists in library and design

HRC2.3

Module/entity is renamed

HRC2.4

Ambiguous component is instantiated

HRC2.6

Multiple component is declared

HRC3.1

Module instance has different number of arguments

HRC3.2

Component is instantiated without specifying any port connection

HRC3.2a

Module/entity has no I/O ports

HRC3.3

Undefined named port connection

HRC3.4

Duplicate port connection is detected

HRC3.4a

Actual net is connected to more than one port

HRC3.5a

Open input/inout port connection is detected

HRC3.5b

Open output port connection is detected

HRC3.5c

Expression to null port connection is detected

HRC3.6

Port connection width mis-matches. Undriven signals are floating

HRC3.7

Boundary port direction might not be correct

HRC3.8

Port positional association occurred in instantiation

HRC3.9

Constraint contains floating net

May 2008

551

Product Version 7.2


Rule Number

Message

HRC3.10

Input port connects to instance output pin. This might cause multiple drivers to the net

HRC3.11

Too many actuals connect to formals

HRC3.12

Port declaration error

HRC3.13

Usage of ’const ref’ port is treated as ’input’ port

HRC4

Multiple root modules/entities are found

HRC5

DesignWare is referenced but not defined

HRC6.1

Mapping empty edif cell to parameterized module is not supported

HRC7

Modules specified by the ‘add notranslate modules’ command cannot be found

May 2008

552

Product Version 7.2


HRC1.1 Message Module/entity is not loaded due to unsupported construct (blackboxed)

Default Severity Warning Description The design includes one or more modules or entities that contain unsupported constructs. The checker will blackbox all modules and entities that contain unsupported constructs. Example In the following example, real value 50.2 is an unsupported construct (see lines 7 and 8)(in bold). module test (clk,in1,out0); input clk,in1; output out0; reg out0; real r1; always @ ( posedge clk ) begin if (r1 > 50.2) begin out0 <= in1; end end endmodule

May 2008

553

Product Version 7.2


HRC1.2 Message Module/entity is not translated (blackboxed)

Default Severity Note Description The design includes one or more modules or entities that were blackboxed with the command: add notranslate module

Example Input: SETUP> add notranslate module SUB SETUP> read design SUB.v -verilog // Note: (HRC1.2) Module/entity not translated (black boxed) (occurrence:1)

May 2008

554

Product Version 7.2


HRC1.3 Message Module/entity is undefined and created (blackboxed)

Default Severity Note Description Indicates that blackboxing was specified for design modules that are referenced but not defined. This message can be generated by the following commands: ■

SET UNDEFINED CELL

■

ADD NOTRANSLATE MODULES

The ADD NOTRANSLATE MODULES command causes undefined modules to be blackboxed. Example In the following example, the design references module SUB on line 9, but it is not defined. module TEST (in0,in1,in2,out0); input in0,in1,in2; output out0; reg out0; always @ ( in0 or in1 ) begin out0 = in0 | in1; end SUB inst1 (.in2(in2)); endmodule

May 2008

555

Product Version 7.2


HRC1.4 Message Module/entity is empty (blackboxed)

Default Severity Warning Description The design includes one or more empty modules or entities. The checker blackboxes all empty modules. Example In the following example, the checker blackboxes the empty SUB module. module SUB (in2, out3); input in2; output out3; endmodule

May 2008

556

Product Version 7.2


HRC1.5 Message Module/entity is referenced recursively (blackboxed)

Default Severity Warning Description The design includes one or more modules that are referenced recursively. The checker blackboxes all recursively referenced modules. Example In the following example, module abc is referenced recursively and will be blackboxed (see line 4). module abc (a,b); input a; output b; abc gen1_x1 (a,b); endmodule

May 2008

557

Product Version 7.2


HRC2.1 Message Module/entity instantiated from un-imported library

Default Severity Warning Description The design includes one or more components that are instantiated, but the checker did not find an imported library containing the components. Example In the following example, component SUB is instantiated but the checker did not find an imported library (see line 8)(in bold). ARCHITECTURE arch OF test IS BEGIN proc2 : PROCESS (in0, in1, sig2) BEGIN out0 <= in0 or in1 or sig2; END PROCESS; sig1 <= in2; inst1 : SUB PORT MAP (in0=>sig1, out0=>sig2); END arch;

May 2008

558

Product Version 7.2


HRC2.2 Message Module/entity exists in library and design

Default Severity Warning Description One or more modules or entities exist in both design and library spaces. The checker selects modules and entities from the design space. Example In the following example, we read in module test for both the library and design spaces. Input: SETUP> read library test.v SETUP> read design test.v

May 2008

559

Product Version 7.2


HRC2.3 Message Module/entity is renamed

Default Severity Warning Description The library space includes one or more modules or entities with the same name. The checker will rename these library modules or entities. Example In the following example, the design includes the entity name e1 in two libraries (lib1 and lib2). Therefore, the checker renames the el entities as follows: ■

From library lib1: ENTITY e1 IS PORT (min1: IN bit; mout1: OUT bit); END; ARCHITECTURE rtl OF e1 IS BEGIN mout1 <= not min1; END;

Library 1: el is renamed lib1_e1 ■

From library lib2: ENTITY e1 IS PORT (min1: IN bit; mout1: OUT bit); END; ARCHITECTURE rtl OF e1 IS BEGIN mout1 <= not min1; END;

Library 2: el is renamed lib2_e2

May 2008

560

Product Version 7.2


HRC2.4 Message Ambiguous component is instantiated

Default Severity Warning Description A library component is instantiated, but more than one library contains the component. Example In the following example, component e1 is instantiated, but both library liba and libb contain the e1 component (see line 15)(in bold). LIBRARY liba; LIBRARY libb; USE liba.pkg.ALL; USE libb.pkg.ALL; ENTITY top IS PORT (in1: IN bit; out1: OUT bit); END; ARCHITECTURE rtl OF top IS COMPONENT e1 PORT(min1: IN bit; mout1: OUT bit); END COMPONENT; BEGIN inst1: e1 PORT MAP (min1=>in1, mout1=>out1); END;

May 2008

561

Product Version 7.2


HRC2.6 Message Multiple component is declared

Default Severity Warning Description A component is declared in more than one library. Example In the following example, In line 13, component c1 is declared in both lib1, package pp1 and lib2, package pp2: library lib1, lib2; use lib1.pp1.all; use lib2.pp2.all; ENTITY top IS PORT ( ccc : IN bit; bbb : IN bit; ooo : OUT bit ); END top; ARCHITECTURE rtl OF top IS BEGIN u0: c1 port map (ccc=>ccc, bbb=>bbb, ooo=>ooo); END rtl;

May 2008

562

Product Version 7.2


HRC3.1 Message Module instance has different number of arguments

Default Severity Warning Description The design includes one or more module instances with arguments that differ from the module definition. Example In the following examples, instance inst1 has 3 connections, but module sub has only 2 ports: module sub (in2,out3); input in2; output out3; assign out3 = in2; endmodule module test (in2,out0); input in2; output out0; sub inst1 (in2,in2,out0); endmodule

May 2008

563

Product Version 7.2


HRC3.2 Message Component is instantiated without specifying any port connection

Default Severity Warning Description The design includes one or more components that are instantiated but do not have a port connection. Example In the following example, module SUB is instantiated, but has no connected ports (see line 4)(in bold). module TEST (in2,out0); input in2; output out0; SUB inst1 (); endmodule

May 2008

564

Product Version 7.2


HRC3.2a Message Module/entity has no I/O ports

Default Severity Warning Description The module has no I/O ports. Example In the following example, module ABC does not have any I/O ports. module ABC; endmodule

May 2008

565

Product Version 7.2


HRC3.3 Message Undefined named port connection

Default Severity Error Description The design includes one or more module instances that refer to undefined ports. Example In the following example, module sub references port in4, but does not define it (see line 4)(in bold). module test(a, b, c, d, e); input a, b, c, d; output e; sub inst0 (.in1(a),.in2(b),.in3(c),.in4(d), .out1(e)); endmodule module sub (in1, in2, in3, out1); input in1, in2, in3; output out1; wire out1; assign out1 = in1 ^ in2; endmodule

May 2008

566

Product Version 7.2


HRC3.4 Message Duplicate port connection is detected

Default Severity Warning Description The design includes duplicate ports that the checker has ignored. Example In the following example, the checker will ignore the duplicate port .c included on line 4. module test (a, b, q); input [3:0] a, b; output [3:0] q; sub sub1 (.c(a), .c(b), .q1(q)); endmodule module sub (c, d, q1); input [3:0] c, d; output [3:0] q1; assign q1 = c | d; endmodule

May 2008

567

Product Version 7.2


HRC3.4a Message Actual net is connected to more than one port

Default Severity Warning Description Actual net is connected to more than one port in module declaration. Example In the following example, din is connected to both .in1 port and .in2 port (see line 1). module sub(.in1(din), .in2(din), .out(dout)); input din; output dout; assign dout = din; endmodule module top(din, dout); input din; output dout; sub sub1(.in1(din), .in2(din),.out(dout)); endmodule

May 2008

568

Product Version 7.2


HRC3.5a Message Open input/inout port connection is detected

Default Severity Warning Description The design includes one or more input or inout ports with open connections. Example In the following example, the connection for port .d is open (see line 4). module test (a, b, q); input [3:0] a, b; output [3:0] q; sub sub1 (.c(a), .d(), .q1(q)); endmodule module sub (c, d, q1); input [3:0] c, d; output [3:0] q1; assign q1 = c | d; endmodule

May 2008

569

Product Version 7.2


HRC3.5b Message Open output port connection is detected

Default Severity Note Description The design includes one or more output ports with open connections. Example In the following example, the connection for port .q1 is open (see line 4). module test (a, b, q); input [3:0] a, b; output [3:0] q; sub sub1 (.c(a), .d(b), .q1()); endmodule module sub (c, d, q1); input [3:0] c, d; output [3:0] q1; assign q1 = c | d; endmodule

May 2008

570

Product Version 7.2


HRC3.5c Message Expression to null port connection is detected

Default Severity Warning Description The design includes one or more null ports with open connections. Example In the following example, the connection between module port c and d is open (see line 4). module test (a, b, q); input [3:0] a, b; output [3:0] q; sub sub1 (a, x, b, q); endmodule module sub (c,, d, q1); input [3:0] c, d; output [3:0] q1; assign q1 = c | d; endmodule

May 2008

571

Product Version 7.2


HRC3.6 Message Port connection width mis-matches. Undriven signals are floating

Default Severity Warning Description The design includes at least one port that has port connection width mis-matches. Example In the following example, port_name out1, which is two-bit, is greater in size than port_expr e, which is one-bit. See line 4 (in bold). module test(a, b, e); input a, b; output e; sub inst0 (.in1(a),.in2(b),.out1(e)); endmodule module sub (in1, in2, out1); input in1, in2 ; output [1:0] out1; wire [1:0] out1; assign out1 = {in1,in2}; endmodule

May 2008

572

Product Version 7.2


HRC3.7 Message Boundary port direction might not be correct

Default Severity Warning Description The design includes one or more module boundary ports that might be declared incorrectly because of their irregular use. Example In the following example, both input in1 and input in2, drive output out0. Thus, the checker interprets this situation to mean that input in2 is incorrectly declared (see lines 4 and 5). module test(in1, in2, out0); input in1, in2; output out0; not U1 (out0, in1); assign out0=in2; endmodule

Note: For multi-driven nets, the checker applies wire-AND resolution by default.

May 2008

573

Product Version 7.2


HRC3.8 Message Port positional association occurred in instantiation

Default Severity Warning Description The design includes one or more module instances that use port positional association. In a positional association, the port_exprs connect to the ports of the module in the specified order. Port positional association syntax: module_name instance_name( port_expr1, port_expr2, …);

Example In the following example, port_expr a connects to port o0 and port_expr b connects to port o1 of module sub. See line 9 (in bold). module sub (o0, o1); output o0, o1; assign o0 = 1'b0; assign o1 = 1'b1; endmodule module test(a, b); output a, b; sub s1(a, b); endmodule

May 2008

574

Product Version 7.2


HRC3.9 Message Constraint contains floating net

Default Severity Warning Description The constraint has floating nets. Example In the following example, val is a floating net (see line 8): module test(in, out); input in; output out; wire val; assign out = in; endmodule append_to module test; $constraint( val == 1'b1); endmodule

May 2008

575

Product Version 7.2


HRC3.10 Message Input port connects to instance output pin. This might cause multiple drivers to the net

Default Severity Warning Description There is an input port connected to an instance output pin. This could cause multiple drivers to the net. Example In the following example, the input pin b is connected to the instance sub output pin o1. In module ABC it is an input pin, and in sub s1 is is an output pin. module sub (o0, o1); output o0, o1; assign o0 = 1'b0; assign o1 = 1'b1; endmodule module ABC(a, b); output a; input b; sub s1(a, b); endmodule

May 2008

576

Product Version 7.2


HRC3.11 Message Too many actuals connect to formals

Default Severity Error Description The number of actuals in the port map is more than the number of formals. Example In the following example, there are three actuals but only two formals (see line 20): entity sub is port ( o0, o1 : out bit ); end sub; architecture arch of sub is begin o0 <= '0'; o1 <= '1'; end arch; entity test is port ( a : out bit; b : out bit; c : in bit ); end test; architecture arch of test is begin u1 : sub port map (o0 => a, o1=> b, o1 =>c); end arch;

May 2008

577

Product Version 7.2


HRC3.12 Message Port declaration error

Default Severity Error Description The external port name specified by .name should not conflict with other internal port names, or other external port names. Example In the following example, you cannot redeclare a1 input a1: module hrc3_12 (.a1(a1)); endmodule;

May 2008

578

Product Version 7.2


HRC3.13 Message Usage of ’const ref’ port is treated as ’input’ port

Default Severity Warning Description The ’const ref’ port is treated as ’input’ port. You will get this message when running the READ DESIGN -systemverilog command to read in the design and there is a violation on this rule. Example In the following example, in line 5, port ’din’ of function func is declared as ’const ref’, it will be treated as ’input’ port. module test(in, out); input in; output reg out; function func; const ref din; begin func = din; end endfunction always @(in) out = func(in); endmodule

May 2008

579

Product Version 7.2


HRC4 Message Multiple root modules/entities are found

Default Severity Warning Description The design includes multiple modules or entities at the top level of hierarchy; thus, any one of them can be designated as the root module. By default, the checker selects the module with the greatest gate count. Example In the following example, the file test.v contains two possible root modules, TEST0 and TEST1. test.v file: module TEST0 (in0,in1,in2,out0); input in0,in1,in2; output out0; assign out0 = in0 | in1; endmodule module TEST1 (in0,in1,in2,out0); input in0,in1,in2; output out0; assign out0 = in0 & in1; endmodule

May 2008

580

Product Version 7.2


HRC5 Message DesignWare is referenced but not defined

Default Severity Warning Description The design includes one or more DesignWare multiplier/divider instances, but does not define them. The checker supplies the missing definition, using a Conformal multiplier definition. Example In the following example, DesignWare multiplier DW02_mult is instantiated (see line 9), but the design does not define it. The checker will supply the missing DW02_mult definition with a Conformal multiplier definition. module test(A,B,TC,PRODUCT); parameter A_width = 8; parameter B_width = 8; input [A_width-1:0] A; input [B_width-1:0] B; input TC; output [A_width+B_width-1:0]

PRODUCT;

DW02_mult mult_1 (A,B,TC,PRODUCT); endmodule

May 2008

581

Product Version 7.2


HRC6.1 Message Mapping empty edif cell to parameterized module is not supported

Default Severity Warning Description The EDIF design includes an empty cell that is an instance of a parameterizable Verilog module, which is not supported. Example In the following example, top.edf is an EDIF file that contains a cell called CTLBLK, which is defined in a Verilog module. CTLBLK module: module CTLBLK( A, SUM ); parameter INIT = 16'h0000; … endmodule

Input: > read design top.edf -golden -edif // Warning: (HRC6.1) Mapping empty edif cell to parameterized module is not supported (occurrence:1)

May 2008

582

Product Version 7.2


HRC7 Message Modules specified by the ‘add notranslate modules’ command cannot be found

Default Severity Warning Description A module cannot be found in the design that was specified with the ADD NOTRANSLATE MODULES command. Example In the following example mod1 is the name of module that does not exist in the design. Input: > add notranslate modules mod1 // Warning: (HRC7) Modules specified by the ‘add notranslate modules’ command cannot be found (occurrence:2)

May 2008

583

Product Version 7.2


Ignored This category of rules applies to designs that include constructs or statements that are either redundant or unsupported, and thus ignored by the checker. The following table lists the Ignored (IGN) rule numbers and messages. The severity level for all IGN rule check messages is warning. Rule Number

Message

IGN1.1

initial assignment is ignored

IGN1.2

final construct is ignored

IGN2.1

Delay value(s) are ignored

IGN2.2

Illegal defparam statement(s) are ignored

IGN2.3

Unsupported defparam statement is ignored

IGN3.1

Duplicated pin/port names are detected and ignored

IGN3.2

Duplicate modules/entities are detected. Subsequent modules/ entities are ignored

IGN3.3

Multiple declarations of same packages are detected. Earlier declarations are ignored

IGN3.4

Duplicate modules/entities are detected. Previous modules/ entities are ignored

IGN3.5

Duplicate modules/entities are detected. Local module/entity is used

IGN3.6

Blackbox is replaced with the current module/entity

IGN4

Attribute instance(s) are ignored

IGN5.1

Liberty state table is ignored with the -nostatetable option

IGN5.2

Liberty attribute is ignored

IGN5.3

Liberty state table contains lowercase value(s) and is ignored

IGN6.1

timeunit statement is ignored

IGN6.2

timeprecision statement is ignored

IGN7.1

trireg net is treated as regular wire net

May 2008

584

Product Version 7.2


IGN1.1 Message initial assignment is ignored

Default Severity Warning Description The initial statement is a SystemVerilog construct for simulation that the checker does not support. Thus, when the checker detects this construct in the syntax, it ignores the entire initial construct. Similarly, the checker reports rule IGN1.2 for the final statement. Example In the following example, the checker ignores the keyword initial. See line 5 (in bold). module test ( clk, din, dout ); input clk, din; output dout; wire dout; initial dout = !din; assign dout = din; endmodule

May 2008

585

Product Version 7.2


IGN1.2 Message final construct is ignored

Default Severity Warning Description The final statement is a SystemVerilog construct for simulation that the checker does not support. Thus, when the checker detects this statement in the syntax, it ignores the entire final statement. Similarly, the checker reports rule IGN1.1 for the initial statement. Example In the following example, the checker ignores the entire final statement. See lines 7, 8, and 9 (in bold). module test(aa, bb, o1, o2); input aa, bb; output o1, o2; assign o1 = aa == bb; assign o2 = aa != bb; final begin $display(“done”); end endmodule

May 2008

586

Product Version 7.2


IGN2.1 Message Delay value(s) are ignored

Default Severity Warning Description The checker has ignored one or more delay values. Example In the following example, the checker ignores delay value #(10). See line 5 (in bold). module test ( clk, din, dout ); input clk, din; output dout; wire dout; not #(10) (dout, din); endmodule

May 2008

587

Product Version 7.2


IGN2.2 Message Illegal defparam statement(s) are ignored

Default Severity Warning Description The design uses one or more defparam keywords illegally. The checker ignores illegally used defparam keywords. Example In the following example, P8P is undefined. The checker will ignore the statement. See line 4 (in bold). module test ( clk, din, dout ); input clk, din; output dout; defparam P8P.INI=8'h88; assign dout = din; endmodule

May 2008

588

Product Version 7.2


IGN2.3 Message Unsupported defparam statement is ignored

Default Severity Warning Description The defparam directive is unsupported and ignored. Example In the following example, defparam is ignored (see line 16): module sub1(aa, oo); parameter NN = 1'b0; input aa; output oo; assign oo = aa & NN; endmodule module sub2(aa, oo); input aa; output oo; sub1 u0 [2:0] (aa, oo); endmodule module sub3(aa, oo); input aa; output oo; sub2 u0(aa, oo); defparam u0.u0[0].NN = 1'b1; endmodule

May 2008

589

Product Version 7.2


IGN3.1 Message Duplicated pin/port names are detected and ignored

Default Severity Warning Description The design includes duplicate pins or ports. Example In the following example, the checker ignores the duplicated port dout (see the first line) module test ( dout, clk, din, dout ); input clk, din; output dout; reg dout; always @(posedge clk) dout <= din; endmodule

May 2008

590

Product Version 7.2


IGN3.2 Message Duplicate modules/entities are detected. Subsequent modules/entities are ignored

Default Severity Warning Description The design includes duplicate modules or entities. The checker ignores duplications. Example In the following example, the design duplicates module test. The checker ignores the second module test. Note: Ellipses ( … ) denote characters that are present in the file, but not shown in this example. module test ( clk, din, dout ); … endmodule module test ( clk, din, dout ); … endmodule

May 2008

591

Product Version 7.2


IGN3.3 Message Multiple declarations of same packages are detected. Earlier declarations are ignored

Default Severity Warning Description There are multiple declarations of the same package. The checker ignores earlier declarations. Note: Ellipses ( … ) denote characters that are present in the file, but not shown in this example. Example In the following example, the first declaration for pkg is ignored. package pkg is CONSTANT val1 : bit := ’1’; end pkg; package pkg is CONSTANT val1 : bit := ’0’; end pkg;

May 2008

592

Product Version 7.2


IGN3.4 Message Duplicate modules/entities are detected. Previous modules/entities are ignored

Default Severity Warning Description There are multiple definitions for a module or entity. The checker takes the last definition and ignores previous ones. This usually occurs when you use the -lastmod option with the READ DESIGN command. Example In the following example, the checker ignores the first definition for test when you use the read design -lastmod test.v -replace command. module test ( clk, din, dout ); input clk, din; output dout; reg dout; always @(posedge clk) dout <- din; endmodule module test (clk, din, dout ); input clk, din; output dout; reg dout; always @(posedge clk) dout <= din; endmodule

May 2008

593

Product Version 7.2


IGN3.5 Message Duplicate modules/entities are detected. Local module/entity is used

Default Severity Warning Description Duplicate modules are found and the Conformal software uses the local module. If you want to use the local module, you must use the read design -localref command. Example In the following example, you can use read design -localref to use local module sub1 (see lines 9 for each of the following files). For each file, the instantiation of sub1 in lines 9 will use the sub1 defined in lines 1 (module sub1(aa, oo)). File mod1.v module sub1(aa, oo); input aa; output oo; assign oo = aa; endmodule module mod1(aa, oo); input aa; output oo; sub1 u0 (aa, oo); endmodule

File mod2.v module sub1(aa, oo); input aa; output oo; assign oo = !aa; endmodule module mod2(aa, oo); input aa; output oo; sub1 u0 (aa, oo); endmodule

May 2008

594

Product Version 7.2


IGN3.6 Message Blackbox is replaced with the current module/entity

Default Severity Warning Description The blackbox module is replaced by a non-blackbox module. Example In the following example, same module, but the first one is a blackbox, so this will replace the module sub1 in mod2.v will replace the modue sub1 in mod1.v. Use read design -bboxsolver to replace sub1 with a non-blackbox model File mod1.v: module sub1(aa, oo); input aa; output oo; // this is a bbox endmodule

File mod2.v: module sub1(aa, oo); input aa; output oo; assign oo = !aa; endmodule

May 2008

595

Product Version 7.2


IGN4 Message Attribute instance(s) are ignored

Default Severity Warning Description The checker has ignored one or more attribute instances. Example In the following example, the checker ignores the attribute instance (* a = b *). See line 4. module test(a, b); input a; output b; (* a = b *) assign b = a; endmodule

May 2008

596

Product Version 7.2


IGN5.1 Message Liberty state table is ignored with the -nostatetable option

Default Severity Note Description A Liberty file contains a state table and is ignored due to the -nostatetable option specified in the READ DESIGN or READ LIBRARY command. The checker does not support state tables. Example In the following example, while reading the Liberty library lsi_10k.lib, the checker encountered 17 occurrences of the unsupported state table. Refer to the state table example below. Input: SETUP>read lib -lib lsi_10k.lib // Parsing file lsi_10k.lib… // Warning: (IGN5.1) Liberty State Table is not supported and is ignored (occurrence:17)

State Table Example: statetable ( " D CP ", " Q QN") { table : " - ~R : - - : N N, \ H/L R : - - : H/L L/H"; }

May 2008

597

Product Version 7.2


IGN5.2 Message Liberty attribute is ignored

Default Severity Ignore Description The Liberty attribute is ignored. Example Some unsupported attributes are: poly_template hyperbolic_noise_above_high hyperbolic_noise_low hyperbolic_noise_high steady_state_current_high steady_state_current_low steady_state_current_tristate

May 2008

598

Product Version 7.2


IGN5.3 Message Liberty state table contains lowercase value(s) and is ignored

Default Severity Warning Description The parser found lowercase value(s) in the truth table of the statetable. These must be changed to uppercase. Example In the following example, lines 2 and 3 shows that the edge value(s) ’~r’ and ‘r’ are written in lowercase, which should be changed to uppercase: statetable( " D CP" , " Q QN" ) { table : " - ~r : - - : N N,\ H/L r : - - : H/L L/H" ; }

May 2008

599

Product Version 7.2


IGN6.1 Message timeunit statement is ignored

Default Severity Warning Description The timeunit statement is a SystemVerilog construct for simulation that the checker does not support. When the checker detects this statement in the syntax, it ignores the entire timeunit statement. Similarly, the checker reports rule IGN6.2 for the timeprecision statement. Example In the following example, the checker ignores the timeunit statement on line 2: module test(aa, bb, o1, o2); timeunit 1ps; input aa, bb; output o1, o2; assign o1 = aa == bb; assign o2 = aa != bb; endmodule

May 2008

600

Product Version 7.2


IGN6.2 Message timeprecision statement is ignored

Default Severity Warning Description The timeprecision statement is a SystemVerilog construct for simulation that the checker does not support. When the checker detects this statement in the syntax, it ignores the entire timeprecision statement. Similarly, the checker reports rule IGN5.3 for the timeunit statement. Example In the following example, the checker ignores the timeprecision statement on line 2: module test(aa, bb, o1, o2); timeprecision 0.1ps; input aa, bb; output o1, o2; assign o1 = aa == bb; assign o2 = aa != bb; endmodule

May 2008

601

Product Version 7.2


IGN7.1 Message trireg net is treated as regular wire net

Default Severity Warning Description A trireg net can model a charge storage node whose charge decays over time. The Conformal software does not support charge storage and charge decays. As a result, the software treats a trireg net as regular wire net. Example In the following example, the checker ignores the trireg statement on line 3 (in bold). module test (clk, in1, out1); input clk; input trireg in1; output reg out1; always @(clk) out1 = in1; endmodule

May 2008

602

Product Version 7.2


Register Transfer Level This category of rules applies to designs that are written in the register transfer level of abstraction. The following table lists the Register Transfer Level (RTL) rule numbers and messages. Rule Number

Message

RTL1.1

Variable/signal is assigned by more than one concurrent statement

RTL1.2

Variable/signal is assigned by multiple non-blocking assignments

RTL1.2a

Variable/signal on instance INOUT port might have multiple drivers

RTL1.3

Variable/signal is assigned by both blocking and non-blocking assignments

RTL1.4

Assignment with LHS bit width is greater than RHS bit width

RTL1.5a

Assignment with RHS bit width is greater than LHS bit width

RTL1.5b

Potential loss of RHS msb or carry-out bit

RTL1.6

Blocking assignment is in sequential always block

RTL1.7

Non-blocking assignment is in combinational always block

RTL1.8

Latch is assigned by blocking assignments

RTL1.9

Parameter bit width does not match RHS bit width

RTL1.11

Variable is assigned by both continuous and procedural statements

RTL1.12

variable(SV:logic/bit) is assigned by multiple continuous statements

RTL1.13

Mismatched enumeration types are in the assignment

RTL1.14

Mismatched enumeration types are in the expression

RTL2.1

Variable is referenced before the assignment

RTL2.1a

Variable is referenced before assignment in subprogram. Possible simulation mismatch

RTL2.2

Variable is referenced but never assigned

RTL2.3

Externally defined signal reference is not supported

RTL2.4

Externally defined signal reference is supported

RTL2.5

Undriven net is detected

RTL2.6

Shared variables are not supported

May 2008

603

Product Version 7.2


Rule Number

Message

RTL2.7

Dynamic slice is not supported

RTL2.8

’BUS’ and ’REGISTER’ signal type are not supported for synthesis

RTL2.9

Guarded assignment requires GUARD signal

RTL2.10

GUARD is not declared

RTL2.11

Implicitly declared GUARD signal cannot be updated

RTL2.12

Illegal redeclaration of GUARD signal

RTL2.13

Undriven pin is detected

RTL3.1

Variable/signal is unassigned in asynchronous set/reset

RTL3.2

Assignment of X is in asynchronous set/reset branch

RTL3.3

Non-constant value assignment is in asynchronous set/reset value

RTL3.4

DFF/DLAT is with both asynchronous set and reset connections

RTL3.5

Variable/signal is assigned without using asynchronous set/reset

RTL4.1

Enum encoding is applied to enum type

RTL4.2

Multiple wait statements. FSM encoding might be different

RTL4.3

Enum value size is different than the declared data type

RTL4.4

Encoding format has too many values

RTL5.1

Overlapped case items are in parallel case statement

RTL5.2

Non-binary case items are in case statement

RTL5.3

Case expressions/items are resized

RTL5.4

Partial case items are in full case statement

RTL6.1

X created due to the assignment of value X

RTL6.2

Integer value range constraint is added

RTL6.3

X created when divisor equals to zero

RTL6.4

Enum value constraint is added

RTL6.5

priority if and unique if statements are incomplete

RTL6.6

unique if statements have redundant or overlapping conditions

RTL7.1

Design includes comparison that uses X or Z values

May 2008

604

Product Version 7.2


Rule Number

Message

RTL7.2

Gate or transistor primitive is using weak attributes

RTL7.3

Array index in RHS might be out of range

RTL7.4

Array index in LHS might be out of range

RTL7.5

Input signal is assigned by logic values

RTL7.6

Value X or Z is treated as 0 in unary/binary expressions

RTL7.7

Real number rounded to integer value

RTL7.8

Overflowed integer is truncated

RTL7.9

Sign overflowed integer is truncated

RTL7.10

Comparison with signed and unsigned operands

RTL7.11

Implicit signed expression is converted to unsigned

RTL7.12

Unsized integer number is truncated to 32 bits

RTL7.13

Logical operator is applied to multiple-bit operand

RTL7.14

Loop exceeds maximum iterations

RTL7.15

Null slice is not supported

RTL7.16

Variable index is out of the defined range

RTL7.17

Exponentiation operator is unsupported

RTL7.18

Argument size to integer type conversion is too large

RTL7.19

Added constraint on integer overflow for arithmetic operation ADD/SUB

RTL7.20

Size value in size’(expr) casting is too large

RTL7.21

Real variables are not supported

RTL8.1

Multiple multipliers/dividers are in module/entity

RTL8.2

Latch(es) are inferred due to an incomplete conditional statement

RTL8.3

Unreachable DFF/DLAT is removed

RTL8.4

Unreachable DFF/DLAT is kept

RTL8.5

Implicit signed multiplier is detected in module/entity

RTL9.1

Instance inout/output port has dynamic indexing. Treated as floating

RTL9.2

Design has irregularly used inout/output expression

May 2008

605

Product Version 7.2


Rule Number

Message

RTL9.3

Supply0/supply1 is converted into a wire

RTL9.4

Supply0/supply1 net is not a module port

RTL9.5

Power pin is converted to an input pin

RTL9.7

Cannot read value from OUT port

RTL9.8

Set Liberty pin direction to output because it has an output function

RTL9.9

Extra ’;’ is detected in port list

RTL9.10

Liberty cell does not use any input pin

RTL9.11

Liberty Master-Slave DFF cell clock phase does not match the timing table

RTL9.12

Liberty cell with internal_node does not have correct statetable

RTL9.13

Set liberty cell to blackbox because some of its output pins have no function

RTL9.14

Liberty cell has duplicate signal (pin/member)

RTL10

Both posedge and negedge are used in different always/process

RTL11

Incomplete condition is in a function/procedure/task block

RTL12

Referenced variable(s)/signal(s) are not in sensitivity list

RTL12.1

Constant object is in sensitivity list

RTL13

For loop condition is always false

RTL13.1

The FOR-LOOP index should not be assigned within the loop itself

RTL13.2

The evaluation of for-loop condition is not constant

RTL14

Signal with fanin drive and no fanout load is detected

RTL14.1

Fanout load of the signal is removed

RTL15

Clock and asynchronous set/reset expression must be one bit wide

RTL15.1

Else branch of event controlled if statement is not supported

RTL15.2

Sensitivity/clock style is unsupported

RTL16.1

Non-local variable is read in a function body

RTL16.2

Non-local variable is assigned in a function body

RTL17

Variable size exceeds the maximum limit

May 2008

606

Product Version 7.2


Rule Number

Message

RTL17.1

Expression size exceeds the maximum limit

RTL18.1

Package is not an IEEE standard

RTL18.2

Function definition has empty body

RTL18.3

Function call does not refer to a function definition

RTL18.4

Ignoring resolution function. This might cause mismatches between simulation and synthesis

RTL19.1

Identifier is a reserved keyword and might conflict in designs with mixed languages

RTL20.1

Pre-defined attribute is not supported

RTL20.2

Function is not supported

RTL20.3

Could not find configuration

May 2008

607

Product Version 7.2


RTL1.1 Message Variable/signal is assigned by more than one concurrent statement

Default Severity Warning Description The design includes one or more cases where a variable or signal is assigned by two or more concurrent statements. Example In the following example, the design concurrently assigns output out0. See lines 4 and 5 (in bold). module SEN (clk,rst,in0,in1,out0); input clk,rst,in0,in1; output out0; assign out0 = in0 & in1; assign out0 = in1 & in0; endmodule

May 2008

608

Product Version 7.2


RTL1.2 Message Variable/signal is assigned by multiple non-blocking assignments

Default Severity Warning Description The design includes one or more cases where a variable or signal is assigned by two or more non-blocking assignments. Example In the following example, variable out0 is assigned by a non-blocking assignment. See lines 7 and 8 (in bold). module VLGT (clk,rst,in0,in1,out0); input clk,rst,in0,in1; output out0; reg out0; always @(posedge clk) begin out0 <= in0 & in1; out0 <= in1 & in0; end endmodule

May 2008

609

Product Version 7.2


RTL1.2a Message Variable/signal on instance INOUT port might have multiple drivers

Default Severity Warning Description The variable or signal on the INOUT instance port might have multiple drivers. Example In the following example, in line 4 , ports VSSA and VSSG are defined as INOUT ports in the library file: module mod1_G(Y,A,VDDA,VSSA,VDDG,VSSG); input A, VDDA, VSSA, VDDG, VSSG; output Y; KAQ2 I0(.Y(I0_Y), .A(A), .VDD_A(VDDA), .VSS_A(VSSA), .VDD_G(VDDG), \ .VSS_G(VSSG)); KAQ2 I2(.Y(Y), .A(I0_Y), .VDD_G(VDDG), .VSS_G(VSSG), .VDD_A(VDDA), \ .VSS_A(VSSA)); end endmodule;

May 2008

610

Product Version 7.2


RTL1.3 Message Variable/signal is assigned by both blocking and non-blocking assignments

Default Severity Warning Description The design includes one or more cases where a variable or signal is assigned by both blocking and non-blocking assignments. Example On line 7 of the following example, variable out0 is assigned by a blocking assignment, and on line 9, variable out0 is assigned by a non-blocking assignment. module VGT (rst,in0,in1,out0); input rst,in0,in1; output out0; reg out0; always @(rst or in1 or in0) begin if (rst) out0 = in1 & in0; else out0 <= in0 & in1; end endmodule

May 2008

611

Product Version 7.2


RTL1.4 Message Assignment with LHS bit width is greater than RHS bit width

Default Severity Warning Description The design includes one or more assignments with a left-hand-side (LHS) bit width greater than the right-hand-side (RHS) bit width. Example In the following example, the assignment of in0 to out0 has mismatched bit widths. See line 6 (in bold). module VT (clk,in0,out0); input clk,in0; output [3:0] out0; reg [3:0] out0; always @(posedge clk) begin out0 <= in0; end endmodule

May 2008

612

Product Version 7.2


RTL1.5a Message Assignment with RHS bit width is greater than LHS bit width

Default Severity Warning Description The design includes one or more assignments with a right-hand-side (RHS) bit width greater than the left-hand-side (LHS) bit width. Example 1. In the following example, the design assigns a two-bit vector logic 2'b01 to a one-bit output out0 (see line 3). module test(out0); output out0; assign out0 = 2'b01; endmodule

2. In the following Verilog example, the self-determined bit width for the RHS expression is 5, while the LHS is only 4. x[3:0] = a[4:0] + b [4:0];

May 2008

613

Product Version 7.2


RTL1.5b Message Potential loss of RHS msb or carry-out bit

Default Severity Warning Description The design includes one or more assignments where there is potential for the right-hand-side (RHS) to lose its most-significant-bit (MSB) or carry-out bit. Example 1. In the following example, the self-determined bit width of the RHS is 4 and the LHS is also 4; however, x[3:0] does not take the potential carry-out from the RHS. x[3:0] = a[3:0] + b[3:0];

2. In the following Verilog example, the self-determined bit width for the RHS is 4 and the LHS is also 4; however, arithmetically, the product is 8 bits and x[3:0] only takes the lower 4 bits of the total 8 bits. x[3:0] = a[3:0] * b[3:0];

May 2008

614

Product Version 7.2


RTL1.6 Message Blocking assignment is in sequential always block

Default Severity Warning Description The design includes one or more blocking assignments in a sequential always block. Example On lines 7 and 9 of the following example, the design uses blocking assignments: module VLGT (clk,rst,in0,in1,out0); input clk,rst,in0,in1; output out0; reg out0; always @(posedge clk) begin if (rst) out0 = in1 & in0; else out0 = in0 & in1; end endmodule

May 2008

615

Product Version 7.2


RTL1.7 Message Non-blocking assignment is in combinational always block

Default Severity Warning Description The design includes one or more non-blocking assignments in a combinational always block. Example On lines 7 and 9 of the following example, the design uses non-blocking assignments: module VT (sel,in0,in1,out0); input sel,in0,in1; output out0; reg out0; always @(sel or in1 or in0) begin if (sel) out0 <= in1 & in0; else out0 <= in0 & in1; end endmodule

May 2008

616

Product Version 7.2


RTL1.8 Message Latch is assigned by blocking assignments

Default Severity Warning Description The design includes one or more latches that are coded using a blocking assignment. We recommend that sequential elements be coded using a non-blocking assignment rather than a blocking assignment. Example In the following example, latch Q is coded using a blocking assignment (see line 7): module Dlat(data, en, Q); input data, en; output Q; reg Q; always @( en or data) if (en) Q = data; endmodule

May 2008

617

Product Version 7.2


RTL1.9 Message Parameter bit width does not match RHS bit width

Default Severity Warning Description The design includes one or more parameter bit widths that do not match with right-hand-side (RHS) bit widths. Example In the following example, parameter my_values is declared as a 3-bit vector, but was assigned a 4-bit vector (see line 3): module test (Z); output [3:0]Z; parameter signed [2:0] my_values = 4’b1010; assign Z = my_values; endmodule

May 2008

618

Product Version 7.2


RTL1.11 Message Variable is assigned by both continuous and procedural statements

Default Severity Error Description A variable is assigned by both continuous and procedural statements. Example In the following example, variable t1 is assigned in lines 5 and 8. module test (a, b,t1); input a,b ; output t1 ; logic t1 ; assign t1 = a & b; always @(a or b ) begin task1 (t1); end task task1 (output c); begin c = a | b; end endtask endmodule

May 2008

619

Product Version 7.2


RTL1.12 Message variable(SV:logic/bit) is assigned by multiple continuous statements

Default Severity Error Description A variable is assigned by multiple continuous statements. Example In the following example, variable t1 is assigned in lines 5 and 6. module test (a, b,t1); input a,b ; output t1 ; logic t1 ; assign t1 = a & b; assign t1 = a | b; endmodule

May 2008

620

Product Version 7.2


RTL1.13 Message Mismatched enumeration types are in the assignment

Default Severity Error Description There are mismatched enumeration types in the assignment. Example In the following example, In line 5, read and din have mismatched enumeration type. typedef enum {write , add, sub, mult} instr_t; typedef enum {WAIT, LOAD, STORE} state_t; module test(output state_t read, input instr_t din); always_comb read = din; endmodule

May 2008

621

Product Version 7.2


RTL1.14 Message Mismatched enumeration types are in the expression

Default Severity Error Description There are mismatched enumeration types in the expression. Example In the following example, In line 6, enumeration types are mismatched. module test (output integer out1) ; enum {IDLE=2’b00, S1, S2} state; assign state = S1; always @* begin out1 = (state == 4)? 2’b00:state; end endmodule

May 2008

622

Product Version 7.2


RTL2.1 Message Variable is referenced before the assignment

Default Severity Warning Description The design includes one or more variables that are referenced before they are assigned. Example On line 8 of the following example, the design references variable sig1, but does not assign it until line 9: module TPS (clk,in1,in2,out0); input clk,in1,in2; output out0; reg out0; always @ (in1 or in2) begin reg sig1; out0 = sig1; sig1 = in1 | in2; end endmodule

May 2008

623

Product Version 7.2


RTL2.1a Message Variable is referenced before assignment in subprogram. Possible simulation mismatch

Default Severity Warning Description For initialized variable in subprogram, simulation mismatch might occure when the variable is referenced before the assignment. For the Conformal Equivalence Checking software and synthesis tools, the variable will default to 0. However, for simulation, the variable assumes previously assigned value. Example In the following example, in line 16, variable nxt_svl is referenced before assignment. This can cause a simulation or synthesis mismatch. function [11:0] foo; ... reg nxt_svl; begin if (reset) begin ... nxt_svl = 1’b0; ... end else begin ... case (state) state0: if (nxt_svl) ... state5: nxt_svl = 1’b1; ... endfunction

May 2008

624

Product Version 7.2


RTL2.2 Message Variable is referenced but never assigned

Default Severity Warning Description The design includes one or more variables that are referenced but never assigned in the design. Example In the following example, the design references variable da0, but never assigns it: module SEN (clk,rst,out0); input clk,rst; output out0; reg out0; reg da0; always @ ( posedge rst or posedge clk ) begin if (rst) begin out0 <= 1'b0; end else begin out0 <= da0; end end endmodule

May 2008

625

Product Version 7.2


RTL2.3 Message Externally defined signal reference is not supported

Default Severity Warning Description The checker did not support one or more externally defined signal references when they were used in multiple entities. The checker only supports one entity that uses the externally defined signal. Example In the following example, the design references the externally defined signal glob1 in multiple entities, which causes the checker to error out. Note: Ellipses ( … ) denote characters that are present in the file, but not shown in this example. PACKAGE pack IS SIGNAL glob1 : boolean; END PACK; USE work. pack.all; ENTITY test IS … END test; ARCHITECTURE arch OF test IS … glob1 <= in0 or in1; END arch; ENTITY test2 IS … END test2; ARCHITECTURE arch OF test2 IS … glob1 <= in0 or in1; END arch;

May 2008

626

Product Version 7.2


RTL2.4 Message Externally defined signal reference is supported

Default Severity Note Description The checker supports one or more externally defined signal references. The checker only supports the first entity that uses the externally defined signal. Example In the following example, the design uses signal glob1 although it is defined outside entity TEST (see line 13). package pack is signal glob1 : boolean; end pack; use work. pack.all; entity TEST is port ( in0, in1, in2 : in boolean; out0 : out boolean ); end test; architecture arch of test is begin glob1 <= in0 or in1; out0 <= glob1 and in2; end arch;

May 2008

627

Product Version 7.2


RTL2.5 Message Undriven net is detected

Default Severity Warning Description The specified wire is not assigned. It is connected to an object indicating that the wire has been read at least once. Such usage leads to redundant code, undefined states, and errors. To avoid this, assign wires properly. If unassigned wires are not used, remove them. This rule honors the synthesis off or on pragmas. This implies that a wire is considered unassigned when assignment is made inside synthesis off or on pragma and its declaration is outside the pragma. Example In the following example, g1 (line 5) is an undriven net: module unassigned_wire (in1, out1); input in1; output out1; wire g1; assign out1 = in1 & g1; endmodule

May 2008

628

Product Version 7.2


RTL2.6 Message Shared variables are not supported

Default Severity Warning Description Shared variables are not supported. To avoid this error, remodel the design. Example In the following example, shared variable counter (line 8) is not supported: library IEEE; use IEEE.std_logic_1164.all; entity shared_variables is port (DataIn : in integer); end entity shared_variables; architecture shared_variables_arch of shared_variables is subtype ShortRange is integer range 0 to 1; shared variable counter : ShortRange := 0; begin PROC1:process begin counter := counter + 1; wait; end process PROC1; PROC2:process begin counter := counter - 1; wait; end process PROC2; end architecture shared_variables_arch;

May 2008

629

Product Version 7.2


RTL2.7 Message Dynamic slice is not supported

Default Severity Warning Description The left and right bounds of the part range cannot be evaluated to constant values. Such expressions are not supported by synthesis tools and are ignored. Example In the following example, the dynamic slice in line 14 is not supported: Library IEEE; use IEEE.std_logic_1164.all; Entity TEST is Port ( Sdq_data : out std_logic_vector (7 downto 0)); End TEST; Architecture ARCH_TEST of TEST is Type vect_array is array (7 downto 0) of std_logic_vector (7 downto 0); Signal data : vect_array; Begin Process Variable I : integer; Begin Sdq_data (I+7 downto I) <= data (I) (7 downto 0); End process; End ARCH_TEST;

May 2008

630

Product Version 7.2


RTL2.8 Message ’BUS’ and ’REGISTER’ signal type are not supported for synthesis

Default Severity Warning Description The BUS and REGISTER signal type are not supported by the synthesis tools and are ignored. Example In the following example, the bus signal type in line 5 is not supported: entity EG1 is port (a: in BIT; z: out bit); end; architecture RTL of EG1 is signal sig1: bit bus; begin process begin if a = ’1’ then z <= ’1’; else z<= ’0’; end if; end process; end;

May 2008

631

Product Version 7.2


RTL2.9 Message Guarded assignment requires GUARD signal

Default Severity Error Description The GUARD signal is not declared for guarded assignment. Example In the following example, the guarded signal is not declared for line 9’s guarded assignment: entity EG1 is port (a,b: in bit; z: out bit); end; architecture RTL of EG1 is signal val: bit; begin guarded_block: block begin val <= guarded a and b; end block; z <= val; end;

May 2008

632

Product Version 7.2


RTL2.10 Message GUARD is not declared

Default Severity Error Description The GUARD signal is not declared. Example In the following example, the guard signal in line 8 is not declared: entity EG1 is port (a,b: in bit; z: out bit); end; architecture RTL of EG1 is begin guarded_block: block --(a = ’1’) begin z <= ’1’ when guard else ’0’; end block; end;

May 2008

633

Product Version 7.2


RTL2.11 Message Implicitly declared GUARD signal cannot be updated

Default Severity Error Description The implicitly declared GUARD signal cannot be updated. The implicit guard signal will be declared for a guarded block. This is illegal to update the implicitly declared GUARD signal. Example In the following example, the guard signal in in line 8 is illegal: entity EG1 is port (a,b: in bit; z: out bit); end; architecture RTL of EG1 is begin guarded_block: block (a = ’1’) begin guard <= (b= ’1’); z <= ’1’ when guard else ’0’; end block; end;

May 2008

634

Product Version 7.2


RTL2.12 Message Illegal redeclaration of GUARD signal

Default Severity Error Description The redeclaration of GUARD signal is illegal. The implicit GUARD signal will be declared for a guarded block. It is illegal to redeclare GUARD signal. Example In the following example, the guard signal in in line 7 is illegal: entity EG1 is port (a,b: in bit; z: out bit); end; architecture RTL of EG1 is begin guarded_block: block (a = ’1’) signal guard : boolean; begin z <= ’1’ when guard else ’0’; end block; end;

May 2008

635

Product Version 7.2


RTL2.13 Message Undriven pin is detected

Default Severity Warning Description Undriven pin(s) are detected in the design. Example In the following example, pin in1 of instance test is undriven (see line 4): module top (din1, dout1); output dout1; input din1; test t1(.in2(din1),.out1(dout1)); endmodule module test(in1,in2, out1); input in1, in2; output out1; assign out1 = in1 & in2; endmodule

May 2008

636

Product Version 7.2


RTL3.1 Message Variable/signal is unassigned in asynchronous set/reset

Default Severity Warning Description The design includes one or more variables or signals that are unassigned in one of the conditional branches in asynchronous set/reset branches. Example In the following example, the design assigns output out0 in the else branch, but not in the if branch of the asynchronous set/reset. See line 11 (in bold). module SEN (clk,rst,in0,out0,out1); input clk,rst,in0; output out0,out1; reg out0,out1; always @ ( posedge rst or posedge clk ) begin if (rst) begin out1 <= 1'b0; end else begin out0 <= in0; out1 <= !in0; end end endmodule

May 2008

637

Product Version 7.2


RTL3.2 Message Assignment of X is in asynchronous set/reset branch

Default Severity Warning Description The design includes one or more X value assignments in asynchronous set/reset branches. Example In the following example, the design assigns X value to out0. See line 8 (in bold). module OPW (clk,rst,in0,out0); input clk,rst,in0; output out0; reg out0; always @ ( posedge rst or posedge clk ) begin if (rst) begin out0 <= 1'bx; end else begin out0 <= in0; end end endmodule

May 2008

638

Product Version 7.2


RTL3.3 Message Non-constant value assignment is in asynchronous set/reset value

Default Severity Warning Description The design includes one or more non-constant value assignments in asynchronous set/reset branches. Example In the following example, the design assigns a non-constant value to out0. See line 8 (in bold). module OPW (clk,rst,in0,in1,out0); input clk,rst,in0,in1; output out0; reg out0; always @ ( posedge rst or posedge clk ) begin if (rst) begin out0 <= in1; end else begin out0 <= in0; end end endmodule

May 2008

639

Product Version 7.2


RTL3.4 Message DFF/DLAT is with both asynchronous set and reset connections

Default Severity Warning Description The design includes one or more DFFs or DLATs that have both asynchronous set and reset connections. Example On line 8 of the following example, the design uses rst for an asynchronous reset. The design then uses set for an asynchronous set on line 10. module test (clk,set,rst,in0,in1,out0); input clk,set,rst,in0,in1; output out0; reg out0; always @ ( posedge rst or posedge set or posedge clk ) begin if (rst) out0 <= 1'b0; else if (set) out0 <= 1'b1; else out0 <= in0; end endmodule

May 2008

640

Product Version 7.2


RTL3.5 Message Variable/signal is assigned without using asynchronous set/reset

Default Severity Ignore Description Design style check to report if the RTL codes infer to a DFF gate that does not use any asynchronous set or reset signal. Example On line 6 of the following example, the design assigns output out0 without any asynchronous set or reset signal: module SEN (clk,rst,in0,out0); input clk,rst,in0; output out0; reg out0; always @(posedge clk) out0 <= in0; ... endmodule

May 2008

641

Product Version 7.2


RTL4.1 Message Enum encoding is applied to enum type

Default Severity Note Description The design includes one or more ENUM_ENCODING attributes to declare enum type in VHDL. For Verilog, use the synopsys enum directive to declare enum type. Example On line 14 of the following example, the design includes an ENUM_ENCODING attribute to declare enum type: PACKAGE small_1164 IS attribute ENUM_ENCODING : string; TYPE std_ulogic IS ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' ); attribute ENUM_ENCODING of end package;

May 2008

----------

Uninitialized Forcing Unknown Forcing 0 Forcing 1 High Impedance Weak Unknown Weak 0 Weak 1 Don't care

std_ulogic : type is “U D 0 1 Z D 0 1 D”;

642

Product Version 7.2


RTL4.2 Message Multiple wait statements. FSM encoding might be different

Default Severity Warning Description The design includes one or more always/process blocks containing multiple wait statements. The checker creates a Finite State Machine (FSM) when it encounters multiple wait statements. We recommend that you verify that the FSM encoding is what you expected. Example On lines 8 and 12 of the following example, the design uses the wait statement: Module Medge (Clock, Cond, In1, In2, In3, Out1); input Clock, Cond, In1, In2, In3; output Out1; reg Out1; always begin @ (posedge Clock); Out1 = In1; if (Cond) begin @ (posedge Clock); Out1 = In2; end else begin @ (posedge Clock); Out1 = In3; end end endmodule

May 2008

643

Product Version 7.2


RTL4.3 Message Enum value size is different than the declared data type

Default Severity Warning Description The enum value size is different than the declared data type. Example The declared type ‘light’ size is 2, but the enum value GREEN size is 3: module enum10(input clk,output reg out1); typedef enum reg signed [1:0] { RED = 2'sb10,YELLOW,GREEN = 3'b000} light; light mylight; always @(clk) begin mylight=RED; out1 = mylight; end endmodule

May 2008

644

Product Version 7.2


RTL4.4 Message Encoding format has too many values

Default Severity Warning Description There are more encoding values than necessary. Example In line 3, there are more encoding values than are needed: attribute ENUM_ENCODING : string; type fifo_valid_state_type is (full1, full2, full3, empty); attribute ENUM_ENCODING of fifo_valid_state_type : type is "0001 0011 0010 0000 0100 0101 0111 0110 1110";

May 2008

645

Product Version 7.2


RTL5.1 Message Overlapped case items are in parallel case statement

Default Severity Warning Description The design includes multiple case_items that potentially match the case_expressions in parallel case statements. A parallel case statement syntax: case (case_expression) //synopsys Parallel_case case_item1 : //case_item_statement1; case_item2 : case_item_statement2; default : case_item_statement3; endcase

Example On lines 8 and 9 of the following example, case_items 2'b1? and 2'b?1 match the case_expression sel when sel is equal to 2'b11. module test ( a, b, sel, out0); input a, b; input [1:0] sel; output out0; reg out0; always @(sel or a or b) begin casez (sel) //synopsys parallel_case 2'b1? : out0 = a; 2'b?1 : out0 = b; default: out0 = 1'bx; endcase end endmodule

May 2008

646

Product Version 7.2


RTL5.2 Message Non-binary case items are in case statement

Default Severity Warning Description The design includes one or more case_items with non-binary values in case statements. A case statement syntax: case (case_expression) case_item1 : case_item_statement1; case_item2 : case_item_statement2; default : case_item_statement3; endcase

Example In the following example, the design includes a Z value for a case_item. See line 9 (in bold). module test ( a, b, input a, b, c; input sel; output out0; reg out0; always @(sel or a case(sel) 1'b1 : out0 1'bz : out0 default: out0 endcase end endmodule

May 2008

c, sel, out0);

or b or c) begin = a; = b; = c;

647

Product Version 7.2


RTL5.3 Message Case expressions/items are resized

Default Severity Warning Description The design includes one or more case item sizes that do not match the case expression sizes. Example On lines 8 and 10 of the following example, the case items have a single bit, while the case expression (line 3) is a 2-bit vector. module test ( a, b, c, sel, out0); input a, b, c; input [1:0] sel; output out0; reg out0; always @(sel or a or b or c) begin case(sel) 1’b1 : out0 = a; 1’b0 : out0 = b; default: out0 = c; endcase end endmodule

May 2008

648

Product Version 7.2


RTL5.4 Message Partial case items are in full case statement

Default Severity Note Description The design includes a partial case enumeration in a full case statement. Example The following example contains a potential partial case enumeration. The 4’b00 and 4’11 case items are not enumerated in the full_case statement(in bold). module test (out, a, b, select); output out; input a, b; input [1:0] select; reg out; always @(select or a casez (select) /* 4’b01: out = 4’b10: out = endcase end endmodule

May 2008

or b) begin full_case */ a; b;

649

Product Version 7.2


RTL6.1 Message X created due to the assignment of value X

Default Severity Warning Description One or more assignments use value X. The checker generates a don’t care for any value X assignment. Example In the following example, the design assigns a 1'bx value to output o. See line 6 (in bold). module test(o,i); output o; reg o; input i; always o = 1'bx; endmodule

May 2008

650

Product Version 7.2


RTL6.2 Message Integer value range constraint is added

Default Severity Warning Description When you read in the design, you specified a constraint on integers for a specific range. The switch of the command that you used to apply the constraint is -rangeconstraint. Example In the following example, integer int1 has a value range from -1024 to 1024 (see line 4). ENTITY PORT (

test IS

clk : IN std_ulogic ; int1 : IN integer range -1024 to 1024 ; bufferA : BUFFER std_ulogic ); END test; ARCHITECTURE arc OF test IS BEGIN PROCESS BEGIN IF clk = '1' AND clk'event THEN IF int1 = 4095 THEN bufferA <= '0' ; ELSE bufferA <= '1' ; END IF ; END IF ; END PROCESS; END;

Input: SETUP>read design test.vhdl -vhdl -rangeconstraint

May 2008

651

Product Version 7.2


RTL6.3 Message X created when divisor equals to zero

Default Severity Warning Description The design contains one or more divisors that are signals or variables, and not constants. Thus, there is a chance that they will equal zero. In these cases, the checker creates X. Example In the following example, the divisor B is an input signal, thus the checker creates X (see line 4). module test(A, B, QUOTIENT); input [7:0] A, B; output [7:0] QUOTIENT; assign QUOTIENT = A / B; endmodule

May 2008

652

Product Version 7.2


RTL6.4 Message Enum value constraint is added

Default Severity Warning Description The checker recognized the synopsys enum fsm_state directive, thus it added a constraint to Enum value. Example In the following example, on lines 3 through 9 (in bold), the checker constrains enum states ra_state and next_state to a one-hot condition. module test (masterclk, reset_n, mem_write); … parameter [4:0] // synopsys enum fsm_states iddle = 5’b00001, step01 = 5’b00010, step02 = 5’b00100, step03 = 5’b01000, step04 = 5’b10000, reg [4:0] /* synopsys enum fsm_states */ ra_state, next_state; always @(ra_state or mem_write) begin case (ra_state) iddle: begin tmp = mem_write; next_state = step01; end step01: begin tmp = 1’b0; next_state = step02; end … default: begin tmp = mem_write; next_state = iddle; end endcase end … endmodule

May 2008

653

Product Version 7.2


RTL6.5 Message priority if and unique if statements are incomplete

Default Severity Warning Description There are incomplete priority if and unique if SystemVerilog statements. The priority if and unique if SystemVerilog statements ensure that all conditions are complete; they ensure that default else statements exist and if/else if conditions cover all conditions. Example In the following example, the incomplete priority if statement in line 4 triggers this rule check, while the complete priority if statement in lines 11-12 do not trigger this rule check. module test1(input aa, output oo); reg oo; always @* begin priority if (aa) oo = !aa; // incomplete condition end endmodule module test2(input aa, output oo); reg oo; always @* begin priority if (aa) oo = !aa; else oo = aa; // complete condition end endmodule

May 2008

654

Product Version 7.2


RTL6.6 Message unique if statements have redundant or overlapping conditions

Default Severity Note Description There are possible redundant or overlapping conditions in unique if statements. Structural checks generate this message; a more detailed analysis is done during compare. Example In the following example, there are overlapping conditions in the unique if statement that will cause a rule check report. See line 5. module test3(input aa, bb, output oo); reg oo; always @* begin unique if (aa && bb) oo = !aa; else if (aa || bb) oo = aa; else oo = 1’b0; end endmodule

May 2008

655

Product Version 7.2


RTL7.1 Message Design includes comparison that uses X or Z values

Default Severity Warning Description The design includes one or more comparisons that use X or Z values as comparators. Example In the following example, the design compares reset rst with an X value. See line 7 (in bold). module test (clk,rst,in0,out0); input clk,rst,in0; output out0; reg out0; always @ ( posedge clk ) begin if (rst == 1'bx) out0 <= 1'b0; else out0 <= in0; end endmodule

May 2008

656

Product Version 7.2


RTL7.2 Message Gate or transistor primitive is using weak attributes

Default Severity Warning Description One or more gates or transistor primitives are using weak attributes. Note: Not all weak attributes will be used. In the case of a multiple-driven net, the gate with the strong attribute will drive the output. Example In the following example, the design uses a weak attribute for a buffer primitive. See line 5 (in bold). module test (clk,rst,in0,out0); input clk,rst,in0; output out0; wire out0; buf (weak0, weak1) (out0, in0); endmodule

May 2008

657

Product Version 7.2


RTL7.3 Message Array index in RHS might be out of range

Default Severity Warning Description The design includes an index where its right hand side might be out of range. Example In the following example, it uses an index where its right hand side might be out of range. See line 10(in bold). module test (clk, idx, in0, out0); input clk; input [3:0] idx; input [3:0] in0; output out0; reg out0; always @ ( posedge clk) begin out0 <= in0[idx]; end endmodule

May 2008

658

Product Version 7.2


RTL7.4 Message Array index in LHS might be out of range

Default Severity Warning Description The design includes an index where its left hand side might be out of range. Example In the following example, it uses an index where its left hand side might be out of range. See line 10(in bold). module test (clk, idx, in0, out0); input clk; input [3:0] idx; input in0; output [3:0] out0; reg [3:0] out0; always @ ( posedge clk) begin out0[idx] <= in0; end endmodule

May 2008

659

Product Version 7.2


RTL7.5 Message Input signal is assigned by logic values

Default Severity Warning Description The design includes one or more primary input signals that are assigned by logic values. Example In the following example, the design assigns logic value 1 to primary input a. See line 4 (in bold). module test(a, b); input a; output b; assign a = 1'b1; assign b = 1'b1; endmodule

May 2008

660

Product Version 7.2


RTL7.6 Message Value X or Z is treated as 0 in unary/binary expressions

Default Severity Warning Description The checker treats the 1’bx or 1’bz in unary/binary expression as 1’b0. Example In the following example, on line 7 (in bold), the 1’bx value in the conditional expression is treated as 1’b0. Thus, input in2 will be assigned directly to output out. module test(in1, in2, out); input in1, in2; output out; reg out; always begin out = 1’bx ? in1 : in2; end endmodule

May 2008

661

Product Version 7.2


RTL7.7 Message Real number rounded to integer value

Default Severity Warning Description The checker rounds real numbers to integer values. Example In the following example, on line 2 (in bold), input din has a real value of 2.2. However, the checker truncates this value at .2. module test (din, dout); input [2.2:0] din; output [2:0] dout; assign dout = din; endmodule

May 2008

662

Product Version 7.2


RTL7.8 Message Overflowed integer is truncated

Default Severity Warning Description The design contains one or more integers that overflow. Thus, the checker truncates them. Example In the following example, the checker truncates integer b;. See line 3. module test (b); output b; integer b; always b = 5147483648; endmodule

May 2008

663

Product Version 7.2


RTL7.9 Message Sign overflowed integer is truncated

Default Severity Warning Description The design contains one or more integers that overflow at the sign bit. Thus, the checker truncates them. Example In the following example, the checker truncates integer b;. See line 3 (in bold). module test (b); output b; integer b; always b = 2147483648; endmodule

May 2008

664

Product Version 7.2


RTL7.10 Message Comparison with signed and unsigned operands

Default Severity Warning Description The design includes both signed and unsigned operands used in a relational expression. Example In the following example, the checker compares the signed operand in1 (on line 4) to the unsigned operand in2 (on line 5). The checker converts in1 to an unsigned operand first, and then compares it with in2. An unsigned comparison results. module test (out0, in1, in2); output out0; input signed [31:0] in1; input unsigned [31:0] in2; assign out0 = in1 > in2; endmodule

May 2008

665

Product Version 7.2


RTL7.11 Message Implicit signed expression is converted to unsigned

Default Severity Warning Description The design includes a signed expression that the checker has converted to an unsigned expression implicitly. Example In the following example, the checker converts the signed operand in1 to unsigned in the conditional expression. See line 7 (in bold). module test (out0, cond1, in1); output unsigned [32:0] out0; input cond1; input signed [31:0] in1; assign out0 = cond1 ? out0 : in1; endmodule

May 2008

666

Product Version 7.2


RTL7.12 Message Unsized integer number is truncated to 32 bits

Default Severity Warning Description The checker truncated an unsized integer literal to 32-bit. Example In the following example, the checker truncates ’hf00000000 to h00000000. See line 2. module test6(input aa, output oo); assign oo = (’hf00000000 > 32’h0)?aa:!aa;

May 2008

667

Product Version 7.2


RTL7.13 Message Logical operator is applied to multiple-bit operand

Default Severity Warning Description The logical operator is applied to multiple-bit operand when the operand is not a single-bit expression. Example In the following example, the logical operator && is applied to multiple-bit operand tmp (see line 5): module test(in, out); input in; output out; wire [2:0] tmp; assign out = in && tmp; endmodule

May 2008

668

Product Version 7.2


RTL7.14 Message Loop exceeds maximum iterations

Default Severity Warning Description An index variable should be sufficiently large enough to hold both the initial and the final values that the loop index could take. If the index variable is small, the loop will be executed fewer number of times. This can lead to unpredictable behavior. .Example In the following example, ’I’ can only take values from 0 to 3 as its size 2 bits. Line 8 of the code shows that the index of the for loop ranges from 0 to 5. Since the loop index variable ’I’ is not large enough to hold the final value of the loop index, the loop may never terminate. module neg_BITUSD_loop_idx_bitsel(a, b, c); input [3:0] a, b; output [3:0] c; reg [3:0] c; always @(a or b) begin: P reg [1:0] I; for (I = 2; I <= 5; I = I + 1) begin: loop2 c[I] = a[I] | b[I]; end end endmodule

May 2008

669

Product Version 7.2


RTL7.15 Message Null slice is not supported

Default Severity Warning Description The specified datatype or node is defined with a null range, and it cannot hold any value. In VHDL, a range is considered to be a null range, if the subset of values specified by the range is empty (a decreasing range with a ’to’ direction, or an increasing range with a ’downto’ direction). Examples of null range are (3 to 0) and (1 downto 8). The synthesis tools do not support null range. Example In the following example, the null slice in line 9 is not supported: entity TEST1 is port ( in1: in integer ; out2: buffer bit; out3: out bit ) ; end TEST1 ; architecture ARCH_TEST1 of TEST1 is type myvector is array(0 downto 7) of BIT; begin process (in1) variable vec: myvector; variable index: integer; variable temp: bit; begin vec:= (’1’, ’1’, ’1’, ’1’, ’1’, ’1’, ’1’, ’1’) ; temp:= vec(in1); end process; end ARCH_TEST1 ;

May 2008

670

Product Version 7.2


RTL7.16 Message Variable index is out of the defined range

Default Severity Warning Description A bit or part select reference in an expression is found to have an index specification outside of the defined range of the variable. This can lead to unexpected simulation or synthesis results. Cadence recommends that you change the reference so that the index or subrange falls within the valid range. Example In the following example, index [4] is out of a’s range (see line 7): module test1 (a, b, out1); input [3:0] a; input [3:0] b; output out1; reg out1; always @(a or b) out1 = a[4] & b[3]; endmodule

May 2008

671

Product Version 7.2


RTL7.17 Message Exponentiation operator is unsupported

Default Severity Warning Description Some synthesis tools do not support the exponentiation operator. Cadence recommends that you remodel your HDL source code. Example In the following example, a ** 5 (line 14) is not supported: Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity TEST1 is port ( a : in INTEGER; out1 : out INTEGER ) ; end TEST1 ; architecture ARCH_TEST1 of TEST1 is begin process (a) begin out1 <= a ** 5; end process; end ARCH_TEST1 ;

May 2008

672

Product Version 7.2


RTL7.18 Message Argument size to integer type conversion is too large

Default Severity Warning Description The argument width is too large for conversion ’CONV_INTEGER’. The maximum argument width is 32 for a ’signed’ argument or 31 for an ’unsigned’ argument. The Logical Equivalency Checker does truncations for the following: ■

unsigned (31 bits) conversion to integer

■

signed (32 bits) conversion to integer

Example In the following example, on line 10, the argument for ’conv_integer’ is 32 bit width ’unsigned’, is too large (maximum if 31 for an ‘unsigned’ argument). library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity IntCtrl is port( IRQ : out integer; IntCtrlReg_th : in std_logic_vector(31 downto 0)); end IntCtrl; architecture rtl of IntCtrl is begin IRQ <= conv_integer(unsigned(IntCtrlReg_th)); end rtl;

May 2008

673

Product Version 7.2


RTL7.19 Message Added constraint on integer overflow for arithmetic operation ADD/SUB

Default Severity Warning Description A constraint is added on the integer overflow for the ADD or SUB arithmetic operation. Example In the following example, in line 11, if (CONV_INTEGER(a) + b) > 2**31-1 (overflow), the software can derive a constraint on this overflow, and then compare can ignore the different interpretation synthesis tool made when (CONV_INTEGER(a) + b) > 2**31-1 occurs. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY test IS PORT ( a, b : IN natural; z : OUT integer ); END test; ARCHITECTURE rtl OF test IS BEGIN z <= CONV_INTEGER(a) + b ; END rtl;

May 2008

674

Product Version 7.2


RTL7.20 Message Size value in size’(expr) casting is too large

Default Severity Error Description The size value in size’(expr) casting is too large. Use a positive integer value as the size value. Example In the following example, the size ’hffffffff’ in line 4 is too large: module test(in, out); input in; output out; assign out = ’hffffffff’(in); endmodule;

May 2008

675

Product Version 7.2


RTL7.21 Message Real variables are not supported

Default Severity Warning Description Real variables are not supported in synthesis models. They are converted to 32-bit integers when encountered in the static verification tool flows. Example In the following example, r1 (line 5) is not supported: module real_in_cmp (b, out1); input [1:0] b; output out1; reg out1; real r1; always @(b) r1 = b; endmodule

May 2008

676

Product Version 7.2


RTL8.1 Message Multiple multipliers/dividers are in module/entity

Default Severity Note Description One or more modules or entities have multiple multipliers or dividers. Example In the following example, the design uses two multipliers in module test. See line 4 (in bold). module test (a, b, c, q); input [3:0] a, b, c; output [11:0] q; assign q = a * b * c; endmodule

May 2008

677

Product Version 7.2


RTL8.2 Message Latch(es) are inferred due to an incomplete conditional statement

Default Severity Note Description The checker has inferred one or more latches. The checker infers a latch when it finds an incomplete conditional statement. Example In the following example, the checker infers latch out0 so that output out0 will retain its previous value when the clk = 1'b0, the missing condition. See line 8 (in bold). module test (clk,rst,in0,out0); input clk,rst,in0; output out0; reg out0; always @ ( clk or in0 ) begin if (clk) out0 = in0; end endmodule

May 2008

678

Product Version 7.2


RTL8.3 Message Unreachable DFF/DLAT is removed

Default Severity Warning Description The design includes one or more DFFs or DLATs that are unreachable. Unreachable registers are those registers that do not propagate to any observable point (for example, spare flops). By default, the checker removes all unreachable DFFs and DLATs that are local to a module. If you want to keep the unreachable DFFs and DLATs, use the READ DESIGN command’s -keep_unreach option. For example: read design test.vhdl -vhdl -keep_unreach

Example In the following example, the output of register out1[1] does not propagate to any observable point. See line 9 (in bold). module TEST (clk,in1,in2,out0); input clk,in1,in2; output out0; reg out0; reg[1:0] out1; always @ ( posedge clk ) begin out0 <= in1; out1[1] <= in2; end endmodule

May 2008

679

Product Version 7.2


RTL8.4 Message Unreachable DFF/DLAT is kept

Default Severity Warning Description The design includes one or more DFFs or DLATs that are unreachable. Unreachable registers are those registers that do not propagate to any observable point (for example, spare flops). By default, the checker removes all unreachable DFFs and DLATs that are local to a module. You will receive this message if you use the READ DESIGN command’s -keep_unreach option. For example: read design test.vhdl -vhdl -keep_unreach

Example In the following example, on line 9, DFF out1[1] is unreachable: module TEST (clk,in1,in2,out0); input clk,in1,in2; output out0; reg out0; reg[1:0] out1; always @ ( posedge clk ) begin out0 <= in1; out1[1] <= in2; end endmodule

May 2008

680

Product Version 7.2


RTL8.5 Message Implicit signed multiplier is detected in module/entity

Default Severity Note Description The checker detected (and recognized) the Verilog signed multiplier coding style that uses either sign-extension or subtraction. Example In the following example, on lines 5, a signed multiplier is created using sign-extension coding style: module test( in1, in2, out);//using sign-extension input [21:0] in1; input [13:0] in2; output [34:0] out; assign out= {{21{in2[13]}}, in2[13:0]} * {{13{in1[21]}}, in1[21:0]}; endmodule

May 2008

681

Product Version 7.2


RTL9.1 Message Instance inout/output port has dynamic indexing. Treated as floating

Default Severity Warning Description The design includes one or more instance inout/output ports with dynamic indexing. Dynamic indexing is a non-synthesizable coding style. As a result, the checker creates floating signals for all inout/outputs. Example In the following example, only one of the two-bit outputs out0 is dynamically selected by input in2. See line 12 (in bold). module SUB (in2, out3); input in2; output out3; assign out3 = in2; endmodule module TEST (in0,in1,in2,out0); input [1:0] in0; input in1,in2; output [1:0] out0; reg [1:0] out0; SUB inst1 (.in2(in0[in1]),.out3(out0[in2])); endmodule

May 2008

682

Product Version 7.2


RTL9.2 Message Design has irregularly used inout/output expression

Default Severity Warning Description The design includes one or more irregularly used inout/output expressions. Example In the following example, inout port inout3 is tied to 0 logic value. See line 13 (in bold). module SUB (in2, inout3); input in2; inout inout3; wire inout3; assign inout3 = in2; endmodule module TEST (in0,in1,in2,out0); input [1:0] in0; input in1,in2; output [1:0] out0; reg [1:0] out0; SUB inst1 (.in2(in0[in1]),.inout3(1'b0)); endmodule

May 2008

683

Product Version 7.2


RTL9.3 Message Supply0/supply1 is converted into a wire

Default Severity Warning Description The supply0 or supply1 net is converted into a wire. Example In the following example, supply0 net in2 is converted to a wire. module test (in, out); input in; output out; supply0 in2; assign out = in & in2; endmodule

May 2008

684

Product Version 7.2


RTL9.4 Message Supply0/supply1 net is not a module port

Default Severity Warning Description The supply0 or supply1 net is not a module port. Example In the following example, supply0 net in2 is not a module port (see line 4): module test (in, out); input in; output out; supply0 in2; assign out = in & in2; endmodule

May 2008

685

Product Version 7.2


RTL9.5 Message Power pin is converted to an input pin

Default Severity Warning Description A power pin is converted to an input pin. Example In the following example, when running the following Conformal commands: set power pin -input vss vdd read des test.v -fix_power_pin

the vss and vdd pins are changed from inout to input pins. input in; output out; inout vss, vdd; // changed to input pins supply0 vss; supply1 vdd; assign out = !in; endmodule

May 2008

686

Product Version 7.2


RTL9.7 Message Cannot read value from OUT port

Default Severity Error Description A feedback loop has been detected through the asynchronous set or resets of flip-flop(s) and the listed signals, wires, or expressions. Example In the following example, dout (line 5) is the outport. Attempting to read from dout will cause an error: library ieee; use ieee.std_logic_1164.all; Entity dff is port (clk: in std_logic; reset: in std_logic; din: in std_logic; dout: out std_logic); end dff; Architecture behave of dff is signal reset_cond: std_logic; begin reset_cond <= dout or reset; process (clk,din,reset_cond) begin if reset_cond = ’1’ then dout <= ’0’; elsif clk’event and clk = ’1’ then dout <= din; end if end process; end behave;

May 2008

687

Product Version 7.2


RTL9.8 Message Set Liberty pin direction to output because it has an output function

Default Severity Warning Description This rule check sets the pin direction from the Liberty library to an output because it has an output function. Example In the following example, in line 9, the direction of pin Y is set to an output because it has an output function: library(test) { cell (AND2X2) { pin(A) { direction : input; } pin(B) { direction : input; } pin(Y) { function : "(A B)"; } } }

May 2008

688

Product Version 7.2


RTL9.9 Message Extra ’;’ is detected in port list

Default Severity Warning Description This rule check indicates that there is an extra semi-colon (;) after the last port in the port list. Example In the following example, in line 3, there is an extra semi-colon (;) after bit: entity e is port(q : out bit; d : in bit;); end; architecture a of e is+ begin q <= d; end;

May 2008

689

Product Version 7.2


RTL9.10 Message Liberty cell does not use any input pin

Default Severity Warning Description Indicates that the Liberty cell does not use any input pin. Example In the following example, in line 11, no input pin is used in the output function. library(test) { cell (AND2X2) pin(A) { direction } pin(B) { direction } pin(Y) { direction function: } } }

May 2008

{ : input; : input; : output; "(1)";

690

Product Version 7.2


RTL9.11 Message Liberty Master-Slave DFF cell clock phase does not match the timing table

Default Severity Warning Description Indicates that the liberty cell is a master-slave flip flop, but its clock phase does not match with the timing table. Example In the following example, the master-slave flip-flop is triggered by clocked_on_also : !phi, but a timing_type of rising edge is used in pin q. This causes a phase mismatch. cell (DFFDDRX8) { ... pin (resetb) { direction : input; capacitance : 0.00563; min_pulse_width_low : 0.33680; } pin (q) { function : "IQ" ; direction : output; max_fanout : 7.8535; timing() { related_pin : "phi"; timing_type : rising_edge ; ... } } ff (IQ,IQN) { clocked_on : phi ; clocked_on_also : !phi ; clear : !resetb ; next_state : "(!phi * dp) + (phi * dn)" ; } }

May 2008

691

Product Version 7.2


RTL9.12 Message Liberty cell with internal_node does not have correct statetable

Default Severity Warning Description Indicates that there is an internal_node in the liberty cell, but the corresponding statetable is missing or a corresponding pin of the internal_node name is not found in the cell. Example In the correct liberty file, if the internal_node attribute exists, there should be a corresponding statetable group as following: statetable("in1", "ires"){ ... }

but there is no statetable in the cell in the following example: cell(test){ pin (in1) { direction: input; } pin (ires) { direction: internal; internal_node: "ires" } pin (out1) { direction: output; function: "in1 in2"; } }

May 2008

692

Product Version 7.2


RTL9.13 Message Set liberty cell to blackbox because some of its output pins have no function

Default Severity Warning Description Indicates that some of the liberty cell’s output pin has no function attribute in it, but some timing table exist in the output pin. Then the liberty cell is set to be a blackbox. Example In the following example, if line 3 is removed, the cell would be marked as a blackbox. pin (out2) { direction: output; function: "!in1"; timing(){ ... } }

May 2008

693

Product Version 7.2


RTL9.14 Message Liberty cell has duplicate signal (pin/member)

Default Severity Error Description Indicates that there are duplicated signals in a bundle declaration of the Liberty cell. Example In the following example, the bundle (z) has duplicated members z01: cell(zhdp_mpt2) { bundle(r) { members(r0, r1); direction : input; capacitance : 0.003750; fanout_load : 0.188; min_pulse_width_high : 0.056; } bundle(z) { members(z01, z01); /* ERROR: z01 is duplicated * direction : inout; capacitance : 0.005625000; } } /* cell(zhdp_mpt2) */

May 2008

694

Product Version 7.2


RTL10 Message Both posedge and negedge are used in different always/process

Default Severity Warning Description Both the posedge and negedge of a clock are used in different always/process blocks. Example On line 5 of the following example, the design uses the posedge clock in an always block. And on line 9, the design uses the negedge clock in another always block. module SEN (clk,rst,in0,out0,out1); input clk,rst,in0; output out0,out1; reg out0,out1; always @ ( posedge clk ) begin out0 <= in0; end always @ ( negedge clk ) begin out1 <= !in0; end endmodule

May 2008

695

Product Version 7.2


RTL11 Message Incomplete condition is in a function/procedure/task block

Default Severity Warning Description The design includes one or more incomplete conditional statements within functions, procedures, or task blocks. Examples ■

In the following example, the if statement is missing its else branch. See line 8 (in bold). module TER (clk,rst,in0,out0); input clk,rst,in0; output out0; wire out0; assign out0 = func1 (in0,rst); function func1; input in0, rst; if (rst) func1 = in0; endfunction endmodule

■

Incomplete conditional statements might lead to false positive result under certain circumstance and should be carefully examined. In the following example, the variable parameter type output in the subprogram might get an ambiguous value because of the incomplete conditional statements. In this testcase, nxt_state is associated with a variable parameter of mode OUT in procedure next_state. Inside the procedure, when x = 3, there is no assignment to z. In this case, nxt_state does not hold its original value of 3 after calling procedure next_state. Instead, it gets a value 0 (in bold). library ieee; use ieee.std_logic_1164.all; entity test is procedure next_state(x: in integer range 0 to 3; z: out integer range 0 to 3) is

May 2008

696

Product Version 7.2


begin case x is when 1 => z := 1; when 2 => z := 2; when others => NULL; end case; end next_state; end test; architecture rtl of test is begin process variable cur_state: integer range 0 to 3; variable nxt_state : integer range 0 to 3; begin cur_state := 3; nxt_state := 3; next_state(cur_state, nxt_state); end process; end rtl;

May 2008

697

Product Version 7.2


RTL12 Message Referenced variable(s)/signal(s) are not in sensitivity list

Default Severity Warning Description The design includes one or more variables or signals that are referenced but not included in sensitivity lists. Example On line 7 of the following example, the design references variable in2, which is not included in the sensitivity list on line 5. module SEN (in0,in1,in2,out0); input in0,in1,in2; output out0; reg out0; always @ ( in0 or in1 ) begin out0 = in0 | in1 | in2; end endmodule

May 2008

698

Product Version 7.2


RTL12.1 Message Constant object is in sensitivity list

Default Severity Warning Description There is a constant object in the sensitivity list. Example In the following example, val is a constant (see line 6): module SEN (in0,out0); input in0; output out0; parameter val = 1; reg out0; always @ ( in0 or val ) begin out0 = in0 ; end endmodule

May 2008

699

Product Version 7.2


RTL13 Message For loop condition is always false

Default Severity Warning Description The design includes one or more for loops that will never hold true. Example On line 7 of the following example, the variable i is initialized with a value of 2 (i=2). Thus, this for loop will never hold true, since i will never be less than a value of 1 (i<1). module test(out,in); output [3:0] out; reg [3:0] out; input [3:0] in; integer i; always begin for (i=2; i<1; i=i+1) begin out = i; end out = in; end endmodule

May 2008

700

Product Version 7.2


RTL13.1 Message The FOR-LOOP index should not be assigned within the loop itself

Default Severity Warning Description The FOR-LOOP index cannot be assigned within the loop. Example In the following example, i is the FOR-LOOP index and it is assigned within the loop (see line 8): module top(input [1:0] in, output [4:0] out); sum sum1(in,out); endmodule module sum(input [1:0] a, output [4:0]result); integer i; always begin for (i=0; i<3; i=i+1) begin i = a; end end endmodule

May 2008

701

Product Version 7.2


RTL13.2 Message The evaluation of for-loop condition is not constant

Default Severity Warning Description The Conformal software detected a non-static loop. As per synthesis semantics, a loop in an HDL design must be statically unrollable—that is, the number of loop iterations should be statically known. Example In the following example, N is not a constant (see line 9): module neg_NSLOOP (a, b, c); input [1000:0] a, b; output [1000:0] c; reg [1000:0] c; integer N; always @(a or b) begin: P integer I; for (I = 0; I < N; I = I + 1) c[I] = a[I] & b[I]; end endmodule

May 2008

702

Product Version 7.2


RTL14 Message Signal with fanin drive and no fanout load is detected

Default Severity Warning Description The checker has removed one or more floating signals. This situation occurs when the output of a logic cone has no fan-out loads. In other words, the signal is driven by a gate or input port (has drives), but its output does not drive any gate or output port (has no loads). Example On line 5 of the following example, flt does not have any fan-out loads, so the checker issues the RTL14 warning. module test(aa, bb, o1, o2); input aa, bb; output o1, o2; wire flt; assign flt = aa != bb; assign o1 = aa == bb; endmodule

May 2008

703

Product Version 7.2


RTL14.1 Message Fanout load of the signal is removed

Default Severity Warning Description Indicates that the fanout load of a signal is removed, and therefore the signal becomes a floating signal, which is also removed. Example In the following example, bb (on line 5) has fanout load at line 4, but this fanout is removed because aa has RTL14 violation. The RTL14.1 rule checker reports that the fanout load of bb is removed, and therefore bb becomes a floating signal, which is also removed. module test(oo); output oo; wire aa, bb, cc; assign aa = !bb; assign bb = !cc; endmodule

May 2008

// RTL14 rule violation // RTL14.1 rule violation

704

Product Version 7.2


RTL15 Message Clock and asynchronous set/reset expression must be one bit wide

Default Severity Error Description A clock variable or an asynchronous set/reset variable in the sensitivity list is more than onebit wide. Example On line 1 of the following example, myReset is declared as a two-bit wide. On line 2, an RTL15 error is reported because myReSet is not a single-bit and it is used as an asynchrounous set/reset variable on the sensitivity list. reg [1:0] myReset; // myReset is two-bit wide always @(posedge clk or posedge myReset) begin ... end

May 2008

705

Product Version 7.2


RTL15.1 Message Else branch of event controlled if statement is not supported

Default Severity Warning Description For modeling a flip-flop with asynchronous forces, the clock edge should be the fulfilling condition of the last conditional block. In addition, there should be assignment to output under only one clock edge. Both edges of clock signal are used in a sequential process. Example In the following example, both HIGH and LOW edges of the signal clk are used in a sequential process (see lines 19 and 21, respectively): library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ClockEdge is port (sort : out unsigned (3 downto 0); clk : in std_logic; rst : in std_logic; ena1 : in unsigned (3 downto 0)); end ClockEdge; architecture rtl_clkedge of ClockEdge is constant ZERO : unsigned(3 downto 0) := "0000"; constant HIGH : std_logic := ’1’; constant LOW : std_logic := ’0’; begin p0_OK:process (clk,rst) begin if (rst =HIGH) then sort <= ZERO; elsif ( clk’event and clk=HIGH) then sort <= ena1; elsif ( clk’event and clk=LOW) then sort <= ena1 + ena1; end if; end process p0_OK; end rtl_clkedge;

May 2008

706

Product Version 7.2


RTL15.2 Message Sensitivity/clock style is unsupported

Default Severity Warning Description The always block is sensitive to both the edges and levels of some signals. Synthesis tools do not support both level and edge sensitive nodes in the sensitivity list. Example In the following example, line 5 has both level and edge sensitivity nodes: module mult_clks_in_always2 (clk, q, d, rst1, rst2); input clk, d, rst1, rst2; output q; reg q; always @(clk or posedge rst1) begin if (rst2) q <= d; end endmodule

May 2008

707

Product Version 7.2


RTL16.1 Message Non-local variable is read in a function body

Default Severity Warning Description A non-local variable is read in a function body. Example On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7, an RTL16.1 warning is reported because glob_1 is read inside the function body. RTL16.1 warns potential mismatch between synthesis and simulation semantics. reg glob_1; // glob_1 is declared outside of function f1 ... function f1 ... reg local_1; begin ... local_1 = glob_1; // RTL16.1: glob_1 is read inside the function body ... end

May 2008

708

Product Version 7.2


RTL16.2 Message Non-local variable is assigned in a function body

Default Severity Warning Description A non-local variable is assigned in a function body. Example On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7, an RTL16.2 warning is reported because glob_1 is assigned inside the function body. RTL16.2 warns about the function body contains a side effect due to this external variable assignment. reg glob_1; // glob_1 is declared outside of function f1 ... function f1 ... reg local_1; ... begin ... glob_1 = local_1; // RTL16.2: glob_1 is assigned inside the function body ... end

May 2008

709

Product Version 7.2


RTL17 Message Variable size exceeds the maximum limit

Default Severity Error Description The variable size exceeds the maximum limit. Example In the following example, the variable tmp size exceeds the limit of 8192*8192 (see line 3) module test (out); output [31:0] out; wire [8192*8192:0] tmp; assign out = tmp[31:0]; endmodule

May 2008

710

Product Version 7.2


RTL17.1 Message Expression size exceeds the maximum limit

Default Severity Error Description The expression size exceeds the maximum limit. Example The following example triggers the RTL17.1 message because the expression size exceeds limit 67108864. The objects maximum bit size of 67108864 is predefined by all Conformal tools. module test(output r1); wire [67108864:0] r1; assign r1 = 0; endmodule

May 2008

// ERROR: RTL17.1 violation

711

Product Version 7.2


RTL18.1 Message Package is not an IEEE standard

Default Severity Ignore Description The IEEE package is not a standard package. Example In the following example, std_logic_arith is not a standard IEEE package (see line 2): library ieee; use ieee.std_logic_arith.all; entity test is port (out1 : out signed (1 downto 0); in1 : in signed (1 downto 0); in2 : in signed (1 downto 0)); end test; architecture rtl of test is begin p1:process( in1,in2) begin out1 <= in1 + conv_integer(in2); end process p1; end rtl;

May 2008

712

Product Version 7.2


RTL18.2 Message Function definition has empty body

Default Severity Warning Description The function definition has empty body. Example In the following example, the function byte_reversal in line 10 is an empty function: library ieee; use ieee.std_logic_1164.all; entity func is port( data:in std_logic_vector(8 downto 0); rev_data:out std_logic_vector(8 downto 0) ); end func; architecture func of func is function byte_reversal (arg:std_logic_vector) return std_logic_vector is begin end byte_reversal; begin process begin rev_data <= byte_reversal(data); end process; end func;

May 2008

713

Product Version 7.2


RTL18.3 Message Function call does not refer to a function definition

Default Severity Error Description The function call does not refer to a function definition. Example In the following example, the function func in line 6 is not defined: module test(in,out); input in; output out; reg out; always @(in) out = func(in); endmodule

May 2008

714

Product Version 7.2


RTL18.4 Message Ignoring resolution function. This might cause mismatches between simulation and synthesis

Default Severity Warning Description The ’resolved’ function defined in package IEEE STD_LOGIC_1164 is the only supported resolution function. Other resolution functions are ignored. Example In the following example, resolution function RESOLVE_VOLTAGE is ignored: ... function RESOLVE_VOLTAGE ( V: UVOLTAGE_VECTOR ) return UVOLTAGE; subtype VOLTAGE is RESOLVE_VOLTAGE UVOLTAGE;

May 2008

715

Product Version 7.2


RTL19.1 Message Identifier is a reserved keyword and might conflict in designs with mixed languages

Default Severity Warning Description The identifier is a reserved keyword for Verilog or VHDL. Example In the following example, logic is a System Verilog keyword (see line 2): module test (input din, output logic); assign logic = din; endmodule ;

May 2008

716

Product Version 7.2


RTL20.1 Message Pre-defined attribute is not supported

Default Severity Warning Description The specified pre-defined attribute in the design is not supported. Remodel the design to avoid this error. Example In the following example, the last_attribute in line 21 is not supported: library IEEE; use IEEE.std_logic_1164.all; entity lat is port ( din: in bit; clk :in bit; din1 : in bit_vector(1 downto 0); dout : out bit_vector(2 downto 0); dout1 : out bit_vector(1 downto 0)); end lat; architecture behave of lat is signal clk1 : bit; component lat_bit is port ( d: in bit; clk :in bit; q : out bit); end component; begin dout(0) <= din; process(clk1,din) begin if clk1’last_value = ’0’ and clk1 = ’1’ then dout(2 downto 1) <= din1; end if; end process; I1 : lat_bit port map(din, clk, dout1(1)); I0 : lat_bit port map(din, clk, dout1(0)); end behave;

May 2008

717

Product Version 7.2


RTL20.2 Message Function is not supported

Default Severity Warning Description The referenced function is not supported (1’bx will be returned). Example In the following example, the sqrt function (line 10) is not supported: library ieee; use ieee.math_real.all; ENTITY test_constant_reals IS PORT ( sample_out : OUT integer ); END test_constant_reals; ARCHITECTURE rtl OF test_constant_reals IS BEGIN sample_out <= integer(sqrt(1.375)); END rtl;

May 2008

718

Product Version 7.2


RTL20.3 Message Could not find configuration

Default Severity Warning Description The refered configuration could not be found. Example In the following example, if the configuration bug2_cfg is not defined before configuration bug_cfg, this message will be issued. ... configuration bug_cfg of bug is ... use configuration work.bug2_cfg ...

May 2008

719

Product Version 7.2


SPICE Netlist Format This category of rules applies to SPICE netlists used for Conformal Custom. The following table lists the SPICE (SPI) rule numbers and their messages. Rule Number

Message

SPI1.1

Diode instance is ignored

SPI1.2

Incorrect diode instance is ignored

SPI1.3

SPICE element/card is ignored

SPI1.4

Subckt name duplicated and previous ones are ignored

SPI3.2

Model redefined. Using last definition and ignoring earlier ones

SPI4.1

.GLOBAL statement for pin is redefined. Previous definition is ignored

SPI4.2

.GLOBAL statement for pin with type ’C’ is not supported and is ignored

SPI5.1

Implicit bulk VDD Net reset to GND due to .GLOBAL declaration

SPI5.2

Implicit bulk GND Net reset to VDD due to .GLOBAL declaration

SPI7.1

Duplicated pin in subckt. Creating new pin

SPI7.2

Duplicate pin of subckt with different pin connections in instance

SPI8.1

Undefined Pin in ’*.PININFO’ is ignored

May 2008

720

Product Version 7.2


SPI1.1 Message Diode instance is ignored

Default Severity Warning Description The checker is ignoring one or more diode instances in the SPICE netlist. Example The checker reports the following: SPI1.1: Ignoring diode instance Type: Golden design Severity: Warning Occurrence: 1 1: ant/D1 on line 3 in file 'test.sp'

That is, the checker ignores a diode instance called D1 in the SPICE netlist. .SUBCKT ant y D1 y vss .ENDS

May 2008

721

Product Version 7.2


SPI1.2 Message Incorrect diode instance is ignored

Default Severity Warning Description The checker is ignoring one or more incorrectly instantiated diode instances in the SPICE netlist. The checker ignores diodes in all cases. See SPI1.1 on page 721. Example In the following example, the checker generates the SPI1.2 message for line 3 (in bold) because D should be followed by some alphanumeric characters. (Also, since the checker ignores all diodes, line 2 triggers the SPI1.1 message.) .subckt foo a b D1 a b D a b .ends

May 2008

722

Product Version 7.2


SPI1.3 Message SPICE element/card is ignored

Default Severity Warning Description The SPICE element or card is ignored.

May 2008

723

Product Version 7.2


SPI1.4 Message Subckt name duplicated and previous ones are ignored

Description The checker encountered a subcircuit name that was already used in the SPICE netlist. When this duplication happens, the checker retains the last definition encountered and ignores earlier ones.

May 2008

724

Product Version 7.2


SPI3.2 Message Model redefined. Using last definition and ignoring earlier ones

Default Severity Warning Description The checker encountered a redefined model in the SPICE netlist. When this redefinition occurs, the checker uses the last definition encountered and ignores earlier ones. Example In the following SPICE netlist example, P1 is defined as PMOS and redefined as NMOS. In this case, the checker recognizes NMOS as the definition for P1. .model P1 PMOS .model P1 NMOS

May 2008

725

Product Version 7.2


SPI4.1 Message .GLOBAL statement for pin is redefined. Previous definition is ignored

Default Severity Warning Description The checker encountered a redefined .GLOBAL statement in the SPICE netlist. When this redefinition occurs, the checker uses the last definition encountered and ignores earlier ones. Example In the following SPICE netlist example, pin pr is defined as power and redefined as ground. In this case, the checker recognizes ground as the definition for pin pr. .global pr:P .global pr:G

May 2008

726

Product Version 7.2


SPI4.2 Message .GLOBAL statement for pin with type ’C’ is not supported and is ignored

Default Severity Warning Description The checker encountered a .GLOBAL statement with pin type ‘C’ in the SPICE netlist. When this occurs, the checker ignores that pin type. Example In the following SPICE netlist example, pin type ’C’ of the global net ’a’ will be ignored: .global vdd:P a:C;

May 2008

727

Product Version 7.2


SPI5.1 Message Implicit bulk VDD Net reset to GND due to .GLOBAL declaration

Default Severity Warning Description The SPICE netlist includes a .global declaration that overrides an implicit VDD assignment. By default, the checker assumes that the bulk node of PMOS is VDD. The net connected to the bulk node is thus implicitly assigned as VDD. However, if there is a .global declaration for a PMOS net, the global declaration takes precedence over the implicit assignment. Example In the following example, net a retains its definition as assigned by the .global statement on line 1 (in bold). The checker ignores the implicit meaning of this net based on the bulk connection (see line 5). Also refer to SPI5.2 on page 729. .global a:G .global b:P .subckt inv aa bb out M1 aa bb VDD a PMOS M2 aa bb VSS b NMOS .ends

May 2008

728

Product Version 7.2


SPI5.2 Message Implicit bulk GND Net reset to VDD due to .GLOBAL declaration

Default Severity Warning Description The SPICE netlist includes a .global declaration that overrides an implicit GND assignment. By default, the checker assumes that the bulk node of NMOS is GND. The net connected to the bulk node is thus implicitly assigned as GND. However, if there is a .global declaration for an NMOS net, the global declaration takes precedence over the implicit assignment. Example In the following example, net b retains its definition as assigned by the .global statement on line 2 (in bold). The checker ignores the implicit meaning of this net based on the bulk connection (see line 6). Also refer to SPI5.1 on page 728. .global a:G .global b:P .subckt inv aa bb out M1 aa bb VDD a PMOS M2 aa bb VSS b NMOS .ends

May 2008

729

Product Version 7.2


SPI7.1 Message Duplicated pin in subckt. Creating new pin

Default Severity Warning Description The checker encountered a duplicate pin name in the subckt definition while reading a SPICE netlist. When this duplication occurs, the checker creates a new name for the second pin with the following format: _vplx_redundant_. Example In the following SPICE netlist example, pin a is defined on line 2 (in bold) and repeated in the subckt definition on line 3 (in bold). The checker creates a new pin for the second a it encountered. The new pin is named a_vplx_redundant_0. .subckt inv a b a out M1 a b VDD VDD PMOS M2 a b VSS VSS NMOS .ends

May 2008

730

Product Version 7.2


SPI7.2 Message Duplicate pin of subckt with different pin connections in instance

Default Severity Warning Description The checker is detecting an instance with duplicated pins in the SPICE netlist: Example In the following SPICE netlist example, the second pin of instance x1 of subckt inv is redundant and will be ignored: .global vdd gnd; .subckt inv in in; m1 vdd in out vdd p; m2 out in gnd gnd n; .ends inv; .subckt top o i; x1 o i inv; .ends top;

May 2008

731

Product Version 7.2


SPI8.1 Message Undefined Pin in ’*.PININFO’ is ignored

Default Severity Warning Description A SPICE *.PININFO statement includes an undefined pin. *.PININFO can be used to define pins as input (I), output (O) or bidirectional (B). If I, O or B is missing for the pin defined in a PININFO statement, the checker ignores the undefined pin and issues a warning. Example In the following PININFO example, pin a is defined as I. However, on line 2 (in bold) the definition for pin b is missing. When the checker encounters line 2, it generates the SPI8.1 message. *.pininfo a:I *.pininfo b:

May 2008

732

Product Version 7.2


System Verilog This category of rules applies to System Verilog designs. The following table lists the System Verilog (SV) rule numbers and messages. Rule Number

Message

SV1.1

covergroup usage is unsupported and ignored

SV1.2

’assert property’ is unsupported and ignored

SV1.3

’assume property’ is unsupported and ignored

SV1.4

’cover property’ is unsupported and ignored

SV1.5

’void’ type is not allowed in object declaration

SV1.6

Missing argument list for function call

SV1.7

Unbounded range parameter ’$’ is not supported

SV1.8

Procedural assertion is unsupported and ignored

SV1.9

’distribution weight’ is unsupported and ignored

SV1.10

Sequence operation is unsupported and ignored

SV1.11

Sequence concatenation is unsupported and ignored

SV1.12

number_of_ticks is not a constant value

SV1.13

number_of_ticks must be 1 or greater

SV1.14

Sequence method is unsupported and ignored

SV1.15

Recursive properties are unsupported and ignored

SV2.1

Packed type cannot contain real/shortreal/unpacked type

SV2.2

All elements must have same size in a packed union type

SV3.1

Modules can neither be declared nor instantiated in interfaces

May 2008

733

Product Version 7.2


SV1.1 Message covergroup usage is unsupported and ignored

Default Severity Warning Description The covergroup usage is not supported and is ignored. Example In the following example, g2 (line 2) is unsupported: module test( input logic [7:0] in1, reg clk, output logic [7:0] out1); covergroup g2 @(posedge clk); endgroup always@( posedge clk) begin out1 = in1; end endmodule

May 2008

734

Product Version 7.2


SV1.2 Message ’assert property’ is unsupported and ignored

Default Severity Warning Description The assert property is not supported and is ignored. Example In the following example, assert property p1 (line 3) is ignored module prop1 (input clk,output logic [7:0] count1); logic [7:0] counter1 = ’0; assert property (p1) count1 = counter1; endmodule

May 2008

735

Product Version 7.2


SV1.3 Message ’assume property’ is unsupported and ignored

Default Severity Warning Description The assume property is not supported and is ignored. Example In the following example, assume property p1 is ignored: module prop1 (input clk,output logic [7:0] count1); logic [7:0] counter1 = ’0; assume property (p1) count1 = counter1; endmodule

May 2008

736

Product Version 7.2


SV1.4 Message ’cover property’ is unsupported and ignored

Default Severity Warning Description The cover property is not supported and is ignored. Example In the following example, cover property p1 is ignored: module prop1 (input clk,output logic [7:0] count1); logic [7:0] counter1 = ’0; cover property (p1) count1 = counter1; endmodule

May 2008

737

Product Version 7.2


SV1.5 Message ’void’ type is not allowed in object declaration

Default Severity Error Description The ’void’ type is not allowed in the object declaration. Example In the following example, it is illegal to declare a void type variable for var1: void var1;

May 2008

738

Product Version 7.2


SV1.6 Message Missing argument list for function call

Default Severity Error Description Indicates that the function call does not have an argument list. Example In the following example, in line 11, the argument list is missing: module test(in, out); input in; output out; function func; input din; begin func = din; end endfunction always @(in) out = func; endmodule

May 2008

739

Product Version 7.2


SV1.7 Message Unbounded range parameter ’$’ is not supported

Default Severity Error Description Indicates that the unbounded range parameter ’$’ is not supported. This is for System Verilog only. Example In the following example, in line 6, ’$’ is used as parameter. module test #(parameter p1 = 1)(input int i, output int out); always @(i) out = i+p1; endmodule module top(input int in, output int dout); test #($) sub(in,dout); endmodule

May 2008

740

Product Version 7.2


SV1.8 Message Procedural assertion is unsupported and ignored

Default Severity Warning Description Indicates that the procedural assertion is unsupported and is ignored. This is for System Verilog only. Example In the following example, the procedural assertion in line 3 is unsupported and ignored. module test (input logic clk,input logic in); always @(posedge clk) if (in == ’1) assert (req1 || req2); else begin $error("assert failed" ); end endmodule

May 2008

741

Product Version 7.2


SV1.9 Message ’distribution weight’ is unsupported and ignored

Default Severity Warning Description The usage of distribution weight is described in SystemVerilog LRM 13.4.4 Distribution. The usage of distribution weight is unsupported and is ignored by all Conformal software tools. Example In the following example, x is equal to 100, 200, or 300 with weighted ratio of 1-2-5. The usage of the distribution weight will trigger this warning. x dist {100 := 1, 200 := 2, 300 := 5}

May 2008

742

Product Version 7.2


SV1.10 Message Sequence operation is unsupported and ignored

Default Severity Warning Description The usage of sequence is described in SystemVerilog LRM 17.5 Sequences. The usage of sequence is unsupported and is ignored by all Conformal software tools. Example In the following example, the usage of sequence operation (first_match in line 5) will trigger this warning. sequence t1; te1 ## [2:5] te2; endsequence sequence ts1; first_match(te1 ## [2:5] te2); endsequence

May 2008

743

Product Version 7.2


SV1.11 Message Sequence concatenation is unsupported and ignored

Default Severity Warning Description The usage of sequence is described in SystemVerilog LRM 17.5 Sequences. The usage of sequence is unsupported and is ignored by all Conformal software tools. Example In the following example, using cycle delay ##1 will trigger this warning. @(posedge clk0) sig0 ##1 @(posedge clk1) sig1

May 2008

744

Product Version 7.2


SV1.12 Message number_of_ticks is not a constant value

Default Severity Error Description The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is: $past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

where the number_of_ticks must be 1 or greater. If number_of_ticks is not specified, it defaults to 1. The SV1.12 error is reported if number_of_ticks is not evaluated to be a constant value. Example The following example will trigger this error if input_port_N is not a constant expression: $past( bet1, input_port_N)

May 2008

745

Product Version 7.2


SV1.13 Message number_of_ticks must be 1 or greater

Default Severity Error Description The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is: $past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

where number_of_ticks must be 1 or greater. If number_of_ticks is not specified, then it defaults to 1. The SV1.13 error is reported if number_of_ticks is not evaluated to be 1 or greater. Example The following example will trigger this error because -1 is not 1 or greater than 1: $past( bet1, -1)

May 2008

746

Product Version 7.2


SV1.14 Message Sequence method is unsupported and ignored

Default Severity Warning Description The sequence usage is described in SystemVerilog LRM 17.5 Sequences. The sequence methods are described in SystemVerilog LRM 17.12.6. The SV1.14 warning is reported if sequence methods are used. Example The following example will trigger this warning because an ended method is used (line 5): sequence e1; @(posedge sysclk) $rose(ready) ##1 proc1 ##1 proc2 ; endsequence sequence rule; @(posedge sysclk) reset ##1 inst ##1 e1.ended ##1 branch_back; endsequence

May 2008

747

Product Version 7.2


SV1.15 Message Recursive properties are unsupported and ignored

Default Severity Warning Description The sequence usage is described in SystemVerilog LRM 17.11.4 Recursive property. The SV1.15 warning is reported if recursive properties are used. Example ■

The following example shows a simple recursive property case, where a property instantiation prop_always is inside the prop_always property declaration. This causes a recursive property problem. property prop_always(p); p and (1’b1 |=> prop_always(p)); endproperty

■

The following example shows a mutually recursive case, where in property declaration check_phase1, there is an instantiation check_phase2, and in property declaration check_phase2, there is an instantiation check_phase1. This causes a mutually recursive property problem. property check_phase1; s1 |-> (phase1_prop and (1’b1 |=> check_phase2)); endproperty property check_phase2; s2 |-> (phase2_prop and (1’b1 |=> check_phase1)); endproperty

May 2008

748

Product Version 7.2


SV2.1 Message Packed type cannot contain real/shortreal/unpacked type

Default Severity Error Description Noninteger data types, such as real and shortreal, are not allowed in packed structures or unions. Neither are unpacked arrays. Example In the following packed struct type example, the errors are shown by comments: typedef struct packed { bit [3:0] GFC; +real VPI; // real type is not allowed in a packed structure bit PT [3:0] ; // unpacked type is not allowed a packed structure bit [7:0] HEC; } myPackedType;

May 2008

749

Product Version 7.2


SV2.2 Message All elements must have same size in a packed union type

Default Severity Error Description A packed union shall contain members that must be packed structures, or packed arrays or integer data types all of the same size (in contrast to an unpacked union, where the members can be different sizes). This ensures that a union member that was written as another member can be read back. Example In the following packed union type example, the errors are shown by comments: typedef union packed { bit [7:0] v1; bit [3:0][1:0] v2; bit [8:0] v3; // ERROR: v3 has 9 bits, but both v1 and v2 have 8 bits } badPkUnionType;

May 2008

750

Product Version 7.2


SV3.1 Message Modules can neither be declared nor instantiated in interfaces

Default Severity Error Description Interfaces can be declared and instantiated in modules (either flat or hierarchical), but modules can neither be declared nor instantiated in interfaces. Example In the following example, the module instantiation is not allowed in the interface declaration: module mod1 (input aa, bb; output zz); assign zz = aa && bb; endmodule interface simple_bus; // Define the interface logic req, gnt; logic [7:0] addr, data; logic [1:0] mode; logic start, rdy; mod1 u0(req, gnt, rdy); // ERROR: SV3.1 violation. endinterface: simple_bus

May 2008

751

Product Version 7.2


User-Defined Primitive This category of rules applies to designs that include user-defined primitives. The following table lists the User-Defined Primitive (UDP) rule numbers and their messages. Rule Number

Message

UDP1.1

Swapped set and reset of DFF/DLAT

UDP1.2

Removed set-domination logic of DFF/DLAT

UDP1.3

Unknown set and reset domination. Implemented as reset domination

UDP2.1

Inverter on data input of DFF/DLAT is moved to output

UDP2.2

Inverter on data input of DFF/DLAT is not moved to output

UDP3

Merged redundant user-defined DFF/DLAT primitive(s)

UDP3.1

Conflicting entries are detected in the outputs

UDP3.2

Primitive has unspecified term(s)

UDP4.1

Primitive contains illegal symbol ’z’

UDP4.2

Primitive contains an ’x’ output without an ’x’ input

May 2008

752

Product Version 7.2


UDP1.1 Message Swapped set and reset of DFF/DLAT

Default Severity Note Description The checker swapped a set and reset for a user-defined DFF or DLAT primitive. Automatic swapping of DFF and DLAT set and reset occurs only when there is a need to accommodate a conversion (for example, merging DFFs). Example Two warnings occurred for the following example: 1. On lines 5 through 8 (in bold), instance U1 is merged into instance U2 because they have the same connection (except q and qb for outputs). 2. The checker swaps set and reset of instance U2 to accommodate merging instance U1. module RSLTA (Q,QB,S,R,notifier); input S,R; output Q,QB; input notifier; rsltaq U1(.q(Q),.s(S),.r(R), .notify(notifier)); rsltaqb U2(.qb(QB),.s(S),.r(R), .notify(notifier)); endmodule

May 2008

753

Product Version 7.2


UDP1.2 Message Removed set-domination logic of DFF/DLAT

Default Severity Note Description One or more user-defined DFF or DLAT primitives have multiple sets of set-dominant logic. The checker removed the redundant set of set-dominant logic. Example On line 11 of the following example, the design includes an OR logic to ensure a set-dominant DFF, but the DESFQ primitive was already defined in line 1 as a set-dominant DFF. Thus, the design includes two set-dominant logics (shown in lines 1 and 11). primitive DESFQ = a set-dominant DFF module test ( N01, H01, H02, H03, H04); input H01; input H02; input H03; input H04; output N01; not ( _G005, H03 ); not ( _G002, H04 ); or ( N01, _G008, H04 ); DESFQ ( .Q(_G008), .D(H01), .CP(H02), .RB(_G005), .SB(_G002), .notifier(notifier) ); endmodule

May 2008

754

Product Version 7.2


UDP1.3 Message Unknown set and reset domination. Implemented as reset domination

Default Severity Warning Description A UDP is interpreted as a sequential DLAT or DFF logic, and: ■

DLAT or DFF has both asynchronous set and reset logic

■

set and reset logic might result in 1 at the same time

■

no domination on set or reset

Example primitive srq0 ( output Q; reg Q; input S; input RX; table S RX : 1 1 : 0 0 : ? 1 : 0 ? : 0 1 : endtable endprimitive

Q, S, RX );

Q? ? 1 0 ?

: : : : : :

Q+ 1 0 1 0 -

; ; ; ; ;

The Conformal software will generate a DLAT circuit with asynchronous set and reset: ■

set = S

■

reset = RX’

■

d=0

■

clock = 0

May 2008

755

Product Version 7.2

Encounter Conformal Equivalence Checking Reference Manual HDL Rule Check Messages The UDP does not specify the behavior when S = 1 and RX = 0. The Conformal software implements the circuit as a reset dominated logic, which implies that when S = 1 and RX = 0, Q = 0. This is usually caused by UDP table incompletion.

May 2008

756

Product Version 7.2


UDP2.1 Message Inverter on data input of DFF/DLAT is moved to output

Default Severity Warning Description One or more user-defined DFF or DLAT primitives (UDP) include an inverter on the data port. By default, the checker relocates inverters from data port to output port. Example In the following example, primitive dff_simple has an inverter at the data port of the DFF, but the checker moves it to the output port of the DFF. primitive dff_simple(Q, S, R, CK, D); output Q; input S, R, CK, D; reg Q; table 1 0 ? ? : ? : 1; ? 1 ? ? : ? : 0; 0 0 r 0 : ? : 1; 0 0 r 1 : ? : 0; 0 0 (?0) ? : ? : -; endtable endprimitive

May 2008

757

Product Version 7.2


UDP2.2 Message Inverter on data input of DFF/DLAT is not moved to output

Default Severity Warning Description One or more user-defined DFF or DLAT primitives (UDP) include an inverter on the data port. By default, the checker relocates inverters from data port to output port. However, in this case, you specified that the checker will not move the DFF or DLAT when you used the following command: add udp model dff_simple -nomove_inverter

Example In this example, primitive dff_simple has an inverter at the data port of the DFF, but the checker did not move it since the user applied the -nomove_inverter option. primitive dff_simple(Q, S, R, CK, D); output Q; input S, R, CK, D; reg Q; table 1 0 ? ? : ? : 1; ? 1 ? ? : ? : 0; 0 0 r 0 : ? : 1; 0 0 r 1 : ? : 0; 0 0 (?0) ? : ? : -; endtable endprimitive

Input: SETUP>add udp model dff_simple -nomove_inverter SETUP>read design test.v -verilog

May 2008

758

Product Version 7.2


UDP3 Message Merged redundant user-defined DFF/DLAT primitive(s)

Default Severity Note Description The design includes one or more redundant user-defined DFF or DLAT primitives. The checker merges all redundant user-defined DFF and DLAT primitives. Example In the following example, DFF UDP_A is redundant and merged into DFF UDP_B. See lines 7 through 10 (in bold). module test ( N01, N02, H01, H02, notifier ); input H01; input H02; input notifier; output N01; output N02; DESFQ UDP_A(.Q(N01), .D(H01), .CP(H02), .RB(1'b1), .SB(1'b1), .notifier(notifier)); DESFQ UDP_B(.Q(N02), .D(H01), .CP(H02), .RB(1'b1), .SB(1'b1), .notifier(notifier)); endmodule

May 2008

759

Product Version 7.2


UDP3.1 Message Conflicting entries are detected in the outputs

Default Severity Warning Description There are conflict entries in the user-defined primitive outputs. Example In the following example, the two lines have the same input values but different output values: //

May 2008

D ? ?

CK ? ?

RB 0 0

SB 0 0

FLAG : ? : ? :

Qt : ? : ? :

760

Qt+1 1;// 0;//

Product Version 7.2


UDP3.2 Message Primitive has unspecified term(s)

Default Severity Warning Description There are unspecified term(s) in the UDP table. Example In the following example, term ’010’ and ’011’ is unspecified: primitive udp_inv_clr0 (qn, clr, output qn; input clr, pre, inp; table // clr pre inp 0 0 ? 1 ? 0 1 ? 1 // ? 1 0 // ? 1 1 x x 1 x x 0 endtable endprimitive

May 2008

pre, inp);

: : : : : : : :

qn 0; 1; 0; 1; 0; 0; 1;

761

Product Version 7.2


UDP4.1 Message Primitive contains illegal symbol ’z’

Default Severity Warning Description The UDP contains an entry that has illegal symbol ’z’. Example In the following example, because the entry in line 11 has symbol ’z’, mydff will be blackboxed: primitive mydff (qq, clk, dd, ss, rr); output qq; reg qq; input clk, dd, ss, rr; table // clk dd ss rr : qq : qq+ r 0 0 0 : ? : 0 ; r 1 0 0 : ? : 1 ; f ? 0 0 : ? : - ; ? ? 1 0 : ? : 1 ; ? ? 0 1 : ? : 0 ; ? ? 1 1 : ? : z ; endtable endprimitive

May 2008

762

Product Version 7.2


UDP4.2 Message Primitive contains an ’x’ output without an ’x’ input

Default Severity Warning Description The UDP contains an entry that has an ’x’ value output without an ’x’ value input. Example In the following example, the last line of the table has ’x’ as an output, and its input does not contain ’x’: primitive mydff (qq, clk, dd, ss, rr); output qq; reg qq; input clk, dd, ss, rr; table // clk dd ss rr : qq : qq+ r 0 0 0 : ? : 0 ; r 1 0 0 : ? : 1 ; f ? 0 0 : ? : ; ? ? 1 0 : ? : 1 ; ? ? 0 1 : ? : 0 ; ? ? 1 1 : ? : x ; endtable endprimitive

May 2008

763

Product Version 7.2


Verilog This category of rules applies to designs that are written in Verilog language. RTL rules apply to Verilog designs and VHDL designs (see “Register Transfer Level” on page 603). The following table lists the Verilog (VLG) rule numbers and their messages. Rule Number

Message

VLG1.1

Case inequality operators are treated as logical inequality operators

VLG1.2

Case equality operators are treated as logical equality operators

VLG1.3

Wild inequality is treated as inequality

VLG1.4

Wild equality is treated as equality

VLG2.1

Non-constant case-item is used in casex/casez statement

VLG2.2

Non-binary case-item is used in casex/casez statement

VLG2.3

default keyword is not the last item in case statement(s)

VLG3.1

Unsized constant(s) with leading X/Z value is extended beyond 32 bits

VLG3.2

Verilog event expression in always block(s) are complex

VLG3.3

Replication is not a constant or it contains X or Z values

VLG3.4

Zero replication is treated as NULL in concatenation

VLG3.5

Null expression is not allowed (caused by zero replication)

VLG3.6

Negative replication is not allowed

VLG3.7

Unsized constant value is set to 32-bit in concatenation

VLG4.1

Wire type wand is used

VLG4.2

Wire type wor is used

VLG4.3

Implicit declared net is generated

VLG4.4

Cutpoint not found

VLG5.1

Primitive output port has multiple bits. Ignored all but LSB bit

VLG5.2

Primitive input port has multiple bits. Ignored all but LSB bit

VLG5.3

Wire and port size declaration(s) do not match

May 2008

764

Product Version 7.2


Rule Number

Message

VLG5.4

Port size of array instance does not match

VLG5.5

Named port association ignored for primitive gate

VLG5.6

Named port association is ignored for primitive gate

VLG6.1

Globally referenced variable is unresolved

VLG6.2

Globally referenced variable resolved

VLG6.3

Unsupported system function call (converted to 1'b1)

VLG6.3a

Unsupported system task call

VLG6.4

Supported system datapath function call

VLG6.5

Time literal is unsupported

VLG6.6

Event object is unsupported

VLG6.7

Hierarchical function call is not supported (blackboxed)

VLG6.8

Specify block is ignored

VLG6.10

Intra-assignment event specification is not supported

VLG6.12

fork-join constructs are not supported

VLG6.13

force-release constructs are not supported

VLG6.14

Global reference on the left side of the assignment is not supported

VLG6.15

disable construct is not supported

VLG6.16

wait construct is not supported

VLG7

Nets renamed after removing backslash

VLG8

Buffer inserted

VLG9

Names conflict with previous declarations

VLG9.1

Text macro is redefined

VLG9.2

‘define macro is used

VLG9.4

Instance name conflicts with previous declarations

VLG10

Non-blocking assignment is in disabled block

VLG10.1

Non-blocking assignment encountered in function

May 2008

765

Product Version 7.2


Rule Number

Message

VLG10.2

deassign statements cannot be synthesized and are not supported

VLG10.3

Sequential assign statement is not supported

VLG11.1

Combinational logic is inferred in an always_latch block

VLG11.2

Latches are inferred in an always_comb block

VLG12.1

Null statement ’;’ is not allowed inside a begin-end block and is ignored

VLG13.1

Unpacked dimension is not allowed

VLG13.2

Unsized dimension is not allowed

VLG13.3

Associative dimension is not allowed

VLG14.1

Missing module instance name

VLG15.1

Block name is previously declared

VLG16.1

Syntax error in Verilog instantiation

May 2008

766

Product Version 7.2


VLG1.1 Message Case inequality operators are treated as logical inequality operators

Default Severity Warning Description The design includes one or more case inequality operators that the checker treats as logical inequality operators. Inequality operators syntax: !== is a case inequality operator. != is a logical inequality operator.

Example In the following example, the checker treats the case inequality operator as a logical inequality operator. See line 7 (in bold). module VLGT (clk,cond,in0,in1,out0); input clk,in0,in1; input [1:0] cond; output out0; reg out0; always @(posedge clk) begin if (cond[0] !== cond[1]) out0 <= in0; else out0 <= in1; end endmodule

May 2008

767

Product Version 7.2


VLG1.2 Message Case equality operators are treated as logical equality operators

Default Severity Warning Description The design includes one or more case equality operators that the checker treats as logical equality operators. Equality operators syntax: === is a case equality operator. == is a logical equality operator.

Example In the following example, the checker treats the case equality operator as a logical equality operator. See line 7 (in bold). module VLGT (clk,cond,in0,in1,out0); input clk,in0,in1; input [1:0] cond; output out0; reg out0; always @(posedge clk) begin if (cond[0] === cond[1]) out0 <= in0; else out0 <= in1; end endmodule

May 2008

768

Product Version 7.2


VLG1.3 Message Wild inequality is treated as inequality

Default Severity Warning Description The checker does not support the !?= SystemVerilog operator with the exact semantics supported in simulation. The checker treats !?= as !=. Example In the following example, the checker encounters !?= on line 4 (in bold) and treats it as !=. Similarly, on line 5, the checker treats !== (case inequality) as !=. (Refer to VLG1.1 on page 767.) module test(aa, bb, o1, o2); input aa, bb; output o1, o2; assign o1 = aa !?= bb; assign o2 = aa !== bb; endmodule

May 2008

769

Product Version 7.2


VLG1.4 Message Wild equality is treated as equality

Default Severity Warning Description The checker does not support the =?= SystemVerilog operator with the exact semantics supported in simulation. The checker treats =?= as ==. Example In the following example, the checker encounters =?= on line 4 (in bold) and treats it as ==. Similarly, on line 5, the checker treats === (case equality) as ==. (Refer to VLG1.2 on page 768.) module test(aa, bb, o1, o2); input aa, bb; output o1, o2; assign o1 = aa =?= bb; assign o2 = aa === bb; endmodule

May 2008

770

Product Version 7.2


VLG2.1 Message Non-constant case-item is used in casex/casez statement

Default Severity Note Description The design includes one or more case_items that use a non-constant value in a casex or casez statement. Sample casex statement syntax: casex

(case_expression) case_item1 : case_item_statement1; case_item2 : case_item_statement2; default : case_item_statement3;

endcase

Example In the following example, the design uses primary input a for the second case_item (see line 9). module test ( a, b, input a, b, c; input sel; output out0; reg out0; always @(sel or a casex(sel) 1'b1 : out0 a : out0 default: out0 endcase end endmodule

May 2008

c, sel, out0);


771

Product Version 7.2


VLG2.2 Message Non-binary case-item is used in casex/casez statement

Default Severity Note Description The design includes one or more case_items that use a non-binary value in a casex or casez statement. Example casex statement syntax: case

(case_expression) case_item1 : case_item_statement1; case_item2 : case_item_statement2; default : case_item_statement3; endcase

Example In the following example, the design uses an X value for the second case_item. See line 9 (in bold). module test ( a, b, input a, b, c; input sel; output out0; reg out0; always @(sel or a casex(sel) 1'b1 : out0 1'bx : out0 default: out0 endcase end endmodule

May 2008

c, sel, out0);


772

Product Version 7.2


VLG2.3 Message default keyword is not the last item in case statement(s)

Default Severity Warning Description The default keyword is not the last case_item in one or more case statements. Sample case statement syntax: case

(case_expression) case_item1 : case_item_statement1; case_item2 : case_item_statement2; default : case_item_statement3; endcase

Example In the following example, the keyword default is not the last case_item. See line 9 (in bold). module test ( a, b, c, input a, b, c; input sel; output out0; reg out0; always @(sel or a or casex(sel) 1'b1 : out0 = default: out0 = 1'b0 : out0 = endcase end endmodule

May 2008

sel, out0);

b or c) begin a; c; b;

773

Product Version 7.2


VLG3.1 Message Unsized constant(s) with leading X/Z value is extended beyond 32 bits

Default Severity Warning Description One or more unsized constants with a leading X/Z value are extend beyond 32 bits. Example In the following example, the design assigns an unsized constant with leading X value 'bx to a 34-bit output out0 (see line 5). module test(out0,y,in); output [33:0] out0; output y; input in; assign out0 = 'bx; assign y = in; endmodule

May 2008

774

Product Version 7.2


VLG3.2 Message Verilog event expression in always block(s) are complex

Default Severity Warning Description The Verilog event expressions used in one or more always blocks are complex. Example In the following example, event expression a|b is considered complex (see line 5). module test (a, b, q); input [3:0] a, b; output [3:0] q; reg [3:0] q; always @ (a | b ) begin q = a & b; end endmodule

May 2008

775

Product Version 7.2


VLG3.3 Message Replication is not a constant or it contains X or Z values

Default Severity Warning Description A replication multiplier is not a constant or it contains X or Z values. Note: This check has a warning default severity level, but the module is blackboxed. Example In the following example, replication 2’bx is illegal value (see line 6). module test (a, q); input [3:0] a; output [4:0] q; reg [4:0] q; always @ (a ) begin q = {{2’b1x{1’b1}}, 1’b0}; end endmodule

May 2008

776

Product Version 7.2


VLG3.4 Message Zero replication is treated as NULL in concatenation

Default Severity Warning Description A replication multiplier is a constant 0 but the entire concatenation remains valid. The replicated concatenation portion is treated as NULL as if the portion is removed from the entire concatenation. Example In the following example, replication 2’b0 is illegal value (see line 6). module test (a, q); input [3:0] a; output [4:0] q; reg [4:0] q; always @ (a ) begin q = {{2’b0{2’b1}}, 1’b0}; end endmodule

May 2008

777

Product Version 7.2


VLG3.5 Message Null expression is not allowed (caused by zero replication)

Default Severity Warning Description A replication multiplier is a constant 0 and the entire concatenation becomes NULL. The replicated concatenation portion is treated as NULL as if the portion is removed from the entire concatenation. Note: This check has a warning default severity level, but the module is blackboxed. Example In the following example, on line 6 the replication multiplier is a constant 0 and the entire concatenation becomes NULL, which is not allowed. module test (a, q); input [3:0] a; output [4:0] q; reg [4:0] q; always @ (a ) begin q = {2’b0{2’b1}}; end endmodule

May 2008

778

Product Version 7.2


VLG3.6 Message Negative replication is not allowed

Default Severity Warning Description A replication multiplier is a negative integer constant. Note: This check has a warning default severity level, but the module is blackboxed. Example In the following example, replication -1 is not allowed (see line 6). module test (a, q); input [3:0] a; output [4:0] q; reg [4:0] q; always @ (a ) begin q = {{-1{2’b1}}, 4’b1}; end endmodule

May 2008

779

Product Version 7.2


VLG3.7 Message Unsized constant value is set to 32-bit in concatenation

Default Severity Warning Description The unsized constant value is set to 32-bit in concatenation. Example In the following example, 1 is an unsized constant value, will be set to 32-bit in concatenation (see line 6). module test (a, q); input [3:0] a; output [4:0] q; reg [4:0] q; always @ (a ) begin q = {1, 4’b1}; end endmodule

May 2008

780

Product Version 7.2


VLG4.1 Message Wire type wand is used

Default Severity Warning Description The design includes a user-specified wire-AND resolution for one or more multi-driven nets. Example In the following example, the design declares wire wand, which is used for multi-driven output q. See line 4 (in bold). module test (a,b,q); input a, b; output q; wand q; assign q = a assign q = b; endmodule

May 2008

781

Product Version 7.2


VLG4.2 Message Wire type wor is used

Default Severity Warning Description The design includes a user-specified wire-OR resolution for one or more multi-driven nets. Example In the following example, the design declares wire wor, which is used for multi-driven out0. See line 5 (in bold). module test ( a, b, c, sel, out0); input a, b, c; input sel; output out0; wor out0; assign out0 = a; assign out0 = b; endmodule

May 2008

782

Product Version 7.2


VLG4.3 Message Implicit declared net is generated

Default Severity Warning Description An implicit declared net is generated. Example In the following example, in_top is an implicit declared net (see line 13): `default_nettype none module test(out,in); input in; output out; reg out; always @(in) begin if (in ) out = in; else out = ~in; end endmodule module top (out_top); output out_top; test s1(out_top,in_top); endmodule

May 2008

783

Product Version 7.2


VLG4.4 Message Cutpoint not found

Default Severity Warning Description Cannot find the specified cutpoint. Example In the following example, the pragma cutpoint ram2 cannot be found in the design (see line 7): module test(clk, addr, din, dout); input clk; input [1:0] addr; input [0:0] din; output [0:0] dout; reg [0:0] ram [3:0]; // pragma cutpoint "ram2" always @(clk or addr or din) begin if (clk && ram[0] ) ram[addr[1:0]] = din; end assign dout = ram[addr[1:0]]; endmodule

May 2008

784

Product Version 7.2


VLG5.1 Message Primitive output port has multiple bits. Ignored all but LSB bit

Default Severity Warning Description The design includes one or more primitive output ports with multiple bits. The checker ignores all but the least significant bit (LSB) of the primary vector output. Example In the following example, output o has three bits. The checker only keeps the LSB. See line 4 (in bold). module test(o,a,b); output [2:0] o; input a,b; and(o,a,b); endmodule

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VLG5.2 Message Primitive input port has multiple bits. Ignored all but LSB bit

Default Severity Warning Description One or more primitive input ports have multiple bits. The checker changes all primitive vector input ports to scalar input ports by applying OR logic reduction. Example In the following example, the checker reduces the two-bit input a to a single-bit input a by OR-ing a[0] and a[1] together. See line 5 (in bold). module test ( a, out0); input[1:0] a; output out0; wire out0; not (out0,a); endmodule

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786

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VLG5.3 Message Wire and port size declaration(s) do not match

Default Severity Warning Description In one or more cases, the design’s wire and port size declarations do not match. Example In the following example, the declared size of input ports a and b is [3:0], but the declared size of wires a and b is [4:0]. See lines 2 and 4 (in bold). module test (a, b, q); input [3:0] a, b; output [3:0] q; wire [4:0] a, b; assign q = a & b; endmodule

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787

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VLG5.4 Message Port size of array instance does not match

Default Severity Warning Description In one or more cases, port sizes of an array instance do not match. Example In the following example, output o has a port size of [2:0], but inputs a and b have a port size of [1:0] for instance array u1[1:0]. See lines 2 and 3. module test(o,a,b); output [2:0] o; input [1:0] a,b; and u1[1:0] (o,a,b); endmodule

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788

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VLG5.5 Message Named port association ignored for primitive gate

Default Severity Warning Description The checker triggers this rule check when it encounters an internal primitive. This rule check helps identify module instances that you should treat as blackboxes. Example In the following example, you might want to treat AND as a blackbox. See line 2. module test4(input aa, bb, output oo); AND u0(oo, aa, bb); endmodule

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789

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VLG5.6 Message Named port association is ignored for primitive gate

Default Severity Warning Description The checker ignores the named port association for the primitive gate. Example In the following example, line 2 uses the named port association: module test(input aa, bb, output oo); AND u0(.o(oo), .a(aa), .b(bb)); endmodule

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790

Product Version 7.2


VLG6.1 Message Globally referenced variable is unresolved

Default Severity Warning Description The checker cannot find the globally referenced variable. Thus, the variable remains unresolved. Example In the following example, on line 16 (in bold), the checker cannot find variable x in module sub. Thus, variable x remains as an undriven net. module sub (a, b, c); input [7:0] a, b; output [7:0] c; wire [7:0] wiretmp ; assign wiretmp = a & b; assign c = wiretmp ; endmodule module main (i1, i2, o1, o2); input [7:0] i1, i2; output [7:0] o1; output o2; sub inst1 (i1, i2, o1); assign o2= inst1.x; endmodule

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791

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VLG6.2 Message Globally referenced variable resolved

Default Severity Note Description The checker found the globally referenced variable. Example In the following example, on line 16 (in bold), the checker finds variable tmp in module sub. module sub (a, b, c); input [0:0] a, b; output [0:0] c; wire [0:0] tmp ; assign tmp = a & b; assign c = tmp ; endmodule module main (i1, i2, o0, o1, o2, o3); input [0:0] i1, i2; output o0; output [0:0] o1, o2, o3; sub inst1 (.a(i1), .b(i2), .c(o1)); assign o2 = inst1.tmp ; endmodule

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792

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VLG6.3 Message Unsupported system function call (converted to 1'b1)

Default Severity Warning Description The checker does not support the $system/$user_pli function calls; instead, the checker approximates the $system/$user_pli function call to 1'b1. Example In the following example, the checker approximates $random and $time to 1’b1. See lines 4 and 5. module test(aa, bb, o1, o2); input aa, bb; output o1, o2; assign o1 = $random; assign o2 = $time; endmodule

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793

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VLG6.3a Message Unsupported system task call

Default Severity Error Description $systemtask(...) is called as a concurrent statement in Verilog. Note: This check has default error severity level, but you can set it to lower severity level to skip the error checking. Example In the following example, concurrent systemtask $mytask is not supported module m1(aa, bb, oo); input aa, bb; output oo; $mytask(aa, bb, oo); endmodule

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794

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VLG6.4 Message Supported system datapath function call

Default Severity Note Description The checker triggers this rule check when it encounters any supported datapath functions. Conformal supports the following datapath functions. $abs() $blend() $carrysave() $compge() $intround() $inttrunc() $lead0() $lead1() $log2() $max() $min() $rotatel() $rotater() $round() $sat() $sgnmult()

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VLG6.5 Message Time literal is unsupported

Default Severity Warning Description The checker does not support time literals, such as 1fs, 2ps, and 3ns, and that it converted the time literals to 1’b1. Example In the following example, Conformal converts (2ns > 1ns) to (1’b1 > 1’b1). See line 4. module test5(input aa, bb, output oo); reg oo; always @* begin if (2ns > 1ns) oo = !aa; else if (aa || bb) oo = aa; else oo = 1’b0; end endmodule

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796

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VLG6.6 Message Event object is unsupported

Default Severity Warning Description The event object is not supported. Example In the following example, -> ev (see line 7) is not supported: module top (input in, output out); test test1(in, out); endmodule module test(input aa, output oo); event ev; always begin -> ev; oo = aa; end endmodule

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797

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VLG6.7 Message Hierarchical function call is not supported (blackboxed)

Default Severity Warning Description The hierachical function call is not supported and will be blackboxed. Example In the following example, line 16 shows the unsupported hierachical function call: module mod1 (input in1, output out1); reg out1; function ftn1; input in1; begin if (in1 == 0) ftn1 = in1; else ftn1 = 1; end endfunction always @(in1) out1 = ftn1(in1); endmodule module mod2 (input in2, output out2); reg out2; always @(in2) out2 = mod1.ftn1(in2); endmodule

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798

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VLG6.8 Message Specify block is ignored

Default Severity Ignore Description The specify block is ignored. In a design, Verilog specify blocks contain path delay information that is not used in static verification. As a result, the contents of a specify block are ignored. Some library cells may have notifier registers used in a specify block that can potentially affect the logic. Specify blocks are non-synthesizable. Example In the following example, specify (line 5) is ignored: module specify_blk ( o, i); input i; output o; buf(o, i); specify specparam T1RISE$ = 2.7; ( i *> o ) =( 183:311:549 , endspecify endmodule

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799

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VLG6.10 Message Intra-assignment event specification is not supported

Default Severity Warning Description This construct is not supported because intra-assignment event specifications are not synthesizable. Cadence recommends that you remodel your HDL source code. Example In the following example, the intra-assignment in line 8 is not supported: module intra_assign_evt (clk, cout); input clk; output [3:0] cout; reg [3:0] cout; always @(posedge clk) begin cout = 4’b0; cout = @(posedge clk) cout + 1; end endmodule

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800

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VLG6.12 Message fork-join constructs are not supported

Default Severity Warning Description The design includes fork-join constructs. The fork-join constructs cannot be synthesized, and are not supported. To avoid this error, remodel the design. Example In the following example, the fork and join contructs (lines 7 and 10) are not supported: module neg_fork_join (clk, cout); input clk; output cout; reg cout; always @(posedge clk) begin fork cout = 1’b0; cout = 1’b1; join end endmodule

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801

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VLG6.13 Message force-release constructs are not supported

Default Severity Warning Description The design includes force-release constructs. The force-release constructs cannot be synthesized. To avoid this error, remodel your design. Example In the following example, the force and release contructs (lines 7 and 10) are not supported: module force_release (clk, cin, cout); input clk; input cin; output cout; reg cout; always @ (posedge clk) begin force cout = 1’b1; cout = cin; release cout; end endmodule

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802

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VLG6.14 Message Global reference on the left side of the assignment is not supported

Default Severity Warning Description A global reference on left side of the assignment is not supported. Example In the following example, botInst.memNd (line 5) is a global reference on left side of the assignment and is not supported: module test(d); input [1:0] d; bot botInst(); always @(d) botInst.memNd[0] = d; endmodule module bot(); reg [1:0] memNd [7:0]; endmodule

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803

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VLG6.15 Message disable construct is not supported

Default Severity Warning Description The disable construct is supported only when applied to an enclosing named block. The Conformal software cannot disable tasks and non-enclosing named blocks. Remodel the design to avoid this error. Example In the following example, specify (line 5) is ignored: xxxxxxxxxxxxxxx module test; always begin : break end endmodule module top; test t(); integer i; always begin if (i==1) begin:cont disable top.t.break; end end endmodule

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804

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VLG6.16 Message wait construct is not supported

Default Severity Warning Description The design includes a Verilog wait event control, which is not supported. You will need to remodel the design. Example In the following example, the wait event control (line 7) is not supported: module neg_wait (enable, a, b, c, d); input enable, b, d; output a, c; reg a, c; always @(enable or b or d) begin wait (!enable) #10 a = b; #10 c = d; end endmodule

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805

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VLG7 Message Nets renamed after removing backslash

Default Severity Warning Description The checker has renamed one or more net names. The checker renames all net names that include a backslash (\). Example In the following example, net name \out3[0] will be renamed out3[0]1. See line 4 (in bold). module test ( in1, in2, out3 ); output [1:0] out3; input in1, in2; wire \out3[0] ; assign \out3[0] = in1 & in2; assign out3[1] = \out3[0] ; assign out3[0] = \out3[0] ; endmodule

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806

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VLG8 Message Buffer inserted

Default Severity Note Description The checker has inserted one or more buffers because the design includes the $setuphold or $recrem timing checks from the Verilog IEEE Std P1364-Y2K. Example In the following example, the design uses the $setuphold timing check. See line 11 (in bold). module test (CK,D,O); output O; reg O; input CK,D; wire D_del,CK_del; buf (CK_del,CK); buf (D_del,D); always @(posedge CK_del) O <= D; specify $setuphold (posedge CK,posedge D, tsu_d_h_ck,th_ck_d_l, notifier,,,CK_del,D_del endspecify endmodule

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VLG9 Message Names conflict with previous declarations

Default Severity Warning Description The checker found a name conflict among declarations. Example In the following example on line 12 (in bold), instance a has the same name as input a at line 9 (in bold). module test (din, dout); input din; output dout; assign dout=din; endmodule module top (a , b); input a; output b; test a (a,b); endmodule

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808

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VLG9.1 Message Text macro is redefined

Default Severity Warning Description The text macro is redefined. Example In the following example, val1 is redefined (see line 2): define val1 0 `define val1 1 module test (din, dout); input din; output dout; assign dout=din; endmodule

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809

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VLG9.2 Message ‘define macro is used

Default Severity Note Description The ‘define macro is used in the Verilog files. Example In the following example, ‘define macro is used (see line 1): `define VAL module test(in,out); input in; output out; assign out = in; endmodule

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810

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VLG9.4 Message Instance name conflicts with previous declarations

Default Severity Error Description The checker found a name conflict among instance declarations. Example In the following example, u0 is redefined (see line 6): module GCLK (clko, clki, ena); input clki, ena; output clko; not u0 (clki, clki); DLAT l0 (q0, 1’b0, 1’b0, clki_, ena); and u0 (clko, q0, clki); endmodule

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VLG10 Message Non-blocking assignment is in disabled block

Default Severity Warning Description There are non-blocking assignments in a disabled block. These kind of assignments might have undefined behavior. Example In the following example, the disabled blk1 block contains a non-blocking assignment on line 6 (in bold). module test (clk, a,b); input clk,a; output b; always @(posedge clk) begin:blk1 b <= a; disable blk1; end endmodule

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812

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VLG10.1 Message Non-blocking assignment encountered in function

Default Severity Error Description Non-blocking assignment was detected inside the function. You should not use non-blocking statements inside functions. Such usage can lead to compilation failures. Example In the following example, get_address (line 12) is a non-blocking assignment: module top (clk, result); input clk; output [3:0] result; reg [3:0] result; reg [1:0] state_var; function [3:0] get_address; input [1:0] state_var; begin case (state_var) 2’b00: begin get_address <= "0000"; end endcase end endfunction always @(posedge clk) begin result = get_address(2’b0); end endmodule

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VLG10.2 Message deassign statements cannot be synthesized and are not supported

Default Severity Warning Description The deassign statements cannot be synthesized. Example In the following example, the deassign statment in line 13 is not supported: module DeassignMod(a,b); input a; output b; reg b; reg reset, clk; always begin if(clk) b = a; else if(reset) b = ~a; else deassign b; end endmodule

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814

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VLG10.3 Message Sequential assign statement is not supported

Default Severity Warning Description Sequential ’assign’ statement is not supported. Example In the following example, the sequential assign statment in line 13 is not supported: module assignMod(a,b); input a; output b; reg b; reg reset, clk; always begin if(clk) b = a; else if(reset) b = ~a; else assign b = 0; end endmodule

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VLG11.1 Message Combinational logic is inferred in an always_latch block

Default Severity Warning Description There is combinational logic inferred in an always_latch block. Latches are expected to have inferred logic. Example In the following example, the always_latch block contains combinational logic on line 7. module test(a,in1,in2,o); input a; input byte in1, in2; output byte o; always_latch begin o = in1 & in2; end endmodule

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VLG11.2 Message Latches are inferred in an always_comb block

Default Severity Warning Description This rule check tells that there are inferred latches in an always_comb block. Combinational logic is expected to have inferred logic. Example In the following example, the always_comb block contains an inferred latch on line 7 (in bold). module test(a,in1,in2,o); input a; input byte in1, in2; output byte o; always_comb begin if (a) o = in1 & in2; end endmodule

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817

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VLG12.1 Message Null statement ’;’ is not allowed inside a begin-end block and is ignored

Default Severity Warning Description The null statement ‘:’ is not allowed inside a begin-end block and will be ignored. Example In the following example, the extra null statement (line 7) will be ignored. module test(clk, out1, in1); input clk, in1; output out1; reg out1; always @(posedge clk) begin out1 <= in1;; end endmodule

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VLG13.1 Message Unpacked dimension is not allowed

Default Severity Warning Description The unpacked dimension declaration is not allowed. It is only allowed for SystemVerilog. Example In the following example, in line 4, the unpacked dimension for the wire declaration is only allowed in SystemVerilog. module test (aa, bb, oo); input aa, bb; output oo; wire tt[1:0]; assign tt[0] = aa; assign tt[1] = bb; assign oo = tt[0] && tt[1]; endmodule

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VLG13.2 Message Unsized dimension is not allowed

Default Severity Warning Description The unsized dimension is not allowed. Using unsized dimension in an array declaration will cause SystemVerilog module to be blackboxed. Example The following SystemVerilog examples are not allowed and will cause modules to be blackboxed: task foo( string arr[] ); // Dynamic array of strings bit [3:0] nibble[]; // Dynamic array of 4-bit vectors integer mem[]; // Dynamic array of integers

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820

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VLG13.3 Message Associative dimension is not allowed

Default Severity Warning Description The SystemVerilog associative dimension is not allowed. Using associative dimension will cause SystemVerilog module to be blackboxed. Example The following SystemVerilog examples are not allowed and will cause module to be blackboxed: integer i_array[*]; // associative array of integer (unspecified index) bit [20:0] array_b[string]; // associative array of 21-bit vector, indexed by string event ev_array[myClass]; // associative array of event indexed by class myClass

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VLG14.1 Message Missing module instance name

Default Severity Error Description The instance name is missing for the module. Example In the following example, in line 3, the instance name is missing for instantiation of module sub: module top(); wire m, n, k; sub (.o(k), .a(m), .b(n)); endmodule

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VLG15.1 Message Block name is previously declared

Default Severity Error Description Indicates that the block name is previously declared in the same scope. Example In the following example, in line 9, block name ’b1’ in redeclared: module test(clk,in, out); input in,clk; output reg out; always @(clk) begin begin:b1 out = in; end begin: b1 out = ~in; end end endmodule

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823

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VLG16.1 Message Syntax error in Verilog instantiation

Default Severity Error Description Indicates that a syntax error was found in the Verilog instantiation. The correct syntax is ’ (...)’. Example In the following example, in line 4, the correct syntax is ’test sub(...)’. module top(din, dout); input din; output dout; test sub; endmodule

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4 Modeling Messages This chapter lists and describes the modeling messages you encounter when the system mode changes from Setup to LEC in the Encounter® Conformal® software.

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Encounter Conformal Equivalence Checking Reference Manual Modeling Messages

F1 Message Modeled multiple-driven net(s)

Description A multi-driven net has been remodeled into Boolean logic based on how the SET WIRE RESOLUTION command is set. Example Sample modeling message: F1: Modeled multiple-driven net(s) (Occurrence: 1) 1: /n1 (and) In this message: ■

/n1 is a multi-driven net

■

(and) indicates that SET WIRE RESOLUTION is set to AND

The following code illustrates a circuit with a net “n1” that has multiple drivers “u0” and “u1”: not u0 (n1,a); not u1 (n1,b); not u2 (z,n1); Associated Commands SET WIRE RESOLUTION

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F2 Message Inserted user cut point(s)

Description Conformal inserted a cut point to break a combinational loop. This operation is enabled when you use the ADD CUT POINT command. Example Sample modeling message: F2: Inserted user cut point(s) (Occurrence: 1) 1: CUT /n1 In this message: ■

CUT indicates the gate type

■

/n1 indicates the net name

You get this message when you add a cut point at net “n1” using the following command: add cut point n1 -golden Circuit example: mux u0 (n1,n1,d,ck); xor u1 (q,n1); Associated Commands ADD CUT POINT

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F3 Message Inserted system cut point(s)

Description A cut point has been inserted automatically to break a combinational loop. Example Sample modeling message: F3: Inserted system cut point(s) (Occurrence: 1) 1: MUX /u0 In this message: ■

MUX is the gate type

■

/u0 is the driver instance name

The following circuit example inserts CUT gate at the output of a MUX instance “u0”: mux u0 (n1,n1,d,ck); xor u1 (q,n1);

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F5 Message Folded DLAT(s) into DFF(s)

Description D-latches (DLATs) were folded into D flip-flops (DFFs). This operation is enabled when you use the SET FLATTEN MODEL -LATCH_FOLD command, which specifies that two latches that are in a master-slave configuration should be converted into a single DFF gate. This operation is also affected by the SET FLATTEN MODEL -LATCH_FOLD_MASTER command. Example Sample modeling message: F5: Folded DLAT(s) into DFF(s) (Occurrence: 1) 1: /l1 /l0 In this message, /l1 and /l0 are the instance names of the folded DLATs. You would get this modeling message if you use the following command to convert two master-slave DLATs “l0” and “l1” into a DFF: set flatten model -latch_fold Circuit example: not u0 (ck_,ck); DLAT l0 (n1,,1’b0,1’b0,ck_,d); DLAT l1 (q ,,1’b0,1’b0,ck,n1); Associated Commands SET FLATTEN MODEL -LATCH_FOLD SET FLATTEN MODEL -LATCH_FOLD_MASTER

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F6 Message Created DLAT(s) due to trireg net(s) or combinational loop(s)

Description A DLAT was created due to trireg net or a series of buffers/inverters that were implemented as a bus-holder. Example Sample modeling message: F6: Created DLAT(s) due to trireg net(s) or combinational loop(s) (Occurrence: 1) 1: DLAT /n1 due to trireg net This message indicates that a DLAT was created on net “n1” for trireg, which is illustrated in the following circuit example: trireg n1; bufif0 u0 (n1,a,s0); bufif0 u1 (n1,b,s1); buf u2 (z,n1);

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F7 Message Set DLAT data port(s) as ZERO due to disabled clock port(s)

Description DLAT data ports were set to zero because there were disabled clock ports. This operation is enabled when you use the SET FLATTEN MODEL -LATCH_FOLD command. Example Sample modeling message: F7: Set DLAT data port(s) as ZERO due to disabled clock port(s) (Occurrence: 1) 1: Set DLAT ’q_reg’ data port ’/d’ to ZERO due to disabled clock port This message indicates that data port “d” of register “q_reg” is tied to logic ZERO because clock port of register “q_reg” is always disabled (logic ZERO). You would get this message if you issue the following command: set flatten model -latch_fold Circuit example: and u0 (g,1’b0,ck); always @(d or g) begin if (g) q <= d; end

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F8 Message Converted DLAT(s) to BUF(s) due to transparency

Description DLATs were converted into buffers because of transparency. This operation is enabled when you use the SET FLATTEN MODEL -LATCH_TRANSPARENT command, which specifies that DLATs should be converted into buffers if the DLAT clock ports are always enabled. Example Sample modeling message: F8: Converted DLAT(s) to BUF(s) due to transparency (Occurrence: 1) 1: DLAT /q_reg This message indicates that a buffer was converted “buf (q,d),” because the clock of register “q_reg” is always enabled (logic ONE). You would get this message if you issue the following command: set flatten model -latch_transparent Circuit example: or u0 (g,1’b1,ck); always @(d or g) begin if (g) q <= d; end Associated Commands SET FLATTEN MODEL -LATCH_TRANSPARENT

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F10 Message Removed redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s)

Description Redundant AND/NAND/OR/NOR fan-in gates for DFFs and DLATs were removed. This operation is enabled when you use the SET FLATTEN MODEL -SEQ_REDUNDANT command. Example Sample modeling message: F10: Removed redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s) (Occurrence: 1) 1: Removed connection from INV /u0 to AND /u1 for DFF /f0_reg This message indicates that the fan-in AND “u1” and INV “u0” gates were optimized for DFF “f0_reg” due to redundant logic. You would get this command if you issue the following command: set flatten model -seq_redundant Circuit example: not u0 (rst_,rst); and u1 (sr,set,rst_); DFF f0_reg(q,,sr,rst,ck,d); Associated Commands SET FLATTEN MODEL -SEQ_REDUNDANT

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F11 Message Removed redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s)

Description Redundant AND/NAND/OR/NOR fan-out gates for DFFs and DLATs were removed. This operation is enabled when you use the SET FLATTEN MODEL -SEQ_REDUNDANT command. Example Sample modeling message: F11: Removed redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s) (Occurrence: 1) 1: Remodeled AND /u0 for DFF /n1_reg This message indicates that the fan-out AND gate “u0” was optimized for DFF “n1_reg” due to redundant logic. You would get this command if you issue the following command: set flatten model -seq_redundant Circuit example: always @(posedge ck or negedge rst ) begin if (!rst) n1 <= 0; else n1 <= d; end and u0 (q,n1,rst); Associated Commands SET FLATTEN MODEL -SEQ_REDUNDANT

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F12 Message Converted DFF(s) to DLAT(s) due to disabled clock port(s)

Description DFFs were converted into DLATs due to disabled clock ports. This operation is enabled when you use the SET FLATTEN MODEL -DFF_TO_DLAT_ZERO, which converts a DFF to a DLAT when the clock port is zero. Example Sample modeling message: F12: Converted DFF(s) to DLAT(s) due to disabled clock port(s) (Occurrence: 1) 1: DLAT /q_reg This message indicates DFF “q_reg” was converted to a DLAT because the clock of the register is always disabled (logic ZERO). You would get this message with the following command: set flatten model -DFF_TO_DLAT_ZERO Circuit example: and u0 (ck1,1’b0,ck); always @(posedge ck1) begin q <= d; end Note: The -DFF_TO_DLAT_ZERO option is enabled by default. Associated Commands SET FLATTEN MODEL -DFF_TO_DLAT_ZERO

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F13 Message Converted DFF(s) to DLAT(s) due to direct feedback

Description DFFs were converted to DLATs due to direct feedback. This operation is enabled when you use the SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK command, which converts a DFF to a DLAT if the DFF’s output feeds back directly to the DFF’s input. Example Sample modeling message: F13: Converted DFF(s) to DLAT(s) due to direct feedback (Occurrence: 1) 1: DLAT /q_reg This message indicates that DFF “q_reg” was converted to a DLAT because of direct feedback from output “q” of the register to its input “d”. You would get this message if you issue the following command: set flatten model -DFF_TO_DLAT_FEEDBACK Circuit example: always @(posedge ck) begin q <= q; end Note: The -DFF_TO_DLAT_FEEDBACK option is enabled by default. Associated Commands SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK

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F14 Message Remodeled gated-clock DFF(s) or DLAT(s) to mux-feedback

Description Gated-clock logic for DFFs or DLATs were remodeled to MUX-feedback. This operation is enabled when you run the SET FLATTEN MODEL command with the -GATED_CLOCK option, which remodels gated-clock logic of the clock port of a DFF. Example Sample modeling message: F14: Remodeled gated-clock DFF(s) or DLAT(s) to mux-feedback (Occurrence: 1) 1: /q_reg (DFF) This message indicates that the de-glitch gating clock DLAT “l0” and enable logic “u1” for register DFF “q_reg” was converted to a mux-feedback DFF You would get this message when issue the following command: set flatten model -GATED_CLOCK Circuit example: not u0 (ck_,ck); DLAT l0 (en,,1’b0,1’b0,ck_,ena); and u1 (ck1,ck,en); always @(posedge ck1) begin q <= d; end Associated Commands SET FLATTEN MODEL -GATED_CLOCK

May 2008

837

Product Version 7.2


F14.1 Message Remodeled gated-clock DFF(s) or DLAT(s) without latch to mux-feedback

Description Conformal remodeled gated-clock logic for DFFs or DLATs without deglitching to MUXfeedback. This operation is enabled when you use the SET FLATTEN MODEL -GATED_CLOCK, which remodels gated-clock logic of the clock port of a DFF. This operation might need the ADD CLOCK command to define the clock pin Example Sample modeling message: F14.1: Remodeled gated-clock DFF(s) or DLAT(s) without latch to muxfeedback(Occurrence: 1) 1: /q_reg (DFF) This message indicates that the gated-clocking enable logic “u1” for register DFF “q_reg” was converted to a mux-feedback DFF. You get this message when you issue the following commands: add clock 0 ck set flatten model -GATED_CLOCK Circuit example: and u0 (ck1,ck,ena); always @(posedge ck1) begin q <= d; end Associated Commands ADD CLOCK

May 2008

838

Product Version 7.2

Encounter Conformal Equivalence Checking Reference Manual Modeling Messages SET FLATTEN MODEL -GATED_CLOCK

May 2008

839

Product Version 7.2


F16 Message Converted DLAT(s) to MUX(s) due to clock inversion relation

Description DLATs were converted into MUXes due to clock inversion relationships. Example Sample modeling message: F16: Converted DLAT(s) to MUX(s) due to clock inversion relation (Occurrence: 1) 1: /l0 This message indicates that a dual-port DLAT “l0” was converted to a MUX - mux l0 (q,d0,d1,ck) due to the clock inversion relationship on the dual-port DLAT clock ports. Circuit example: not u0 (ck_,ck); DLAT l0 (q,,1’b0,1’b0,ck_,d0,ck,d1);

May 2008

840

Product Version 7.2


F17 Message Converted DLAT(s) to BUF(s)/INV(s) due to set/reset inversion relation

Description DLATs were converted to buffers/inverters due to set/reset inversion relationships. Example Sample modeling message: F17: Converted DLAT(s) to BUF(s) due to set/reset inversion relation (Occurrence: 1) 1: /l0 This message indicates that a DLAT “l0” was converted to a buffer, buf l0 (q,a), because of set/reset inversion relationships on asynchronous set/reset of DLAT. Circuit example: not u0 (a_,a); DLAT l0 (q,,a,a_,ck,1’b0);

May 2008

841

Product Version 7.2


F18 Message Converted DFF/DLAT(s) to ZERO/ONE

Description Conformal converted a DFF or a DLATs to a ZERO or ONE gate. This operation is enabled when you use the SET FLATTEN MODEL -SEQ_CONSTANT command, which converts a DFF or DLAT to a ONE or ZERO gate if the data port is a one or zero. This operation is also affected by the SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK command. Example Sample modeling message: F18: Converted DFF/DLAT(s) to ZERO/ONE (Occurrence: 1) 1: DFF /n1_reg (ZERO) This message indicates that DFF “n1_reg” was converted to logic ZERO because data port is tied to logic ZERO. You would get this message if you issue the following command: set flatten model -seq_constant Circuit example: always @ (posedge ck) n1 <= 1’b0; assign q = a | n1; Associated Commands SET FLATTEN MODEL -SEQ_CONSTANT SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK

May 2008

842

Product Version 7.2


F19 Message Merged DFF(s) or DLAT(s) in clock cones

Description Sequentially equivalent DFFs or DLATs in clock cones were merged. This operation is enabled when you use the SET FLATTEN MODEL -SEQ_MERGE command. Example Sample modeling message: F19: Merged DFF(s) or DLAT(s) in clock cones (Occurrence: 1) 1: DFF /ck0_reg /ck1_reg This message indicates that DFF “ck0_reg” and DFF “ck_reg” were merged into a single DFF because the two DFFs were sequentially equivalent. You would get this message when you issue the following command: set flatten model -seq_merge Circuit example: always @ (posedge ck) begin ck0 <= a; ck1 <= a; end always @ (posedge ck0) q0 <= d; always @ (posedge ck1) q1 <= d; Associated Commands SET FLATTEN MODEL -SEQ_MERGE May 2008

843

Product Version 7.2


F20 Message Merged DFF(s) or DLAT(s)

Description Sequentially equivalent DFFs and DLATs were merged. This operation is enabled when you use the SET FLATTEN MODEL -ALL_SEQ_MERGE command, which merges common groups of sequential elements into one sequential element in a logic cone of a key point. Example Sample modeling message: F20: Merged DFF(s) or DLAT(s) (Occurrence: 1) 1: DFF /q0_reg /q1_reg This message indicates that DFF “q0_reg” and DFF “q_reg” were merged into a single DFF because the two DFFs are sequentially equivalent. You would get this message if you use the following command: set flatten model -all_seq_merge Circuit example: always @ (posedge ck) begin q0 <= d; q1 <= d; end Associated Commands SET FLATTEN MODEL -ALL_SEQ_MERGE

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844

Product Version 7.2


F21 Message Merged DFF(s) or DLAT(s) defined by user

Description User-defined DFFs or DLATs were merged using the ADD INSTANCE EQUIVALENCES command. Example Sample modeling message: F21: Merged DFF(s) or DLAT(s) defined by user (Occurrence: 1) 1: DFF /q0_reg /q1_reg This message indicates that you merged two DFFs “q0_reg” and DFF “q1_reg” into a single DFF using the following command: add instance equivalences /q0_reg /q1_reg -golden Circuit example: always @ (posedge ck) begin q0 <= d; q1 <= d; end Associated Commands ADD INSTANCE EQUIVALENCES

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845

Product Version 7.2


F23 Message Merged DFF(s) or DLAT(s) multiple ports into single port due to equivalence

Description Multiple ports belonging to DFFs or DLATs into one single port due to equivalence were merged. Example Sample modeling message: F23: Merged DFF(s) or DLAT(s) multiple ports into single port due to equivalence (Occurrence: 1) 1: DFF /f0 This message indicates that a dual-port DFF “f0_reg” with equivalent data and clock port was merged into a single port DFF - DFF f0_reg (q,,1’b0,1’b0,ck,d). Circuit example: buf n0 (d0,d); buf n1 (d1,d); DFF f0_reg (q,,1’b0,1’b0,ck,d0,ck,d1); Associated Commands None.

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846

Product Version 7.2


F25 Message Pipeline-retimed DFF(s) to outputs

Description DFFs to outputs were pipeline-retimed. This operation is enabled when you use the ADD MODULE ATTRIBUTE -PIPELINE_RETIME, which checks specified modules for pipeline retiming and remodels when necessary. Example Sample modeling messages: Report modeling message for Revised F25: Pipeline-retimed DFF(s) to outputs (Occurrence: 1) 1: Pipeline retimed DFF ’q_reg’ to output Report modeling message for Revised F25: Pipeline-retimed DFF(s) to outputs (Occurrence: 2) 1: Pipeline retimed DFF ’a1_reg’ to output 2: Pipeline retimed DFF ’b1_reg’ to output These messages indicate that the DFF “a1_reg” and DFF “b1_reg” performed pipelineretiming to the outputs. You would get these messages if you issue the following command: add module attribute ckt -pipeline_retime Circuit example: Golden: assign n1 = a & b; always @(posedge ck) q <= n1; Revised: always @(posedge ck) begin May 2008

847

Product Version 7.2

Encounter Conformal Equivalence Checking Reference Manual Modeling Messages a1 <= a; b1 <= b; end assign q = a1 & b1; Associated Commands ADD MODULE ATTRIBUTE -PIPELINE_RETIME

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848

Product Version 7.2


F26 Message Merged dual-port DLAT(s) into single port DLAT(s)

Description Dual-port DLATs were merged into single-port DLATs. This operation is enabled when you use the SET FLATTEN MODEL -LATCH_MERGE_PORT command. Example Sample modeling message: F26: Merged dual-port DLAT(s) into single port DLAT(s) (Occurrence: 1) 1: Merged multi-port DLAT ’/l0’ into single port DLAT This message indicates that dual-port DLAT “l0” was merged into a single port DLAT using the following command: set flatten model -latch_merge_port Circuit example: DLAT l0 (q,,1’b0,1’b0,ck,d0,sck,d1); Result : and u0 (n1,d0,ck); and u1 (n2,d1,sck); or u2 (din,n1,n2); or u3 (ck_or,ck,sck); DLAT l0 (q,,1’b0,1’b0,ck_or,din); Associated Commands SET FLATTEN MODEL -LATCH_MERGE_PORT

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849

Product Version 7.2


F27 Message Converted internal input port(s) to inout port(s)

Description Internal input ports were converted into inout ports because the input port does not drive any instances. Example Sample modeling message: F27: Converted internal input port(s) to inout port(s) (Occurrence: 1) 1: port /u0/y in module AN2 This message indicates that port “y” of module “AN2” does not drive any load. Circuit example: module AN2 (y,z,a,b); input a,b,y; output z; and buf

u0 (z,a,b); u1 (y,a);

endmodule module ckt (y,z,a,b); input a,b; output y,z; AN2 u0 (y,z,a,b); endmodule

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850

Product Version 7.2


F28 Message Converted internal output port(s) to inout port(s)

Description Internal output ports were converted to inout ports because the output port is not driven. Example Sample modeling message: F28: Converted internal output port(s) to inout port(s) (Occurrence: 1) 1: port /u0/a in module AN3 due to high-impedance (Z) gates This message indicates that port “a” of module “AN3” is not driven by any driver. Circuit example: module AN3 (z,a,b,c); input b,c; output z,a; and u0 (z,a,b,c); endmodule module ckt (z,a,b,c); input a,b,c; output z; AN3 u0 (z,a,b,c); endmodule

May 2008

851

Product Version 7.2


F30 Message Ignored weak device(s) due to the existence of strong device(s)

Description Any weak devices were ignored due to the existence of a stronger device in a multiple-driven net. Example Sample modeling message: F30: Ignored weak device(s) due to the existence of strong device(s) (Occurrence: 1) 1: n1 This message indicates that a weak device buffer “u0” driving net “n1” was ignored due to the existence of stronger buffer device “u1” driving the same net “n1”. Circuit example: buf (weak0,weak1)u0 (n1,a); buf u1 (n1,b); buf u2 (z,n1);

May 2008

852

Product Version 7.2


F32 Message Created Z gate(s) for floating net(s) and floating pin(s)

Description Z gates were created for floating nets and floating pins. Example Sample modeling message: F32: Created Z gate(s) for floating net(s) and floating pin(s) (Occurrence: 1) 1: c This message indicates that a net “c” of instance “u0” is not driven. Circuit example: module ckt (z,a,b); input a,b; output z; wire c; and u0 (z,a,b,c); endmodule

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853

Product Version 7.2


F34 Message Convert X assignment(s) as don’t care(s)

Description X assignments were converted to “don’t cares”. This operation is enabled when you use the SET X CONVERSION command. Example Sample modeling message: F34: Convert X assignment(s) as don’t care(s) (Occurrence: 1) 1: Converted ’X assignment’ at ’N$1’ be don’t care This message indicates that assignment in RTL code “default: z = 1’bx” is converted to don’t cares through the following command: set x conversion DC -golden Note: This option in the golden design is enabled by default. Circuit example: always @(a or b or begin case (sel) 2’b01 : z 2’b10 : z default : z endcase end

sel)

= a; = b; = 1’bx;

Associated Commands SET X CONVERSION

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Product Version 7.2


F34.1 Message Convert X assignment(s) as zero(s)

Description X assignments were converted to zero. This operation is enabled when you use the SET X CONVERSION command. Example Sample modeling message: F34.1: Convert X assignment(s) as zero(s) (Occurrence: 1) 1: Converted X assignment ’N$1’ as 0 This message indicates that X assignment in RTL code “default: z = 1’bx” was converted to logic ZERO using the following command: set x conversion 0 Circuit example: always @(a or begin case (sel) 2’b01 : 2’b10 : default : endcase end

b or sel)

z = a; z = b; z = 1’bx;


May 2008

855

Product Version 7.2


F34.2 Message Convert X assignment(s) as one(s)

Description X assignments were converted to one. This operation is enabled when you use the SET X CONVERSION command. Example Sample modeling message: F34.2: Convert X assignment(s) as one(s) (Occurrence: 1) 1: Converted X assignment ’N$1’ as 1 This message indicates that an X assignment in the RTL code “default: z = 1’bx” was converted to logic ONE using the following command: set x conversion 1 Circuit example: always @(a or b or begin case (sel) 2’b01 : z = 2’b10 : z = default : z = endcase end

sel)

a; b; 1’bx;


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856

Product Version 7.2


F34.3 Message Converted 1 X assignment(s) as E(s)

Description An X assignment was converted to an error (E) gate . This operation is enabled when you use the SET X CONVERSION command. If the X assignment space of the Revised design is within the X assignment space of the Golden design, then the E gate is marked as an extra unmapped point (redundant gate). Example Sample modeling message: F34.2: Convert 1 X assignment(s) as E (Occurrence: 1) 1: Converted X assignment ’N$1’ as E This message indicates that an X assignment in the RTL code “default: z = 1’bx” was converted to logic E using the following command: set x conversion E Circuit example: always @(a or b or begin case (sel) 2’b01 : z = 2’b10 : z = default : z = endcase end

sel)

a; b; 1’bx;


May 2008

857

Product Version 7.2


F36 Message Don’t care(s) added due to $constraint(s)

Description “don’t cares” were added due to $constraints. Example Sample modeling message: F36: Don’t care(s) added due to $constraint(s) (Occurrence: 1) 1: u0: DFF q_reg This message indicates that constraint “cstr_0” for register “q_reg” is added to don’t cares. Circuit example: always @(a or b or sel) begin case (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx; endcase end $constraint cstr_0 ($one_hot (sel)); always @(posedge ck) q <= z;

May 2008

858

Product Version 7.2


F39 Message Added output Z gate(s)

Description Output Z gates were added. This operation is enabled by SET FLATTEN MODEL -OUTPUT_Z, which is enabled by default. Example Sample modeling message: F39: Added output Z gate(s) (Occurrence: 1) 1: /z This message indicates that a Z gate was added at the output “z” using the following command: set flatten model -output_z Circuit example: module ckt (z,a,sel); input a,sel; output z; bufif0 u0 (z,a,sel); endmodule Associated Commands SET FLATTEN MODEL -OUTPUT_Z

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859

Product Version 7.2


F41 Message Converted set/reset loop(s) to data-hold(s)

Description The Conformal software converted a data-hold function that is modeled using an asynchronous set and an asynchronous reset functions, to a mux data-hold function Example Sample modeling message: F41: Converted set/reset loop(s) to data-hold(s) (Occurrence: 1) 1: DFF ’Q_reg’ Circuit example: assign RN = !Q & EN; assign SET = Q & EN; always @(posedge CK or posedge RN or posedge SET) begin if (RN) Q <= 1’b0; else if (SET) Q <= 1’b1; else Q <= D; end

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Product Version 7.2


F42 Message Unfolded DFF to latches

Description A DFF was unfolded into two DLATs. This operation is enabled when you use the REMODEL -UNFOLD_DFF command, which specifies that a DFF should be converted into two DLATs that are in a master-slave configuration. Example Sample modeling message: F42: Unfolded DFF to latches (Occurrence: 1) 1: /q_reg This message indicates you converted a single DFF into a master-slave DLATs using the following command: remodel -unfold_dff Circuit example: always @(posedge ck) q <= d; Associated Commands REMODEL -UNFOLD_DFF

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861

Product Version 7.2


F43 Message Added DLATs to cut loops

Description DLATs were added to cut combination loops.This operation is enabled by the SET FLATTEN MODEL command. Example Sample modeling message: F43: Added DLATs to cut loops (Occurrence: 1) 1: /u0 This message indicates that a DLAT was added at instance driver “u0” to cut the combinational loop using the following command: set flatten model -loop_as_dlat Circuit example: mux u0 (n1,n1,d,ck); xor u1 (q,n1); Associated Commands SET FLATTEN MODEL

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Product Version 7.2


5 Tcl Command Entry Mode Support Tcl Design Access Commands ■

find on page 865

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get_compare_points on page 866

■

get_compare_result on page 866

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get_exit_code on page 867

■

get_current_module on page 868

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get_fanins on page 868

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get_fanouts on page 868

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get_gate_count on page 868

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get_gate_id on page 868

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get_gate_type on page 868

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get_handle_type on page 869

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get_instances on page 869

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get_keypoint on page 870

■

get_map_points on page 871

■

get_module_definition on page 871

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get_names on page 872

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get_nets on page 872

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get_parent on page 873

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get_pins on page 874

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get_ports on page 875

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Encounter Conformal Equivalence Checking Reference Manual Tcl Command Entry Mode Support ■

get_primitive_type on page 876

■

get_property on page 877

■

get_root_module on page 878

■

get_unmap_points on page 878

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set_current_module on page 879

Tcl Utility Commands ■

echo_result on page 879

■

get_license_mode on page 879

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get_version_info on page 879

■

help on page 880

■

objtype on page 880

■

usage on page 880

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Encounter Conformal Equivalence Checking Reference Manual Tcl Command Entry Mode Support

find find <-Module | -Instance | -Port [-Input | -Output | -Bidir] | -Pin [ -Input | -Output| -Bidir] | -Net | -Gate | -Id> [-Golden | -Revised | -Both] [-Single]

Returns a design database object handle or list of handles for a design object or list of objects. -Module

The specified object_name is a module name.

-Instance

The specified object_name is an instance name.

-Port

The specified object_name is a port name. -Input specifies an input port. -Output specifies an output port. -Bidir specifies a bidirectional port.

-Pin

The specified object_name is a pin name. -Input specifies an input pin. -Output specifies an output pin. -Bidir specifies a bidirectional pin.

-Net

The specified object_name is a net name.

-Gate

Specifies a flattened gate name.

-Id

Specifies the ID of a flattened gate. Note: Conformal automatically assigns ID numbers. They can differ from one version to another. Always use ID numbers assigned by the Conformal version you are currently running.

-Golden

Applies to the Golden design only.

-Revised

Applies to the Revised design only.

-Both

Applies to the Golden and Revised designs.

-Single

Returns none or the first found object handle instead of a list.

This is the name of a specified design object. It is a name in module context or hierarchical context. Note: Hierarchical objects start with “/”.

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Example The following example shows how the return value of the command can be saved to a variable for later reference: set abc1 set abc2 … get_nets get_nets

[find -instance /u1/U2] [find -single -instance /u1/U2] [lindex $abc1 0] $abc2

get_compare_points get_compare_points [key_point_types] [result_types] [sort_type] [-count]

Queries for multiple objects and returns a list of compare point object handles or a count of the selected compare points. A compare point handle is a MAP_POINT object handle. key_point_types

Specifies the key point type(s), which can be one or more of -PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types

Specifies the result type(s), which can be one or more of -POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.

sort_type

Specifies the sort type, which can be either -Size or -Support.

-count

Returns a count of the selected compare points rather than a list of compare point handles.

get_compare_result get_compare_result

Returns compare results for the specified compare point. The key point is an object handle of the COMPARE_POINT type. The returned result is POS_EQ, NEG_EQ, DIFF, NOT_COMPARED, or ABORT.

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get_exit_code get_exit_code

Returns the run status without exiting the Conformal software. The status codes are: Bit

Condition

0

Internal Error

1

Status before comparison

2

Command error

3

Unmapped points or extra POs

4

Non-equivalent points during comparison

5

Abort or uncompared points exist during any comparisons.

6

Abort or uncompared points exist during the last comparision or hierarchical comparison.

Note: For bits 0, and 2 through 5, once they are set to 1, they will remain at 1. For bit 1, once it is set to 0, it will remain at 0.

Examples ■

Case 1: Start Conformal and then exit immediately Status = 2 (00010 in binary). There are no equivalent points since there was no comparison. Thus, bit 1 is set.

■

Case 2: Comparison produced a non-equivalent point, an abort point, and an equivalent point. Status = 48 (110000 in binary). Bits 4 and 5 are set to flag the abort and non-equivalent points.

■

Case 3: Comparison produced all non-equivalent points. Status = 18 (010010 in binary). Bits 1 and 4 are set to show two conditions: During this session, Conformal found no equivalent points and the comparison produced non-equivalent points.

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get_current_module get_current_module

Returns the MODULE handle for the current module.

get_fanins get_fanins

Queries for multiple objects and returns a list of fan-in gate handles for the specified gate object handle. The type of object handle is a FLAT_GATE.

get_fanouts get_fanouts

Queries for multiple objects and returns a list of fan-out gate handles for the specified gate object handle. The type of object handle is a FLAT_GATE. The syntax is as follows:

get_gate_count get_gate_count [-golden |-revised]

Returns the gate count for the specified design. The default design is Golden.

get_gate_id get_gate_id

Returns the gate id for the specified flattened gate object handle. Note: The Conformal software automatically assigns ID numbers. They can differ from one version to another. Always use ID numbers assigned by the software version you are running.

get_gate_type get_gate_type

Returns the gate type of the specified obj_handle. The type of object handle is FLAT_GATE. May 2008

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get_handle_type get_handle_type

Returns the object type of the specified object handle. The returned result is one of the following strings: ■

MODULE

■

MODULE_INSTANCE

■

MODULE_PORT

■

MODULE_INSTANCE_PIN

■

MODULE_NET

■

HIERARCHY_INSTANCE

■

HIERARCHY_PORT

■

HIERARCHY_INSTANCE_PIN

■

HIERARCHY_NET

■

FLAT_GATE

■

MAP_POINT

get_instances get_instances [-all_hierarchy]

Queries for multiple objects and returns a list of instances associated with the specified object handle. -all_hierarchy

May 2008

Use this argument in combination with the HIERARCHY_NET object handle type. It returns a list of hierarchical instance object handles that are associated with the given hierarchical net object.

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The specified obj_handle as one of the following types: ■

MODULE: lists the instances in the module

■

MODULE_INSTANCE: lists the instance that identifies itself

■

MODULE_PORT: not applicable

■

MODULE_INSTANCE_PIN: lists the instances whose pins are listed in the specified object handle

■

MODULE_NET: lists the instances that connect with the net

■

HIERARCHY_INSTANCE: lists the hierarchical instance that identifies itself

■

HIERARCHY_PORT: lists the hierarchical instance of which pins include this pin

■

HIERARCHY_INSTANCE_PIN: lists the hierarchical instance of which pins include this pin

■

HIERARCHY_NET: lists the hierarchical instances that connect with the net in a hierarchical context

■

FLAT_GATE: lists the hierarchical instance that represents the flattened gate

■

MAP POINT: not applicable

get_keypoint get_keypoint [-golden | -revised]

Returns the key point (FLAT_GATE type) of a specified compare point. The object handle will be a MAP_POINT type.

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get_map_points get_map_points [key_point_types] [result_types] [sort_type] [-count]

Queries for multiple objects and returns a list of map point object handles or a count of the selected map points. A map point handle is a MAP_POINT object handle. key_point_types

Specifies the key point type(s), which can be one or more of -PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types

Specifies the result type(s), which can be one or more of -POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.

sort_type


-count

Returns a count of the selected map points rather than a list of map point handles.

get_module_definition get_module_definition

Returns a module definition for the specified object handle, where is one of the following types: ■

MODULE: define itself

■

MODULE_INSTANCE: define the module of the specified instance

■

MODULE_PORT: not applicable

■

MODULE_INSTANCE_PIN: not applicable

■

MODULE_NET: not applicable

■

HIERARCHY_INSTANCE: define the module of the specified instance in a hierarchical context.

■

HIERARCHY_PORT: not applicable

■

HIERARCHY_INSTANCE_PIN: not applicable

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HIERARCHY_NET: not applicable

■

FLAT_GATE: define the module of the specified flattened gate

■


get_names get_names

Queries for multiple objects and returns a name or list of names for the specified object handles.

get_nets get_nets [-all_hierarchy]

Queries for multiple objects and returns a list of nets for the specified object handle. -all_hierarchy

May 2008

Use this argument in combination with the HIERARCHY object handle type. It returns a list of hierarchical net object handles that are associated with the given hierarchical design object (for example, HIERARCHY_INSTANCE).

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MODULE: lists the nets of the specified module

■

MODULE_INSTANCE: lists the nets that connect with the specified instance

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MODULE_PORT: lists the nets that connect with the specified port

■

MODULE_INSTANCE_PIN: lists the nets that connect with the specified pin

■

MODULE_NET: lists the net that identifies itself

■

HIERARCHY_INSTANCE: lists the nets that connect with the specified instance in a hierarchical context

■

HIERARCHY_PORT: lists the nets that connect with the specified port in a hierarchical context

■

HIERARCHY_INSTANCE_PIN: lists the nets that connect with the specified pin in a hierarchical context

■

HIERARCHY_NET: lists the net that identifies itself

■

FLAT_GATE: lists the nets that connect with the specified flattened gate in a hierarchical context

■


get_parent get_parent

Returns a handle to the parent of the specified object handle, where is one of the following types: ■

MODULE: not applicable

■

MODULE_INSTANCE: return the module that contains the specified instance

■

MODULE_PORT: return the module that contains the specified port

■

MODULE_INSTANCE_PIN: return the module that contains the specified pin

■

MODULE_NET: return the module that contains the specified net

May 2008

873

Product Version 7.2


HIERARCHY_INSTANCE: return the module definition of the instance

■

HIERARCHY_PORT: return the hierarchical instance that contains the specified port in a hierarchical context

■

HIERARCHY_INSTANCE_PIN: return the hierarchical instance that contains the specified pin in a hierarchical context

■

HIERARCHY_NET: return the hierarchical instance that contains the specified net in a hierarchical context

■

FLAT_GATE: return the hierarchical instance that contains the specified flattened gate in a hierarchical context

■


get_pins get_pins [-all_hierarchy]

Queries for multiple objects and returns a list of pins associated with the specified object handle. -all_hierarchy

May 2008

Use this argument in combination with the HIERARCHY_NET object handle type. It returns a list of hierarchical instance pin object handles that are associated with the given hierarchical net object.

874

Product Version 7.2



MODULE: lists the pins of the specified module

■

MODULE_INSTANCE: lists the pins of the specified instance

■

MODULE_PORT: lists the pins that connect with the net of the specified port

■

MODULE_INSTANCE_PIN: lists the pin that identifies itself

■

MODULE_NET: lists the pins that connect with the specified net

■

HIERARCHY_INSTANCE: lists the pins of the specified instance in a hierarchical context

■

HIERARCHY_PORT: lists the pins that connect with the net of the specified port in a hierarchical context

■

HIERARCHY_INSTANCE_PIN: lists the nets that connect with the specified pin in a hierarchical context

■

HIERARCHY_NET: lists the pin that identifies itself

■

FLAT_GATE: lists the pins of the specified flattened gate in a hierarchical context

■


get_ports get_ports [-all_hierarchy]

Queries for multiple objects and returns a list of ports associated with the specified object handle. -all_hierarchy

May 2008

Use this argument in combination with the HIERARCHY_NET object handle type. It returns a list of hierarchical port object handles that are associated with the given hierarchical net object.

875

Product Version 7.2



MODULE: lists the ports of the specified module

■

MODULE_INSTANCE: lists the ports of the specified instance

■

MODULE_PORT: lists the port that identifies itself

■

MODULE_INSTANCE_PIN: returns the relative port of the specified pin

■

MODULE_NET: lists the ports that connect with the specified net

■

HIERARCHY_INSTANCE: lists the ports of the specified instance in a hierarchical context

■

HIERARCHY_PORT: lists the port that identifies itself

■

HIERARCHY_INSTANCE_PIN: returns the relative port of the specified pin in a hierarchical context

■

HIERARCHY_NET: lists the ports that connect with the specified net in a hierarchical context

■

FLAT_GATE: lists the ports of the specified flattened gate

■


get_primitive_type get_primitive_type

Returns the primitive type for the specified instance object handle, where is one of the following: ■

MODULE_INSTANCE

■

HIERARCHY_INSTANCE

■

FLAT_GATE

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Product Version 7.2


get_property get_property

Returns the property of the specified object handle. The following lists the object handle one of the following types, with their property types and return values. ■

MODULE Property Type: BlackBox; Return Value: YES, NO Property Type: InLib; Return Value: YES, NO Include the InLib property to test whether the module definition is defined in the library space (YES) or design space (NO)—that is, it tests whether the module definition is imported by the READ LIBRARY or READ DESIGN command.

■

MODULE_INSTANCE Property Type: Primitive; Return Value: YES, NO Property Type: CutPoint; Return Value: YES, NO Include the CutPoint property to test whether the module definition is a cut point—that is, it tests whether you have run the ADD CUT POINT command on this module definition.

■

MODULE_PORT Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR

■

MODULE_INSTANCE_PIN Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR

■

MODULE_NET Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1, TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE Note: GLOBAL applies to those signals that cross multiple modules (for example, assertions).

■

HIERARCHY_INSTANCE Property Type: BlackBox; Return Value: YES, NO

■

HIERARCHY_PORT Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR

May 2008

877

Product Version 7.2


HIERARCHY_INSTANCE_PIN Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR

■

HIERARCHY_NET Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1, TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE Note: GLOBAL applies to those signals that cross multiple modules (for example, assertions).

■

FLAT_GATE Property Type: BlackBox; Return Value: YES, NO Property Type: Golden; Return Value: YES, NO Property Type: Revised; Return Value: YES, NO

■

MAP POINT: not applicable Property Type: Result; Return Value: POS_EQ, NEG_EQ, DIFF, ABORT, UNKNOWN

get_root_module get_root_module [-golden | -revised]

Returns the name of the root module for the specified design. The default design is Golden.

get_unmap_points get_unmap_points [key_point_types] [result_types] [sort_type] [-count]

Queries for multiple objects and returns a list of unmap point object handles or a count of the selected unmap points. An unmap point handle is a MAP_POINT object handle. key_point_types

Specifies the key point type(s), which can be one or more of -PI, -PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types

Specifies the result type(s), which can be one or more of -Extra, -UNReachable, or -NOTmapped.

sort_type


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Product Version 7.2


-count

Returns a count of the selected unmap points rather than a list of unmap point handles.

set_current_module set_current_module <[which_design] module_name | obj_handle>

Changes the current module. By default, the current module is the root module. which_design

Includes one or more of the following options. Note: which_design is ignored if you use . -golden sets the current module for the Golden design. This option is the default value. -revised sets the current module for the Revised design.

The specified name is a module name.

This argument is a MODULE handle.

echo_result echo_result [-on | -off]

Turns the command result printing on or off.

get_license_mode get_license_mode

Returns the current license mode. For example, custom, ultra, asic, lp, rcv, verify, and ccd.

get_version_info get_version_info

Returns a TCL list of the version related info, including version_num, build_date, 32 or 64 bit, host name, and platform.

May 2008

879

Product Version 7.2


help help [command_name]

Returns the command usage of the specified command or a list of all Conformal Tcl commands if you do not specify a command.

objtype objtype

Returns the type of an native TCL object, for example string and list, or Conformal design object handle type (i.e. vpxhandle).

usage usage [-CPU | -MEM]

Displays usage values in Tcl scripts for total CPU run time and peak memory use.

May 2008

880

Product Version 7.2


individual messages

Index

526

O online help Tcl commands 27

Numerics 3-2-1 rule

R

26

reports, examples of environment 300

A -all option 30

S

B

shorthand, for command entry SPICE HDL rules 720 syntax rules 26 System Verilog HDL rules 733

-both option 31

C case sensitivity in command syntax 26 commands shorthand for entry 26 conventions for syntax 30

U UNIX commands, using in Conformal with exclamation (!) point 30 with system command 30 usage, command syntax help (Tcl) 27

D directives rule check numbers and messages

26

522

H HELP command 27 hierarchical design, naming rules report 300

M MAN command 27 man directory 27 messages generated by HDL (RTL) rule check, see

May 2008

881

Product Version 7.2


May 2008

882

Product Version 7.2

Conformal Ref

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