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O00CSE 3666 Homework 2 1.) Page 164, Exercise 2.1 (5 points) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS assembly instructions. f = g + (h − 5);
sub $t0, $s1, $s2 add $s0, $s3, $t0
2.) Page 165, Exercise 2.3 (10 points) For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. B[8] = A[i−j]; sub
$t0, $s3, $s4
# t0 = i-j
sll
$t0, $t0, 2
# t0 = (i-j)*4
lw
$t1, 0($s6)
# t1 = A[0]
add
$t1, $t1, $t0
# $t1 = &A[i-j]
lw
$t1, 0($t1)
# $t1 = A[i-j]
sw
$t1, 32($s7)
# B[8] = A[i-j]
3.) Page 165, Exercise 2.4 (10 points) For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. sll
$t0, $s0, 2
add sll add lw addi lw add sw
$t0, $t1, $t1, $s0, $t2, $t0, $t0, $t0,
$s6, $t0 $s1, 2 $s7, $t1 0($t0) $t0, 4 0($t2) $t0, $s0 0($t1)
# $t0 = f * 4 # $t0 = &A[f] # $t1 = g * 4 # $t1 = &B[g] # $s0 = A[f] #$t2 = &A[f+1] #$t0 = A[f+1] #$t0 = A[f] + A[f+1] #B[g] = A[f] + A[f+1]
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B[g] = A[f] + A[f+1]
4.) Page 166, Exercise 2.7 (5 points) Show how the value 0xabcdef12 would be arranged in memory of a little-endian and a big-endian machine. Assume the data is stored starting at address 0. Little-edian: Address
Data
12
ab
8
cd
4
ef
0
12
Big-edian: Address
Data
12
12
8
ef
4
cd
0
ab
5.) Page 166, Exercise 2.8 (5 points) Translate 0xabcdef12 into decimal. 0xabcdef12 = 10*167 + 11*166 + 12*165 + 13*164 + 14*163 + 15*162 + 1*161 + 2*160 =
6.) Page 166, Exercise 2.9 (10 points) Note: C code is: f = A[ B[g] + 1 ] Translate the following C code to MIPS. Assume that the variables f, g, h, i, and j are
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assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: B[8] = A[i] + A[j]; sll add lw sll add lw add sw
$t0, $t0, $t0, $t1, $t1, $t1, $t2, $t2,
$s3, 2 $t0, $s6 0($t0) $s4, 2 $t1, $s6 0($t1) $t0, $t1 32($s7)
# # # # # # # #
i*4 $t0 = &A[i] $t0 = A[i] j*4 $t0 = &A[j] $t1 = A[j] $t2 = A[i] + A[j] B[8] = A[i] + A[j]
7.) Page 167, Exercise 2.12 (20 points) Assume that registers $s0 and $s1 hold the values 0x80000000 and 0xD0000000, respectively. 2.12.1 [5]<§2.4> What is the value of $t0 for the following assembly code? add $t0, $s0, $s1 $s0 = 0x80000000 = 1000 0000 0000 0000 0000 0000 0000 0000 $s1 = 0 xD0000000 = 1101 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 + 1101 0000 0000 0000 0000 0000 0000 0000 10101 0000 0000 0000 0000 0000 0000 0000 = 150000000 hex
An overflow occurs because the result is greater than 32 bits so the value of $t0 is 50000000.
2.12.2 [5]<§2.4>Is the result in $t0 the desired result, or has there been overflow?
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There has been an overflow.
2.12.3 [5] <§2.4> For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 for the following assembly code? sub $t0, $s0, $s1 $s0 = 0x80000000 = 1000 0000 0000 0000 0000 0000 0000 0000 $s1 = 0 xD0000000 = 1101 0000 0000 0000 0000 0000 0000 0000
invert $s1 => 0010 1111 1111 1111 1111 1111 1111 1111 add 1 => 0011 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 + 0011 0000 0000 0000 0000 0000 0000 0000
1011 0000 0000 0000 0000 0000 0000 0000 = 0xB0000000 2.12.4 [5]<§2.4>Is the result in $t0 the desired result, or has there been overflow? The value of $t0 is the desired result. No overflow has occurred. 2.12.5 [5] <§2.4> For the contents of registers $s0 and $s1 as specified above, what is the value of $t0 for the following assembly code? add $t0, $s0, $s1 add $t0, $t0, $s0 $s0 = 0x80000000 = 1000 0000 0000 0000 0000 0000 0000 0000 $s1 = 0 xD0000000 = 1101 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 + 1101 0000 0000 0000 0000 0000 0000 0000 10101 0000 0000 0000 0000 0000 0000 0000 = 150000000 hex $s0 = 1000 0000 0000 0000 0000 0000 0000 0000 $t0 = 10101 0000 0000 0000 0000 0000 0000 0000 10101 0000 0000 0000 0000 0000 0000 0000
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+ 1000 0000 0000 0000 0000 0000 0000 0000 $t0 = 1 1101 0000 0000 0000 0000 0000 0000 0000 =
An overflow occurs because the result is greater than 32 bits so the value of $t0 is D0000000hex
2.12.6 [5] <§2.4> Is the result in $t0 the desired result, or has there been overflow? There has been overflow
8.) Page 167, Exercise 2.14 (5 points) Provide the type and assembly language instruction for the following binary value: 0000 0010 0001 0000 1000 0000 0010 0000two R-type instruction
Opcode(6 bits)
RS(5 bits)
RD(5 bits)
RT(5 bits)
Shamt(5 bits)
Funct(6 bits)
0000000
10000
10000
10000
00000
100000
This describes add instruction of assembly language. For the values in the registers as above, the instruction is add $s0, $s0, $s0. 9.) Page 167, Exercise 2.15 (5 points) Provide the type and hexadecimal representation of following instruction: sw $t1, 32($t2)
sw Opcode = 43 = 101011 immediate address = 32 = 0000000000100000 This instruction is I-type. $t1 = 9 = 01001 $t2 = 10 = 01001
Binary
Opcode
RS
RT
Immediate address
101011
01010
01001
0000000000100000
Binary representation: 1010 1101 0100 1001 0000 0000 0010 0000two
10.)
Page 168, Exercise 2.16 (5 points)
Provide the type, assembly language instruction, and binary
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representation of instruction described by the following MIPS elds: op=0, rs=3, rt=2, rd=3, shamt=0, funct=34 rs = 3 => $v1 rt = 2 => $v0 rd = 3 => $v1 funct = 34 => sub sub $v1, $v1, $v0 R-Type instruction
Opcode(6 bits)
RS(5 bits)
RD(5 bits)
RT(5 bits)
Shamt(5 bits)
Funct(6 bits)
0000000
00011
00010
00011
00000
100010
Binary = 0000 0000 0110 0010 0001 1000 0010 0010two 11.)
Page 168, Exercise 2.17 (5 points)
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS elds: op=0x23, rs=1, rt=2, const=0x4 lw $v0, 4($at)
I-Type Instruction
Binary
12.)
Opcode
RS
RT
Constant
100011
00001
00010
000100
Page 168, Exercise 2.18 (15 points)
Assume that we would like to expand the MIPS register le to 128 registers and expand the instruction set to contain four times as many instructions. 2.18.1 [5] <§2.5> How this would this affect the size of each of the bit fields in the R-type instructions? Log2(128) = 7 Opcode
RS
RD
RT
Shamt
Funct
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6 bits
7 bits
7 bits
7 bits
5 bits
6 bits
2.18.2 [5] <§2.5> How this would this affect the size of each of the bit fields in the I-type instructions? Opcode
RS
RT
Immediate
6 bits
7 bits
7 bits
16 bits
2.18.3 [5] <§§2.5, 2.10> How could each of the two proposed changes decrease the size of an MIPS assembly program? On the other hand, how could the proposed change increase the size of an MIPS assembly program? It would decrease the size of a MIPS assembly program since there are more registers, it means they can hold more information so it would make less calls to l w and sw. The increase in registers would mean more bits are required to represent the registers in the instructions and that would increase the size of a MIPS assembly program.
