Design and Implementation of a Fast Unsigned 32-bit Multiplier Using VHDL Hasan Krad* and Aws Yousif** * Qatar University/Department of Computer Science & Engineering, Doha, Qatar. Email:
[email protected] ** Qatar University/Department of Computer Science & Engineering, Doha, Qatar. Email:
[email protected]
classified binary adder architectures. They compared the ripple adder, carry-look-ahead adder, carry select adder and the conditional sum adder. They used VHDL implementation for their designs and comparison studies. Their work included the unit-gate models for area and delay [4]. Asadi and Navi developed a new 54×54 bit multiplier using a high-speed carry-look-ahead adder. Their proposed multiplier reduced the number of transistors, delay and power consumption [1].
Abstract― This paper presents a Very high speed integrated circuit – Hardware Description Language (VHDL) based design and implementation of a fast unsigned multiplier. The multiplier uses a carry lookahead adder, which reduces the delay time caused by the effect of carry propagation through all the stages of a ripple-carry adder. The paper’s main focus is on the speed and complexity of the multiplier and it also provides a performance comparison between the fast multiplier and a ripple-carry adder based multiplier. The multiplier multiplies 32-bit values. Under the worst case, where the gate delay is assumed to be 5 ns, the ripplecarry adder based multiplier uses 979.056 ns to complete the operation, while the fast multiplier uses only 659.292 ns. This 26.93% speed improvement was possible with the use of the carry look-ahead adder. However, the carry look-ahead adder requires extra logic circuit to generate the carry, which can reasonably justified by the relatively cheap cost of the contemporary hardware. The VHDL– based model of the fast multiplier was developed using the DirectVHDL simulator software.
II. CARRY LOOK-AHEAD ADDER To reduce the delay caused by the effect of carry propagation in the ripple carry adder, we attempt to evaluate the carry-out for each stage (same as carry-in to next stage) concurrently with the computation of the sum bit [5, 6]. The two Boolean functions for the sum and carry are as follows [7, 8]:
Key Words― Carry Look-Ahead Adder; Multiplier; VHDL Modeling & Simulation
I.
SUM = Ai ⊕ Bi ⊕ Ci Cout = Ci+1 = Ai · Bi + (Ai ⊕ Bi) · Ci
INTRODUCTION
Let Gi = Ai · Bi be the carry generate function and Pi = (Ai ⊕ Bi) be the carry propagate function, Then we can rewrite the carry function as follows:
The multiplier is a vital module of a computer system and can be considered one of the fundamental arithmetic functions. However, multiplication is not as a simple operation as addition or subtraction, because it takes more time to perform two subtasks, addition and shifting. Typically, a multiplication operation takes between 2 and 8 cycles [1]. Therefore, using high-speed multipliers is a critical requirement for high performance processors. Multipliers use the addition operation for all the partial products. The adder can be a ripple-carry adder, a carry lookahead adder, or any other adder [2, 3]. However, using a fast adder to complete the multiplication operation improves the overall performance of the computer system. Our study is focused on multipliers using unsigned data. VHDL, a Very high speed integrated circuit Hardware Description Language, was used to model and simulate the multiplier design.
Ci+1 = Gi + Pi · Ci Thus, for 4-bit adder, we can compute the carry for all the stages as shown below: C1 = G0 + P0 · C0 C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0 C3 = G2 + P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0 C4 = G3 + P3 · G2 + P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0 In general, we can write: The sum function: SUMi = Ai ⊕ Bi ⊕ Ci = Pi ⊕ Ci The carry function:
Several researchers had addressed the adder performance issues and others did the same with regard to the multiplier performance. Sertbas and Özbey worked on the performance analysis of
i
i
i
j= 0
k = j +1
k =0
Ci +1 = ∑ (G j ∏ Pk ) + ∏ Pk Cin
1
We modeled the look-ahead adder for our design with the following VHDL code:
Different gate-level architectures have a substantial impact on hardware size, layout complexity, speed and power, for basic adder types (ripple, lookahead, skip). For example, ripple adders are slower but use the least energy, whereas speculative styles such as bypass adders are fast but consume much more power, since they perform computations they later discard [9]. III. MULTIPLIER FOR UNSIGNED DATA Multiplication involves the generation of partial products, one for each digit in the multiplier, as in Fig.1. These partial products are then summed to produce the final product. The multiplication of two n-bit binary integers results in a product of up to 2n bits in length [2].
We modeled the carry ripple adder for our design with the following VHDL code:
Figure. 1. A partial schematic of the multiplier We used the following algorithm to implement the multiplication operation for unsigned data: IV. MULTIPLICATION ALGORITHM Let the product register size be 64 bits. Let the multiplicand registers size be 32 bits. Store the multiplier in the least significant half of the product register. Clear the most significant half of the product register. Repeat the following steps for 32 times: 1. If the least significant bit of the product register is “1” then add the multiplicand to the most significant half of the product register. 2. Shift the content of the product register one bit to the right (ignore the shifted-out bit.)
Carry Look Ahead Adder can produce carries faster due to parallel generation of the carry bits by using additional circuitry. This technique uses carry bypass logic to speed up the carry propagation [4, 5].
2
3.
Shift-in the carry bit into the most significant bit of the product register.
As we increase the number of bits in the carry look-ahead adders, the complexity increases because the number of gates in the expression Ci+1 increases [5], as shown in the following expression:
Fig. 2 shows a block diagram for such a multiplier [2].
i
i
i
j= 0
k = j +1
k =0
Ci +1 = ∑ (G j ∏ Pk ) + ∏ Pk Cin
The multiplier with ripple carry adder had a smaller area while the multiplier with the carry look ahead adders had a larger area [5], due to the extra logic gates needed for the look-ahead network. VI. CONCLUSION A design and implementation of a VHDL-based 32-bit unsigned fast multiplier was presented. VHDL, a Very High Speed Integrated Circuit Hardware Description Language, was used to model and simulate our multiplier. Using a fast adder improves the overall performance of the multiplier. The ripple-carry adder based multiplier uses 979.056 ns to complete the multiplication operation, while the carry look-ahead adder based multiplier uses only 659.292 ns. A 26.93% speed improvement was possible with the use of the carry look-ahead adder. However, the extra complexity of the carry look-ahead adder required to generate the carry can be reasonably justified by the relatively cheap cost of the contemporary hardware.
Figure 2. Multiplier of two n-bit values. V. VHDL SIMULATION The VHDL simulation of the two multipliers is presented in this section. The VHDL code for both multipliers, using a fast carry look-ahead adder and a ripple carry adder, are generated. The VHDL model has been developed using DirectVHDL simulator [10]. The multipliers use 32-bit values. The worst case was applied to the two multipliers, where the gate delay is assumed to be 5 ns. The worst case is a 32-bit string of binary 1.
REFERENCES 1.
Figure 3. Command line.
2.
3. Figure 4. Waveform for a carry ripple adder
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5.
Figure 5. Waveform for a carry look-ahead adder Under the worst case, the multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carry look-ahead adder uses time = 659.292 ns. While the two multipliers showed the same time by using a string of 32-bit of binary 0. The results in both cases uses time = 118.024 ns, because of the least significant bit in the multiplicand are all showing binary 0.
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P. Asadi and K. Navi, “A novel highs-speed 54-54 bit multiplier”, Am. J. Applied Sci., vol. 4 (9), pp. 666-672. 2007. http://www.scipub.org/fulltext/ajas/ajas49666672.pdf. W. Stallings, Computer Organization and Architecture Designing for Performance, 7th ed., Prentice Hall, Pearson Education International, USA, 2006, ISBN: 0-13-1856448. J. F. Wakerly, Digital Design-Principles and Practices, 4th ed., Pearson Prentice Hall, USA, 2006. ISBN: 0131733494. A. Sertbas and R.S. Özbey, “A performance analysis of classified binary adder architectures and the VHDL simulations”, J. Elect. Electron. Eng., Istanbul, Turkey, vol. 4, pp. 1025-1030, 2004. http://www.istanbul.edu.tr/eng/ee/jeee/main/pa ges/issues/is41/41005.pdf . P. S. Mohanty, “Design and Implementation of Faster and Low Power Multipliers”, Bachelor Thesis. National Institute of Technology, Rourkela, 2009. http://ethesis.nitrkl.ac.in/213/1/10509019_final .pdf.pdf. S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd ed., McGraw-Hill Higher Education, USA, 2005. ISBN: 0072499389.
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J. R. Armstrong and F.G. Gray, VHDL Design Representation and Synthesis, 2nd ed., Prentice Hall, USA, 2000. ISBN: 0-13-021670-4. Z. Navabi, VHDL Modular Design and Synthesis of Cores and Systems, 3rd ed., McGraw-Hill Professional, USA, 2007. ISBN: 9780071508926. P. C. H. Meier, R. A. Rutenbar and L. R. Carley, “Exploring Multiplier Architecture and
Layout for low Power”, CIC’96, 1996. http://www.ece.cmu.edu/~lowpower/cicc96.pd f 10. Software Simulation Package: DrirectVHDL, Version 1.2, 2007, Green Mounting Computing Systems, Inc., Essex, VT, UK. http://www.gmvhdl.com
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