Digital-Electronics-sample-chapter.pdf

Eighth Edition

GATE ELECTRONICS & COMMUNICATION

Digital Electronics Vol 6 of 10

R. K. Kanodia Ashish Murolia

NODIA & COMPANY

GATE Electronics & Communication Vol 6, 8e Digital Electronics RK Kanodia & Ashish Murolia

Copyright © By NODIA & COMPANY

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To Our Parents

Preface to the Series For almost a decade, we have been receiving tremendous responses from GATE aspirants for our earlier books: GATE Multiple Choice Questions, GATE Guide, and the GATE Cloud series. Our first book, GATE Multiple Choice Questions (MCQ), was a compilation of objective questions and solutions for all subjects of GATE Electronics & Communication Engineering in one book. The idea behind the book was that Gate aspirants who had just completed or about to finish their last semester to achieve his or her B.E/B.Tech need only to practice answering questions to crack GATE. The solutions in the book were presented in such a manner that a student needs to know fundamental concepts to understand them. We assumed that students have learned enough of the fundamentals by his or her graduation. The book was a great success, but still there were a large ratio of aspirants who needed more preparatory materials beyond just problems and solutions. This large ratio mainly included average students. Later, we perceived that many aspirants couldn’t develop a good problem solving approach in their B.E/B. Tech. Some of them lacked the fundamentals of a subject and had difficulty understanding simple solutions. Now, we have an idea to enhance our content and present two separate books for each subject: one for theory, which contains brief theory, problem solving methods, fundamental concepts, and points-to-remember. The second book is about problems, including a vast collection of problems with descriptive and step-by-step solutions that can be understood by an average student. This was the origin of GATE Guide (the theory book) and GATE Cloud (the problem bank) series: two books for each subject. GATE Guide and GATE Cloud were published in three subjects only. Thereafter we received an immense number of emails from our readers looking for a complete study package for all subjects and a book that combines both GATE Guide and GATE Cloud. This encouraged us to present GATE Study Package (a set of 10 books: one for each subject) for GATE Electronic and Communication Engineering. Each book in this package is adequate for the purpose of qualifying GATE for an average student. Each book contains brief theory, fundamental concepts, problem solving methodology, summary of formulae, and a solved question bank. The question bank has three exercises for each chapter: 1) Theoretical MCQs, 2) Numerical MCQs, and 3) Numerical Type Questions (based on the new GATE pattern). Solutions are presented in a descriptive and step-by-step manner, which are easy to understand for all aspirants. We believe that each book of GATE Study Package helps a student learn fundamental concepts and develop problem solving skills for a subject, which are key essentials to crack GATE. Although we have put a vigorous effort in preparing this book, some errors may have crept in. We shall appreciate and greatly acknowledge all constructive comments, criticisms, and suggestions from the users of this book. You may write to us at [email protected] and [email protected].

Acknowledgements We would like to express our sincere thanks to all the co-authors, editors, and reviewers for their efforts in making this project successful. We would also like to thank Team NODIA for providing professional support for this project through all phases of its development. At last, we express our gratitude to God and our Family for providing moral support and motivation. We wish you good luck ! R. K. Kanodia Ashish Murolia

SYLLABUS GATE Electronics & Communications Boolean algebra, minimization of Boolean functions; logic gates; digital IC families (DTL, TTL, ECL, MOS, CMOS). Combinatorial circuits: arithmetic circuits, code converters, multiplexers, decoders, PROMs and PLAs. Sequential circuits : latches and flip-flops, counters and shift-registers. Sample and hold circuits, ADCs, DACs. Semiconductor memories. Microprocessor(8085): architecture, programming, memory and I/O interfacing. IES Electronics & Telecommunication Transistor as a switching element ; Simplification of Boolean functions, Karnaguh map , Boolean algebra, and applications; IC logic families : DTL, ECL, TTL, NMOS, CMOS and PMOS gates and their comparison; Full adder , Half adder; IC Logic gates and their characteristics; Digital comparator; Multiplexer Demultiplexer; Flip flops. J-K, R-S, T and D flip-flops; Combinational logic Circuits; Different types of registers and counters Waveform generators. Semiconductor memories.A/D and D/A converters. ROM an their applications. **********

CONTENTS CHAP 1

NUMBER SYSTEM AND CODES

1.1

INTRODUCTION

1.2

ANALOG AND DIGITAL SYSTEMS

1

1.2.1 1.2.2

2 2

1.3

2

Decimal Number System 2 Binary Number System 3 Octal Number System 3 Hexadecimal Number System

NUMBER SYSTEM CONVERSION

1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.5

Advantages of Digital System Limitations of Digital System

NUMBER SYSTEMS

1.3.1 1.3.2 1.3.3 1.3.4 1.4

1

5

Decimal-to-Binary Conversion 5 Decimal-to-Octal Conversion 6 Decimal-to-Hexadecimal Conversion 7 Octal-to-Binary conversion 7 Binary-to-Octal Conversion 7 Hexadecimal-to-Binary Conversion 8 Binary-to-Hexadecimal Conversion 8 Hexadecimal-to-Octal and Octal-to-Hexadecimal Conversion 8

BASIC BINARY ARITHMETIC

9

1.5.1 1.5.2 1.5.3 1.5.4

9 9

Binary Binary Binary Binary

Addition 9 Subtraction Multiplication Division 9

1.6

COMPLEMENTS OF NUMBERS

1.7

NUMBER REPRESENTATION IN BINARY

1.7.1 1.7.2 1.7.3 1.8

1.9

10

Sign-Magnitude Representation 1’s Complement Representation 2’s Complement Representation

11

11 11 12

COMPLEMENT BINARY ARITHMETIC

13

1.8.1 1.8.2 1.8.3 1.8.4

13 13 14 15

Addition Using 1’s Complement Subtraction Using 1’s Complement Addition Using 2’s Complement Subtraction using 2’s Complement

HEXADECIMAL ARITHMETIC

1.9.1 1.9.2 1.10

4

15

Hexadecimal Arithmetic Using 1’s or 2’s Complements Hexadecimal Subtraction Using 15’s or 16’s Complement

OCTAL ARITHMETIC

16

1.10.1 Octal Arithmetic using 1’s or 2’s Complements 1.10.2 Octal Subtraction using 7’s or 8’s complement

16 16

15 15

1.11

DECIMAL ARITHMETIC

17

1.11.1 Decimal Arithmetic Using 1’s or 2’s Complements 17 1.11.2 Decimal Subtraction Using 9’s and 10’s Complement 1.12

BINARY CODES

1.13

BINARY CODED DECIMAL (BCD) CODE OR 8421 CODE

17

18 20

1.13.1 BCD-to-Binary Conversion 20 1.13.2 Binary-to-BCD Conversion 20 1.14

BCD ARITHMETIC 20

1.14.1 BCD Addition 1.14.2 BCD Subtraction

21 21

1.15

THE EXCESS-3 CODE

22

1.16

GRAY CODE

23

1.16.1 Binary-to-Gray Code Conversion 1.16.2 Gray-to-Binary Code Conversion 1.16.3 Applications of Gray Code EXERCISE 1.1

25

EXERCISE 1.2

31

EXERCISE 1.3

33

SOLUTIONS 1.1

41

SOLUTIONS 1.2

53

SOLUTIONS 1.3

58

23 24 24

CHAPTER 2 BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION 2.1

INTRODUCTION

2.2

BOOLEAN ALGEBRA

63

2.2.1 2.2.2

63 64

2.3

BASIC BOOLEAN OPERATIONS

2.3.1 2.3.2 2.3.3 2.4

2.5

Logic Levels Truth Table

63

64

Boolean Addition (Logical OR) Boolean Multiplication (Logical AND) Logical NOT 65

THEOREMS OF BOOLEAN ALGEBRA

66

2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.4.7 2.4.8 2.4.9 2.4.10 2.4.11 2.4.12 2.4.13

68

Complementation Laws 66 AND Laws 66 OR Laws 66 Commutative Laws 67 Associative Laws 67 Distributive Law 67 Redundant Literal Rule 67 Idempotent Law 67 Absorption Law 67 Consensus Theorem 67 Transposition Theorem 68 De Morgan’s Theorem 68 Shannon’s Expansion Theorem

64 65

SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA

2.5.1

Complement of Boolean Function

69

68

2.5.2 2.5.3 2.6

LOGIC GATES

2.6.1 2.6.2 2.7

Principal of Duality 69 Relation Between Complement and Dual 69

Logic Levels 70 Types of Logic Gates

UNIVERSAL GATE

2.7.1 2.7.2

70

75

NAND Gate as a Universal Gate NOR Gate as a Universal Gate

75 77

2.8

ALTERNATE LOGIC-GATE REPRESENTATIONS

2.9

BOOLEAN ANALYSIS OF LOGIC CIRCUITS

2.9.1 2.9.2 2.10

69

79 80

Converting Boolean Expressions to Logic Diagram Converting Logic to Boolean Expressions 81

80

CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC

2.10.1 NAND-NAND Logic 2.10.2 NOR-NOR Logic 83 EXERCISE 2.1

84

EXERCISE 2.2

105

EXERCISE 2.3

107

SOLUTIONS 2.1

117

SOLUTIONS 2.2

144

SOLUTIONS 2.3

148

82

82

CHAPTER 3 THE K-MAP 3.1

INTRODUCTION

3.2

REPRESENTATION FOR BOOLEAN FUNCTIONS

3.2.1 3.2.2 3.3

Sum-of-Products (SOP) Product-of-Sum (POS)

155

156 156

STANDARD OR CANONICAL SUM-OF-PRODUCTS (SOP) FORM 156

3.3.1 3.3.2 3.3.3 3.4

155

Minterm 157 157 S Notation Converting SOP Form to Standard SOP Form

158

STANDARD OR CANONICAL PRODUCT-OF-SUMS (POS) FORM 158

3.4.1 3.4.2 3.4.3

Maxterm 158 159 P Notation Converting POS Form to standard POS Form

159

3.5

CONVERTING STANDARD SOP FORM TO STANDARD POS FORM

3.6

BOOLEAN EXPRESSIONS AND TRUTH TABLES

3.7

CALCULATION OF TOTAL GATE INPUTS USING SOP AND POS

3.8

KARNAUGH MAP (K-MAP)

3.8.1 3.8.2 3.8.3 3.9

PLOTTING A K-MAP

3.9.1 3.9.2 3.9.3

162

Structure of K-map 163 Another Structure of K-map Cell Adjacency 165

165

166

Plotting Standard SOP on K-map Plotting Standard POS on K-map Plotting a Truth Table on K-map

166 166 166

160

161 162

3.10

GROUPING OF CELLS FOR SIMPLIFICATION

3.10.1 3.10.2 3.10.3 3.10.4

Grouping of Two adjacent Cells (Pair) Grouping of Four Adjacent Cells (Quad) Grouping of Eight Adjacent Cells (Octet) Redundant Group 169

3.11

MINIMIZATION OF SOP EXPRESSIONS

169

3.12

MINIMIZATION OF POS EXPRESSIONS

170

3.13

CONVERTING SOP TO POS AND VICE-VERSA

3.14

DON’T CARE CONDITIONS

166

166 167 168

170

171

3.14.1 K-map Simplification With Don’t Care Conditions 171 3.14.2 Conversion of Standard SOP to Standard POS with Don’t Care Conditions 3.15

K-MAPS FOR MULTI-OUTPUT FUNCTIONS

3.16

LIMITATIONS OF K-MAP 172

EXERCISE 3.1

173

EXERCISE 3.2

186

EXERCISE 3.3

188

SOLUTIONS 3.1

192

SOLUTIONS 3.2

223

SOLUTIONS 3.3

228

171

171

CHAPTER 4 COMBINATIONAL CIRCUITS 4.1

INTRODUCTION

4.2

DESIGN PROCEDURE FOR COMBINATION LOGIC CIRCUITS

4.3

ADDERS

4.3.1 4.3.2 4.4

232 233 235

Half-Subtractor Full-Subtractor

235 236

4.5

BINARY PARALLEL ADDER

237

4.6

CARRY LOOK-AHEAD ADDER

238

4.6.1 4.6.2 4.6.3

238 239 239

Carry Generation Carry Propagation Look Ahead Expressions

4.7

SERIAL ADDER

240

4.8

COMPARATOR

241

4.8.1 4.8.2 4.9

4.10

1-bit Magnitude Comparator 2-bit Magnitude Comparator

MULTIPLEXER

4.9.1 4.9.2 4.9.3 4.9.4

231

232

Half-Adder Full-Adder

SUBTRACTORS

4.4.1 4.4.2

231

241 242

244

2-to-1 Multiplexer 245 4-to-1 Multiplexer 245 Implementation of Higher Order Multiplexers using Lower Order Multiplexers Applications of Multiplexers 247

DEMULTIPLEXER

4.10.1 1-to-2 Demultiplexer 4.10.2 1-to-8 Demultiplexer

247

248 249

247

4.10.3 Applications of Demultiplexers 250 4.10.4 Comparison between Multiplexer and Demultiplexer 4.11

DECODER 251

4.11.1 2-to-4 Line Decoder 4.11.2 Applications of Decoder 4.12

250

ENCODERS

253

4.12.1 Octal-to-Binary Encoder 4.12.2 Decimal-to-BCD Encoder 4.13

PRIORITY ENCODERS

256

4.14

CODE CONVERTERS

257

4.15

PARITY GENERATOR

259

4.15.1 Even Parity Generator 4.15.2 Odd Parity Generator EXERCISE 4.1

262

EXERCISE 4.2

281

EXERCISE 4.3

284

SOLUTIONS 4.1

291

SOLUTIONS 4.2

314

SOLUTIONS 4.3

318

252 253 253 254

260 260

CHAPTER 5 SEQUENTIAL CIRCUITS 5.1

INTRODUCTION

5.2

SEQUENTIAL LOGIC CIRCUITS

323

5.3

LATCHES AND FLIP-FLOPS

324

5.3.1 5.3.2 5.4

S - R Latch using NOR Gates S - R Latch using NAND Gates

FLIP-FLOPS

5.5.1 5.5.2 5.5.3 5.5.4 5.6

General Block Diagram of a Latch or Flip-flop Difference between Latches and Flip-flops 325

S-R LATCH 325

5.4.1 5.4.2 5.5

323

327

S-R Flip-Flop D-Flip Flop J-K Flip-Flop T Flip-Flop

327 328 329 331

TRIGGERING OF FLIP-FLOPS

5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6

325 326

332

Level Triggering 332 Edge Triggering 332 Edge Triggered S - R Flip Flop Edge Triggered D Flip-Flop Edge Triggered J - K Flip-Flop Edge Triggered T -Flip-Flop

334 336 337 339

5.7

OPERATING CHARACTERISTIC OF FLIP-FLOPS 340

5.8

APPLICATION OF FLIP-FLOPS

5.9

REGISTER

5.9.1 5.9.2

343

Buffer Register Shift Register

343 344

342

324

5.9.3 5.10

Applications of Shift Registers

345

COUNTER 345

5.10.1 Asynchronous and Synchronous Counter 5.10.2 Up-Counter and Down-Counter 5.10.3 MOD Number or Modulus of a Counter 5.11

SHIFT REGISTER COUNTERS

348

5.11.1 Ring Counter 5.11.2 Johnson Counter

349

EXERCISE 5.1

352

EXERCISE 5.2

369

EXERCISE 5.3

372

SOLUTIONS 5.1

383

SOLUTIONS 5.2

402

SOLUTIONS 5.3

407

345 346 348

348

CHAPTER 6 LOGIC FAMILIES 6.1

INTRODUCTION

6.2

CLASSIFICATION OF DIGITAL LOGIC FAMILY

6.3

CHARACTERISTIC PARAMETERS OF DIGITAL LOGIC FAMILY

6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.4

Speed of Operation 414 Power Dissipation 415 Voltage Parameters 415 Current Parameters 416 Noise Immunity or Noise Margin Fan-In 417 Fan-out 417 Operating Temperature 417 Speed Power Product 417

RESISTOR-TRANSISTOR LOGIC (RTL)

6.4.1 6.4.2 6.5

413

Circuit Operation Drawbacks of RTL Family

413

416

418

418 418

DIRECT COUPLED TRANSISTOR LOGIC (DCTL) 419

6.5.1

Circuit Operation

419

6.6

DIODE TRANSISTOR LOGIC (DTL)

6.7

TRANSISTOR-TRANSISTOR LOGIC (TTL)

6.8

TTL CIRCUIT OUTPUT CONNECTION

6.8.1 6.8.2 6.8.3

Totem-pole Output Open-collector Output Tri-state Output 423

6.9

TTL SUBFAMILIES

6.10

EMITTER COUPLED LOGIC (ECL)

419 421 422

422 423

424 425

6.10.1 ECL OR/NOR Gate 426 6.10.2 ECL Characteristics 427 6.10.3 Advantages and Disadvantages of ECL Family 6.11

INTEGRATED INJECTION LOGIC (I L) 2

6.11.1 Characteristic of I2L

428

428

427

414

6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.12

NMOS Inverter 430 NMOS NAND Gate 431 NMOS NOR Gate 432 Characteristics of MOS Logic

433

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) LOGIC

6.13.1 6.13.2 6.13.3 6.13.4 6.13.5 6.14

429 429

METAL OXIDE SEMICONDUCTOR (MOS) LOGIC 430

6.12.1 6.12.2 6.12.3 6.12.4 6.13

I2L Inverter 428 428 I2L NAND Gate I2L NOR Gate 429 Advantages of I2L Disadvantages of I2L

CMOS Inverter 434 CMOS NAND Gate 434 CMOS NOR Gate 435 Characteristics of CMOS Logic 436 Advantages and Disadvantages of CMOS Logic

COMPARISON OF VARIOUS LOGIC FAMILIES

EXERCISE 6.1

439

EXERCISE 6.2

455

EXERCISE 6.3

458

SOLUTIONS 6.1

465

SOLUTIONS 6.2

485

SOLUTIONS 6.3

490

437

437

CHAPTER 7 INTERFACING TO ANALOG 7.1

INTRODUCTION

7.2

DIGITAL TO ANALOG CONVERTER

7.2.1 7.3

7.4

7.5

496

R - 2R Ladder Type DAC Weighted Resistor Type DAC

496 497 497

7.4.1 7.4.2 7.4.3

499

Sample-and-hold circuit 498 Quantization and Encoding Parameters of ADC 499

ADC CIRCUITS

500

Flash Type A/D Converter 500 Counting A/D Converter 501 Dual Slope Type A/D Converter 503 Successive Approximation Type ADC

ASTABLE MULTIVIBRATOR

7.6.1 7.6.2 7.6.3 7.7

495

496

ANALOG-TO-DIGITAL CONVERTER

7.5.1 7.5.2 7.5.3 7.5.4 7.6

Parameters of DAC

DAC CIRCUITS

7.3.1 7.3.2

495

503

504

Astable Multivibrator Using BJT 505 Astable Multivibrator Using 555 Timer Astable Multivibrator Using Op-amps

507 507

MONOSTABLE MULTIVIBRATOR 508

7.7.1 7.7.2

Monostable Multivibrator Using BJT Monostable Multivibrator Using 555 Timer

508 510

433

7.8

SCHMITT TRIGGER

7.8.1 7.8.2

511

Schmitt Trigger Using BJT Schmitt Trigger Using 555 Timer

EXERCISE 7.1

515

EXERCISE 7.2

532

EXERCISE 7.3

535

SOLUTIONS 7.1

541

SOLUTIONS 7.2

564

SOLUTIONS 7.3

568

512 513

CHAPTER 8 MICROPROCESSOR 8.1

INTRODUCTION

8.2

MICROCOMPUTER

8.2.1 8.2.2 8.2.3 8.3

8.6

572

FETCH 573 EXECUTE

572

573

MICROPROCESSOR ARCHITECTURE

8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.5

571

Memory 572 Input-Output Interfacing System Bus 572

MICROPROCESSOR OPERATION

8.3.1 8.3.2 8.4

571

System Bus 573 Arithmetic Logic Unit (ALU) Registers 574 Program Counter (PC) 574 Flags 574 Timing and Control Unit

573

573

574

PIN DIAGRAM OF 8085 MICROPROCESSOR

574

8.5.1 8.5.2 8.5.3 8.5.4 8.5.5

576

Address and Data Bus 575 Control and Status Signals 575 Power Supply and Clock Frequency Interrupts and Other Operations 576 Serial I/O Ports 577

INSTRUCTION SET

8.6.1 8.6.2 8.6.3 8.6.4 8.6.5

577

Data Transfer Instructions Arithmetic Instructions Branching Instructions Logic Instructions Control Instructions

EXERCISE 8.1

589

EXERCISE 8.2

602

EXERCISE 8.3

605

SOLUTIONS 8.1

609

SOLUTIONS 8.2

621

SOLUTIONS 8.3

625

577 579 581 584 587

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Page 63 Chap 2

CHAPTER 2

Boolean Algebra and Logic Simplification

BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

2.1

i. n

INTRODUCTION

o c . a

This chapter, concerned with the basic study of Boolean algebra and simplification theory, includes the following topics: • Introduction to Boolean algebra: logic levels, truth table. •

Basic Boolean operations: addition, multiplication, not operation

•

Various theorems of Boolean algebra

•

Meaning of positive and negative logic

•

Various types of logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR gates.

. w w

• •

2.2

o n

i d

Universal logic gates; conversion of logic diagrams to universal logic gates.

Boolean analysis of logic circuits.

w

BOOLEAN ALGEBRA

Boolean algebra is mathematics of logic. It is one of the most basic tools which is used in the analysis and synthesis of logic circuit. In Boolean algebra, often the variables are represented by capital letters such as A, B , C , X , Y , Z . The Boolean value of a variable is either logic 0 or logic 1. These, 0 and 1, are known as Boolean constants.

2.2.1

Logic Levels Boolean logic variable ‘0’ or ‘1’ is not used to represent actual numbers but it is used to represent the state of voltage variable called logical level. Commonly used representation of logic levels are shown in Table below. Table 2.1: Representation of Logic Levels for Boolean Variables

Logic 0

Logic 1

False

True

Open switch

Close switch

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Page 64 Chap 2 Boolean Algebra and Logic Simplification

2.2.2

Logic 0

Logic 1

Low

High

No

Yes

OFF

ON

Truth Table A truth table represents the relation between all inputs and possible outputs of any logic device or logic circuit in a tabular form. The number of inputs may vary from one to many depending upon the device or complexity of the circuit. Number of output also varies in this way and may be one or more. For different digital circuits, some of the examples of truth table are given below.

in . o

Table 2.2: Examples of Truth Tables for 1-input, 2-input and 3-input Circuits

c . ia

d o

n . w w

w 2.3

BASIC BOOLEAN OPERATIONS

Boolean algebra uses only three basic operations, namely 1. OR operation

2.3.1

2.

AND operation

3.

NOT operation

Boolean Addition (Logical OR) The OR operation in Boolean algebra is similar to addition in ordinary algebra i.e., OR means logical addition operation. The logical OR operation on A and B is denoted by


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where ‘+’ is the OR operator Y = A + B, The output Y corresponding to various combinations of inputs, A and B , is shown in Table 2.3 below.


Table 2.3: Truth Table for OR Operation

Input

Output

A

B

Y = A+B

0

0

0

0

1

1

1

0

1

1

1

1

i. n

o c . a

NOTE :

The minimum number of inputs for OR operation is two. The number of outputs is always one, irrespective of the number of inputs.

2.3.2

i d

Boolean Multiplication (Logical AND)

o n

The AND operation in Boolean algebra is similar to multiplication in ordinary algebra i.e, AND performs logical multiplication operation. Let A and B be two Boolean variables. Then, the logical AND operation on A and B is denoted by Y = A : B, where : is the AND operator. The output Y corresponding to various combinations of inputs, A and B , is shown in Table 2.4 below.

. w w

w

Table 2.4: Truth table for AND operation

Input

Output

A

B

Y = AB

0

0

0

0

1

0

1

0

0

1

1

1

NOTE :

The minimum number of inputs for AND operation is two. The number of output is always one, irrespective of the number of inputs.

2.3.3

Logical NOT NOT is the simplest of the three basic operations of Boolean algebra. It is also known as inversion and complement. The NOT operation is indicated by a bar ‘-’ over the variable. If A is a variable, then NOT of A is expressed as A . The truth Table of the NOT operation is shown in Table 2.5.


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Table 2.5: Truth table for NOT operation


Input

Output

A

Y=A

0

1

1

0

NOTE :

Logical NOT is the only Boolean operation which must be performed with only one operand or one input. Note that in some texts, the NOT operation is also presented as Al .

2.4

THEOREMS OF BOOLEAN ALGEBRA

The theorems of Boolean algebra can be used to simplify many complex Boolean expression and also to transform the given expression into a more useful and meaningful equivalent expression. These theorems are discussed as below.

2.4.1

in . o

c . ia

Complementation Laws

The term complement implies to invert, i.e. to change 1’s to 0’s and 0’s to 1’s. The five laws of complementation are as follows: 1. The complement of 0 is 1, i.e. 0 = 1

d o

n . w w

The complement of 1 is 0, i.e. 1 = 0

2.

If A = 0 , then A = 1

3.

If A = 1, then A = 0

4. 5.

2.4.2

w

The double complementation does not change the function, i.e. A=A

AND Laws The four AND laws are as follows: 1. Null Law: A : 0 = 0

2.4.3

2.

Identity Law: A : 1 = A

3.

A:A = A

4.

A:A = 0

OR Laws The four OR laws are as follows: 1. Null Law: A + 0 = A 2.

Identity Law: A + 1 = 1

3.

A+A = A

4.

A+A = 1


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2.4.4


Commutative Laws Commutative law states that the order of the variable in OR and AND operations is not important. The two commutative laws are


A+B = B+A A:B = B:A

2.4.5

Associative Laws Associative law states that the grouping of variables in AND or OR expression does not affect the result. There are two associative laws. A + _B + C i = _A + B i + C A : _B : C i = _A : B i : C

2.4.6

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Distributive Law

The distributive laws allow factoring or multiplying out of expressions. There are two distributive laws

i d

A _B + C i = AB + AC A + BC = _A + B i_A + C i

2.4.7

o n

Redundant Literal Rule

. w w

This law states that ORing of a variable with the AND of the complement of that variable with another variable, is equal to ORing of the two variables, i.e. A + AB = A + B Another theorem based on this law is

w 2.4.8

A _A + B i = AB

Idempotent Law Idempotence means the same value. There are two idempotent laws A : A : A :g: A = A A+A+A+g+A = A

2.4.9

Absorption Law There are two absorption laws A+A:B = A A : _A + B i = A

2.4.10

Consensus Theorem There are two consensus theorems, AB + AC + BC = AB + AC _A + B i_A + C i_B + C i = _A + B i_A + C i


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Page 68 Chap 2

2.4.11

Transposition Theorem There are two transposition theorems, the first is given as


AB + AC = _A + C i_A + B i _A + B i : _A + C i = A : C + A : B

2.4.12

De Morgan’s Theorem De Morgan’s theorem gives two of the most powerful laws in Boolean algebra. These theorems are very useful in simplification of Boolean expressions, A+B = A B AB = A + B

2.4.13

Shannon’s Expansion Theorem According to this theorem, any switching expression can be decomposed with respect to a variable A into two parts, one containing A and the other containing A . This concept is useful in decomposing complex system into an interconnection of smaller components.

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f _A, B, C, ....i = A : f _1, B, C...i + A : f _0, B, C, ...i f _A, B, C, ...i = 8A + f _0, B, C, ...iB : 8A + f _1, B, C, ...iB

2.5

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SIMPLIFICATION OF BOOLEAN EXPRESSIONS USING BOOLEAN ALGEBRA

n . w w

In Boolean algebra, we have to reduce the Boolean expression into its simplest form such that the hardware cost reduces efficiently. The basic rules, laws and theorems of Boolean algebra discussed in this chapter, are used to simplify Boolean expressions. The following steps are used to simplify a Boolean expression using Boolean algebra,

w

METHODOLOGY: TO SIMPLIFY A BOOLEAN EXPRESSION USING BOOLEAN ALGEBRA

1. Remove all parentheses and multiply all variables. 2. Look for the identical terms. Only one of those terms be retained and all others skipped. For example, AB + AB + AB = AB 3. Look for a variable and its complement in the same term. This term can be removed. For example, A : BB = A : 0 = 0 ; ABCC = AB : 0 = 0 4. Look for pairs of terms that are identical except for one variable which may be missing in one of the terms. The larger term can be removed. For example, ABC D + ABC = ABC _D + 1i = ABC : 1 = ABC


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5. Look for pairs of terms which have the same variables, except in one term a variable is complemented and in other term is it not. Such terms can be combined into a single terms. For example,


ABC D + ABC D = ABC _D + D i = ABC : 1 = ABC AB _C + D i + AB _C + D i = AB 7_C + D i + _C + D iA = AB : 1 = AB

6. Apply Boolean theorem and laws discussed earlier for further simplification.

2.5.1

Complement of Boolean Function

i. n

The complement of a Boolean function is obtained in the following steps:

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METHODOLOGY: TO OBTAIN COMPLEMENT OF BOOLEAN EXPRESSION

1. Change all the ANDs to ORs and all the ORs to ANDs i.e., change all ‘:’ to ‘+’ and all ‘+’ to ‘:’

i d

2. Complement each of the individual variables.

o n

3. Change all 0’s to 1’s and 1’s to 0’s.

2.5.2

. w w

Principal of Duality

Duality is a very important property of Boolean algebra. The dual of a Boolean expression is obtained by replacing all ‘:’ operations with ‘+ ’ operations, all ‘+’ operations with ‘:’ operations, and complementing all 0’s and 1’s. The variables are not complemented in this process. Dual of a function f _A, B, C, ...i is given as

w

7f _A, B, C,..., 0, 1, + , :iAd = f _A, B, C, ..., 1, 0, : , +i

2.5.3

Relation Between Complement and Dual For a given Boolean expression f _A, B, C, ...i the relation between its complement and dual expressions are given as fc _A, B, C,....i = f _A, B, C, ...i = fd _A, B , C , ...i fd _A, B, C,...i = f _A, B , C , ...i = fc _A, B , C , ....i where subscript ‘c ’ represents the complement and subscript ‘d ’ represents the dual of the given function. NOTE :

The above relation states that the dual can be obtained by complementing all the literals in complement function f Â, B, C, ....h .

2.6

LOGIC GATES

Logic gates are the fundamental building blocks of digital systems. Logic gates are electronic circuits that perform the most elementary


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Boolean operations. Before understanding the logic gates, we must understand the meaning of positive and negative logic.


2.6.1

Logic Levels Inputs and outputs of logic gates can occur only in two levels. These two levels are termed HIGH and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0. There are two different ways to assign a signal value to logic level such as positive logic and negative logic. 1. Positive Logic: If higher of the two voltage levels represents a logic ‘1’ and the lower of the two levels represents a logic ‘0’, then the logic system is referred to as a positive logic system. Figure 2.1 shows the positive logic system.

Figure 2.1: Positive Logic System

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2.

Negative Logic: If the higher of the two voltage levels represents a logic ‘0’ and the lower of the two levels represents a logic ‘1’, then the logic system is referred to as a negative logic system. Figure 2.2 shows the representation of negative logic systems.

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Figure 2.2: Negative Logic System

3.

2.6.2

Mixed Logic: In mixed logic, the assignment of logical values to voltage values is not fixed, and it can be decided by the logic designers. Mixed logic provides a simplified mechanism for the analysis and design of digital circuits. The proper use of mixed logic notation provides logic expressions and logic diagrams that are analogue to each other. Also, a mixed logic diagram provides clear information as to the operation of a circuit.

Types of Logic Gates Logic gates are electronic circuits with a number of inputs and one output. There are three basic logic gates, namely 1. OR gate, 2.

AND gate,

3.

NOT gate


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Other logic gates that are derived from these basic gates are 1. NAND gate,


2.

NOR gate,

3.

EXCLUSIVE-OR gate,

4.

EXCLUSIVE-NOR gate

AND Gate An AND gate is a logic circuit with two or more inputs and one output that performs ANDing operation. The output of an AND gate is HIGH only when all of its inputs are in the HIGH state. In all other cases, the output is LOW. For a positive logic systems, it means that the output of the AND gate is a logic ‘1’ only when all of its inputs are in logic ‘1’ state. In all other cases, the output is logic ‘0’. The logic symbol and the truth table of a two-input AND gate are shown in Figure 2.3 and Table 2.6 respectively.

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Figure 2.3: Logic Symbol of Two-input AND gate

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Table 2.6: Truth table of a 2-input AND gate

Input

w

Output

A

B

Y = AB

0

0

0

0

1

0

1

0

0

1

1

1

OR Gate An OR gate is a logic circuit with two or more inputs and one output that performs ORing operation. The output of an OR gate is LOW only when all of its inputs are LOW. For all other possible input combinations, the output is HIGH. For a positive logic system, the output of an OR gate is a logic ‘0’ only when all of its inputs are at logic ‘0’. For all other possible input combinations, the output is a logic ‘1’. The logic symbol and the truth table of a two-input OR gate are shown in Figure 2.4 and Table 2.7 respectively.

Figure 2.4: Logic Symbol of Two-input OR gate


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Table 2.7: Truth table of a 2-input OR gate

Input


Output

A

B

Y = A+B

0

0

0

0

1

1

1

0

1

1

1

1

NOT Gate A NOT gate, also called an inverter is a one-input, one-output logic circuit whose output is always the complement of the input. That is, a LOW input produces a HIGH output, and vice versa. It means that for a positive logic system, a logic ‘0’ at the input produces a logic ‘1’ at the output, while a logic ‘1’ at the input produces a logic ‘0’ output. It is also known as a complementing circuit or an inverting circuit. The logic symbol and the truth table of an inverter are shown in Figure 2.5 and Table 2.8 respectively.

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Figure 2.5: Symbol for a NOT gate

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Table 2.8: Truth Table of NOT Gate

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Input

Output

A

Y=A

0

1

1

0

NAND Gate The term NAND implies NOT-AND. A NAND gate is equivalent to AND gate followed by a NOT gate. The standard logic symbol for a 2-input NAND gate is shown in Figure 2.6. This symbol is same as AND gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

Figure 2.6: Logic symbol of NAND gate

The truth Table 2.9 of a NAND gate is obtained from the truth Table of an AND gate by complementing the output entries. The output of a NAND gate is a logic ‘0’ when all its inputs are a logic ‘1’.


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For all other input combinations, the output is a logic ‘1’. NAND gate operation is logically expressed as


Y = A:B Table 2.9: Truth Table of a 2-input NAND Gate

Input

Output

A

B

Y = AB

0

0

1

0

1

1

1

0

1

1

1

0

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NOR Gate

The term NOR implies NOT-OR. A NOR gate is equivalent to OR gate followed by a NOT gate. The standard logic symbol for a 2-input NOR gate is shown in Figure 2.7. This symbol is same as OR gate symbol except for a small circle (bubble) on its output. This circle represents the NOT function.

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Figure 2.7: Logic symbol of NOR gate

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The truth Table 2.10 of a NOR gate is obtained from the truth Table of an OR gate by complementing the output entries. The output of a NOR gate is a logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations, the output is a logic ‘0’. The output of a two-input NOR gate is logically expressed as Y = A+B

Table 2.10: Truth table of a 2-input NOR gate

Input

Output Y = A+B

A

B

0

0

1

0

1

0

1

0

0

1

1

0

Exclusive-OR (XOR) Gate The Exclusive-OR gate, commonly known as EX-OR gate, is a twoinput, one-output gate. The logic symbol for the Ex-OR gate is shown in Figure 2.8 and the truth table for a two-input EX-OR operation is given in Table 2.11.


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Figure 2.8: Symbol for 2-input Ex-OR Gate Table 2.11: Truth Table of a 2-input Ex-OR Gate

Input

Output

A

B

Y = A5B

0

0

0

0

1

1

1

0

1

1

1

0

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From the truth table it can be stated that, the output of an EXOR gate is a logic ‘1’ when the two inputs are at different logic and a logic ‘0’ when the two inputs are at the same logic.

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NOTE :

1.

2.

The exclusive-OR and equivalence gates both can be extended to more than two inputs. However, multiple-input exclusive OR gates are uncommon from the hardware standpoint. For a multiple output-input EX-OR logic function we can conclude that the output of a multiple-input EX-OR logic function is a logic ‘1’ only when an odd number of input variables are ‘1’.

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Exclusive-NOR (XNOR) Gate

The exclusive-NOR gate, commonly known as Ex-NOR, is an Ex-OR gate, followed by an inverter. It has two inputs and one output. The logic symbol for the Ex-NOR gate is shown in Figure 2.9, and the truth table for the two-input Ex-NOR operation is given in Table 2.12.

w

Figure 2.9: Symbol for 2-input Ex-NOR Gate Table 2.12: Truth Table of a 2-input Ex-NOR Gate

Input

Output

A

B

Y = A9B

0

0

1

0

1

0

1

0

0

1

1

1


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The Boolean expression for the Ex-NOR gate is Y = A 5 B . Using DeMorgan’s theorem, A 5 B = AB + AB = AB : AB = (A + B ) (A + B) = AB + A B


The output of a two-input EX-NOR gate is a logic ‘1’ when the inputs are same and a logic ‘0’ when they are different. NOTE :

1.

2.

Likewise Ex-OR gates, three or more variable Ex-NOR gates also do not exist. Normally, multiple-input EX-NOR logic functions can be implemented using more than one 2-input Ex-NOR gates. For a multiple output-input EX-NOR logic function we can conclude that the output of a multiple-input EX-NOR logic function is a logic ‘1’ only when an even number of input variables are ‘0’. Note if all inputs are 0, then also output will be ‘1’.

2.7

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UNIVERSAL GATE

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NAND and NOR gates are known as universal gates because any of these two gates is capable of implementing all other gate functions.

2.7.1

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NAND Gate as a Universal Gate

The NAND gate can be used to implement the NOT function, AND function, the OR function and other functions also as explained below.

The NOT Gate using NAND Gate

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An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Figure 2.10, for a two-input NAND gate. Algebraically, we may write Y = A:B = A:A = A

Figure 2.10: NOT gate using NAND gate

The AND Gate Using NAND Gate To construct an AND gate from NAND gates, an inverter or a NOT gate is required to invert the output of a NAND gate. This inversion cancels out the first inverted operation of NAND gate and the final result will be AND function as depicted in Figure 2.11. Algebraically, Y = AB = AB

Figure 2.11: AND Gate using NAND Gate


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The OR Gate using NAND Gate To construct OR function using only NAND gates, first we transform the OR function as follows. Y = A+B = A+B

A=A

(De Morgan’s Theorem) = A:B The above equation is implemented using only NAND gates as shown in the Figure 2.12.

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Figure 2.12: OR Gate using NAND Gate

The NOR Gate Using NAND Gate

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We know that Boolean expression for NOR gate is (De Morgan’s Theorem) Y = A+B = A:B

d o

= A:B A=A The above equation is implemented using only NAND gates, as shown in the Figure 2.13.

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Figure 2.13: NOR Gate Using NAND Gate

The Ex-OR Gate using NAND Gate The Boolean expression for Ex-OR gate is given by Y = AB + AB = AB + AB

X=X


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(De Morgan Theorem) = _AB i : _AB i So, five NAND gates are required to implement the Ex-OR gate as shown in Figure 2.14.


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Figure 2.14: Ex-OR Gate using NAND Gate

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Ex-NOR Gate Using NAND Gate

Ex-NOR gate can be constructed by taking complement of Ex-OR. That is, we need one more NAND gate to implement the Ex-NOR function. Figure 2.15 shows Ex-NOR implementation using five NAND gates.

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Figure 2.15: Ex-NOR Gate Using NAND Gate

2.7.2

NOR Gate as a Universal Gate Just like the NAND gate, the NOR gate also may be used to implement all other operations of Boolean algebra. These are explained in following texts.

NOT Gate Using NOR Gate In the same way as the NAND gate described above, an inverter can be made from a NOR gate by connecting all of the inputs together and creating, in effect, a single common input, as shown in Figure 2.16. Algebraically, Y = A+B = A+A = A

Figure 2.16: NOT Gate Using NOR Gate


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OR Gate Using NOR Gate An OR gate can be created by simply inverting the output of a NOR gate as shown in Figure 2.17. Algebraically, Y = A+B = A+B

Figure 2.17: AND Gate Using NOR Gate

AND Gate using NOR Gate AND function can be generated using three NOR gates. We know that Boolean expression for AND gate is Y = A:B

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= A:B

A=A

(DeMorgan’s Theorem) = A+B The above equation is implemented using only NOR gates as shown in the Figure 2.18.

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NAND Gate using NOR Gate

The Boolean expression for NAND gate is

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Y = A:B = A+B

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(DeMorgan’s Theorem)

= A+B A=A The above equation is implemented using only NOR gates, as shown in the Figure 2.19.

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Figure 2.18: AND Gate Using NOR Gate

Figure 2.19: NAND gate using NOR gate


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The Ex-OR Gate using NOR Gate XOR function may also be implemented by using NOR gates. The ExOR operation is given by, Y = AB + BA = AA + AB + BA + BB


_AA = BB = 0i

= A _A + B i + B _A + B i = A _A + B i + B _A + B i = _A + A + B i + _B + A + B i = _A + A + B i + _B + A + B i _X = X i The above expression can be realized using five NOR gates as shown in Figure 2.20.

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Figure 2.20: Ex-OR Gate Using NOR Gate

The Ex-NOR Gate using NOR Gate To implement Ex-NOR gate using NOR gates, we just remove the last NOR gates from the circuit of Ex-OR gates shown in Figure 2.21.

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Figure 2.21: Ex-NOR Gate using NOR Gate

2.8

ALTERNATE LOGIC-GATE REPRESENTATIONS

We have discussed the five basic logic gates (AND, OR, INVERTER, NAND, and NOR) and the standard symbols used to represent them in a logic circuit diagram. Most of the logic networks use standard symbols. But in some networks an alternative set of symbols is used in addition to the standard symbols. Table 2.13 shows the alternate set of symbols for the five basic gates.


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Table 2.13: Alternate Logic Gate Representations


Logic

Normal Symbol

Alternate symbol

NOT

AND

OR

NAND

NOR

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To convert any normal symbol to its corresponding alternate symbol, the following steps are used:

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METHODOLOGY: TO CONVERT STANDARD SYMBOL TO ALTERNATE SYMBOL

Step 1:

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Add bubbles (indication of inversion) at those input or output points where it is not present.

n . w w

Step 2:

Remove all pre-existing bubbles of the normal symbol, if there is any at the point (only NOT, NAND and NOR gates)

Step 3:

If the existing normal logic symbol is AND, change it to OR, Similarly, if it is OR, then change it to AND. There is no change for the triangular symbol of NOT gate.

w 2.9

BOOLEAN ANALYSIS OF LOGIC CIRCUITS

A Boolean function may be transformed from an algebraic expression into a logic diagram using AND, OR and NOT gates. This is also referred to as AOI logic. Conversely, a logic circuit can be transformed into Boolean expressions for the analysis.

2.9.1

Converting Boolean Expressions to Logic Diagram The simplest way to convert a Boolean expression to a logic circuit is to start with the output and work towards the input. Assume that the expression Y = AB + AC + ABC is to be realized using AOI logic. Start with the final expression AB + AC + ABC , we go through following steps:


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METHODOLOGY: TO CONVERT BOOLEAN EXPRESSION TO LOGIC DIAGRAM

Step 1:

The expression Y = AB + AC + ABC contains three terms (AB , AC , ABC ) which are ORed together. So, draw an OR gate with three inputs as shown below.

Step 2:

AB must be the output of an AND gate whose inputs are A and B and AC must be output of an AND gate whose inputs are A and C . Similarly, ABC must be output of a 3-input AND gate with inputs A , B and C . We introduce these three AND gates as shown below.


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w

Step 3:

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Now, C must be the output of an inverter whose input is C and similarly, A will be the output of an inverter whose input is A. So we put two inverters as shown below.

This is the complete logic diagram of given function

2.9.2

Converting Logic to Boolean Expressions Any logic circuit, no matter how complex it is, can be described using Boolean expressions. To derive the Boolean expression for a given logic circuit, start from the left-most input and work toward the final output, writing output for each gate. As an example, consider the logic


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diagram shown in Figure 2.22. We go through the following steps to get the Boolean expression.


Figure 2.22: Logic diagram for which Boolean expression to be determined METHODOLOGY: EXPRESSION

2.10

TO

CONVERT

LOGIC

DIAGRAM

TO

BOOLEAN

Step 1:

In the logic diagram shown in Figure 2.22, the output of left-most OR gate with inputs A and B is _A + B i .

Step 2:

The output of left-most AND gate with inputs C and D is CD .

Step 3:

The outputs of the OR gate and AND gate are the inputs of right-most AND gate. Therefore, the expression for this AND gate is _A + B i : CD , which is the final output expression for the entire circuit.

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CONVERTING LOGIC DIAGRAMS TO NAND / NOR LOGIC

n . w w

Since, NAND logic and NOR logic are universal logic system, digital circuits which are first computed and converted to AOI logic may then be converted to either NAND logic or NOR logic depending on the choice.

2.10.1

w

NAND-NAND Logic A logic network can be converted into NAND-NAND gate network by going through following steps: METHODOLOGY: TO OBTAIN NAND-NAND GATE NETWORK

Step 1:

First draw the circuit in AOI logic i.e., using AND, OR and NOT gates.

Step 2:

Add a circle (bubble) at the output of each AND gate and at the inputs to all the OR gates.

Step 3:

Add an inverter on each line that received only one circle in steps 2, so that the polarity of signals on those lines remains unchanged from that of the original diagram.

Step 4:

Replace bubbled OR by NAND and each inverter by its NAND equivalent.


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NOR-NOR Logic The procedure of converting an AOI logic to NOR-NOR logic is same as above except steps 2 and 4.


METHODOLOGY: TO OBTAIN NOR-NOR GATE NETWORK

Step 1:

First draw the circuit in AOI logic i.e., using AND, OR and NOT gates.

Step 2:

Add a circle (bubble) at the output of each OR gate and at the inputs to all the AND gates.

Step 3:

Add an inverter on each line that received only one circle in steps 2, so that the polarity of signals on those lines remains unchanged from that of the original diagram.

Step 4:

Replace bubbled AND by NOR and each inverter by its NOR equivalent.

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***********

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w


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EXERCISE 2.1


MCQ 2.1.1

In the following circuit the output Z is

in . o

(A) (A + B ) (C + D ) (E + F) (B) AB + CD + EF (C) (A + B) (C + D) (E + F)

c . ia

(D) AB + CD + EF

MCQ 2.1.2

d o

In the following circuit, the output X is

n . w w

w MCQ 2.1.3

(A) MNQ

(B) N (Q + M )

(C) M (Q + N )

(D) Q (M + N )

In the following circuit, the output Z is

(A) AB + (C + D) E

(B) AB (C + D) E

(C) AB + CD + E

(D) AB + CDE


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MCQ 2.1.4


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The Boolean expression (X + Y) (X + Y ) (X + Y) is equivalent to (A) XY (B) XY (C) XY

MCQ 2.1.5



(D) XY

In the following circuit, the output Z is

i. n

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(A) A + B + C

(B) ABC

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(C) AB + BC + AC

MCQ 2.1.6

o n

Given that AB + AC + BC = AB + AC , then (A + C ) (B + C ) (A + B) is equivalent to (A) (A + B ) (A + C ) (B) (A + B) (A + C )

. w w

(C) (A + B ) (A + C )

MCQ 2.1.7

MCQ 2.1.8

(D) Above all

(D) (A + B ) (A + C )

w

In the following circuit the output X is

(A) AB

(B) AB

(C) AB

(D) 0

In the following circuit the output Y is

(A) AB + AB + C

(B) AB + AB + C

(C) AB + AB + C

(D) AB + AB + C


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MCQ 2.1.9



MCQ 2.1.10

MCQ 2.1.11

(A) ABC

(B) ABC

(C) ABC

(D) 0


in . o

(A) ABC

(B) AB (C + B)

(C) ABC

(D) AB (C + B)

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(A) ABC

(B) ABC

(C) 0

(D) ABC

w MCQ 2.1.12

The truth table of a circuit is shown below. A

B

C

X

0

0

0

1

0

0

1

0

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

0

The expression for X is (A) AB + BC + AC + BC

(B) BC + ABC

(C) BC

(D) ABC


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MCQ 2.1.13

MCQ 2.1.14

Digital Electronics

A + BC is equivalent to (A) (A + B) (A + C )

(B) A + B

(C) A + C

(D) (A + B ) (A + C )

A

B

C

Z

0

0

0

1

0

0

1

0

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1


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(C) (A + B) (B + C )

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(A) (A + B ) (B + C )

(B) (A + B ) (B + C ) (D) Above all

The Boolean expression for the truth table shown is

w

MCQ 2.1.16

Page 87 Chap 2

The truth table of a circuit is shown below.

The Boolean expression for Z is

MCQ 2.1.15


A

B

C

f

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

1

1

0

0

0

1

0

1

0

1

1

0

1

1

1

1

0

(A) B (A + C) (A + C )

(B) B (A + C ) (A + C )

(C) B (A + C ) (A + C )

(D) B (A + C ) (A + C )

The Boolean expression AC + BC is equivalent to (A) AC + BC + AC (B) BC + AC + BC + ACB (C) AC + BC + BC + ABC (D) ABC + ABC + ABC + ABC


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MCQ 2.1.17


Expression A + AB + A BC + ABC D + A B C DE would be simplified to (A) A + AB + CD + E (B) A + B + CDE (C) A + BC + CD + DE (D) A + B + C + D + E

MCQ 2.1.18

The simplified form of a logic function Y = A (B + C (AB + AC )) is (A) A B (B) AB (C) AB

MCQ 2.1.19

(D) AB

The reduced form of the Boolean expression of Y = (AB ) : (AB ) is (A) A + B

in . o

(B) A + B (C) AB + AB

c . ia

(D) A B + AB

MCQ 2.1.20

n . w w

(C) 0

MCQ 2.1.21

MCQ 2.1.22

d o

If XY + XY = Z then XZ + X Z is equal to (B) Y (A) Y

w

If XY = 0 then X 5 Y is equal to (A) X + Y

(B) X + Y

(C) XY

(D) XY

If A = 0 in logic expression Z = [A + EF + BC + D] [A + DE + BC + DE ] , then (A) Z = 0 (B) Z = 1 (C) Z = BC

MCQ 2.1.23

(D) 1

(D) Z = BC

From a four-input OR gate the number of input condition, that will produce HIGH output are (A) 1 (B) 3 (C) 15

(D) 0


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MCQ 2.1.24


Digital Electronics


In the following circuit, for which of the following input combination output will be 1 ?


(A) A = 0, B = 0 (B) A = 1, B = 0 (C) A = 0, B = 1

i. n

(D) Either A = 1 or B = 1

MCQ 2.1.25

o c . a

A logic circuit control the passage of a signal according to the following requirements: 1. Output X will equal A when control input B and C are the same. 2.

i d

X will remain HIGH when B and C are different.

o n

The logic circuit would be

. w w

w MCQ 2.1.26

The output of logic circuit is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH. The logic circuit is


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MCQ 2.1.27


Consider the statements below. 1. If the output waveform from an OR gate is the same as the waveform at one of its inputs, the other input is being held permanently LOW. 2.

If the output waveform from an OR gate is always HIGH, one of its input is being held permanently HIGH.

The statement, which is always true, is (A) Both 1 and 2 (B) Only 1 (C) 2 (D) None of the above

Common Data For Q. 28 and 29 : A Boolean function Z = ABC is to be implemented using NAND and NOR gate. Each gate has unit cost. Only A, B , and C are available.

MCQ 2.1.28

in . o

(C) 4 units

MCQ 2.1.29

c . ia

If both gates are available then minimum cost is (A) 2 units (B) 3 units

d o

n . w w

If only NAND gates are available, then minimum cost is (A) 2 units (B) 3 units (C) 4 units

MCQ 2.1.30

(D) 6 units

(D) 6 units

w

In the circuit shown below the LED emits light when

(A) both switches are closed (B) both switches are open (C) only one switch is closed (D) LED does not emit light irrespective of the switch positions


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MCQ 2.1.31


Digital Electronics


If the input to the digital circuit shown below consisting of a cascade of 20 XOR gates is X , then the output Y is equal to


MCQ 2.1.32

(A) X

(B) X

(C) 0

(D) 1

In the network shown below F can be written as

i. n

o c . a

i d

(A) X0 X1 X3 X5 + X2 X4 X5 ...Xn - 1 + ...Xn - 1 Xn

o n

(B) X0 X1 X3 X5 + X2 X3 X4 ...Xn + ...Xn - 1 Xn

. w w

(C) X0 X1 X3 X5 ...Xn + X2 X3 X5 ...Xn + ... + Xn - 1 Xn (D) X0 X1 X3 X5 ...Xn - 1 + X2 X3 X5 ...Xn + ... + Xn - 1 Xn - 2 + Xn

w

MCQ 2.1.33

The gate G1 and G2 in figure shown below have propagation delays of 10 ns and 20 ns respectively.

If the input Vi makes an abrupt change from logic 0 to 1 at t = t0 then the output waveform Vo is

[t1 = t0 + 10 ns, t2 = t1 + 10 ns, t3 = t2 + 10 ns]


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MCQ 2.1.34

Which of the following Boolean expressions correctly represents the relation between P, Q, R and M1


MCQ 2.1.35

(A) M1 = (P OR Q) XOR R

(B) M1 = (P AND Q) XOR R

(C) M1 = (P NOR Q) XOR R

(D) M1 = (P XOR Q) XOR R

If the X and Y logic inputs are available and their complements X and Y are not available, the minimum number of two-input NAND required to implement X 5 Y is (A) 4 (B) 5

c . ia

(C) 6

MCQ 2.1.36

in . o

(D) 7

d o

In the negative logic system, (A) The more negative of the two logic levels represents a logic ‘1’ state

n . w w

(B) The more negative of the two logic levels represents a logic ‘0’ state (C) All input and output voltage levels are negative (D) The output is always complement of the intended logic function

w MCQ 2.1.37 IES EE 1992

Positive logic in a logic circuit is one in which (A) logic 0 and 1 are represented by 0 and positive voltage respectively (B) logic 0 and 1 are represented by negative and positive voltages respectively (C) logic 0 voltage level is higher than logic 1 voltage level (D) logic 0 voltage level is lower than logic 1 voltage level

MCQ 2.1.38 IES EC 2002

How is inversion achieved using Ex-OR gate ? (A) Giving input signal to the two input lines of the gate tied together (B) Giving input to one input line and logic zero to the other line (C) Giving input to one input line and logic one to the other line (D) Inversion cannot be achieved using Ex-OR gate


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MCQ 2.1.39


Digital Electronics


Match List-I with List-II and select the correct answer using the codes given below the lists. List - I

List - II

a.

A5B = 0

1.

A= YB

b.

A+B = 0

2.

A=B

c.

A:B = 0

3.

A = 1 or B = 1

d.

A5B = 1

4.

A = 1 or B = 0

MCQ 2.1.40 IES EE 1999

a 3 2 3 2

b 2 3 2 3

c 1 4 4 1

d 4 1 1 4


i. n

Codes : (A) (B) (C) (D)

Page 93 Chap 2

o c . a

o n

i d

Consider the following statements: (1) A NAND gate is equivalent to an OR gate with its inputs inverted.

. w w

(2) A NOR gate is equivalent to an AND gate with its inputs inverted. (3) A NAND gate is equivalent to an OR gate with its output inverted. (4) A NOR gate is equivalent to an AND gate with its output inverted.

w

Which of these statements are correct? (A) 1 and 2 (B) 2 and 3 (C) 3 and 4

MCQ 2.1.41

(D) 1 and 4

The output (X ) waveform for the combination circuit shown below for the inputs at A and B (waveform shown in the figure) will be


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MCQ 2.1.42

c . ia

d o

Which of the following represents the correct waveform for X in the given circuit diagram.

n . w w

w


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MCQ 2.1.43


Digital Electronics


A logic circuit and input waveform to it shown below.


i. n

The output waveform is represented by

i d

o n

. w w

o c . a

w

MCQ 2.1.44

In a natural food restaurant, fruit is offered for desert but only in certain combination. One choice is either orange or apple or both. Another choice is either mango and apple or neither. A third choice is orange, but if you choose orange, then you must also take banana. If the fruits are represented by their first alphabet of the name, then the logical expression that specifies the fruit available for desert in the simplified form is (B) M + O (A) A + B (C) A + O

MCQ 2.1.45

(D) M + B

The open collector wired circuit shown below functions as

(A) Ex-NOR

(B) AND

(C) Ex-OR

(D) NOR


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MCQ 2.1.46

The simplified form of the expression (w + x) (w l + x + yz l ) (w + y l ) is (A) w l xy l + wx l + w l yz (B) w l xy l + wx (C) xy l + wx + wyz l (D) xy l + wx + w l yz

MCQ 2.1.47

The elevator door should open if the elevator is stopped, it is level with the floor, and the timer has not expired, or if the elevator is stopped, it is level with the floor, and a button is pressed. If D " Elevator door opens ; S " Elevator is stopped ; F " Level with floor ; T " Timer expired ; B " Button pressed Which of the following Boolean expression represents the above condition ? (A) D = SFT l + SFB (B) D = SFT l B (C) D = SF + T l B (D) D = (S + F ) T l B

MCQ 2.1.48

The logic circuit shown in the given figure can be minimized to


in . o

c . ia

d o

n . w w

w MCQ 2.1.49


(A) AD (B + C ) + A D

(B) AD (B 5 C ) + A D

(C) AD (B 5 C ) + A D

(D) A D (B 5 C ) + AD


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MCQ 2.1.50


Digital Electronics


What does the expression AD + ABCD + ACD + AB + AC D + A B on minimization result into ? (A) A + D (B) AD + A


(C) AD (D) A + D

MCQ 2.1.51

Which one of the following logical operations is performed by the digital circuit shown below ?

i. n

o n

(A) NOR

. w w

(C) Ex-OR

MCQ 2.1.52 IES EE 1995

i d

o c . a (B) NAND (D) OR

The switching circuit given in the figure an be expressed in binary logic notation as

w

(A) L = (A + B) (C + D) E (B) L = AB + CD + E (C) L = E + (A + B) (C + D) (D) L = (AB + CD) E

MCQ 2.1.53 IES EE 2005

Which of the following statements is not correct ? (A) X + XY = X (B) X (X + Y) = XY (C) X + XY = X (D) ZX + ZXY = ZX + ZY


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MCQ 2.1.54

Consider the given circuit diagram of switching of light from two different switches.


The input conditions needed to turn on LED is (B) A = B = 0 (A) A = B = 1 (C) A = 1; B = 0

MCQ 2.1.55 IES EC 1996

(D) Both (A) and (B)

in . o

c . ia

Which one of the following is the dual-form of the Boolean identity given below ? AB + AC = (A + C) (A + B)

d o

(A) AB + AC = AC + AB

(B) (A + B) + (A + C) = (A + C) (A + B)

n . w w

(C) (A + B) (A + C) = AC + AB (D) AB + AC = AB + AC + BC

MCQ 2.1.56

w

What is dual of A + [B + (AC )] + D ? (A) A + [B (A + C)] + D (B) A 7B + AC A D (C) A + [B _A + C i] D

MCQ 2.1.57 IES EE 2004

If x and y are Boolean variables, which one of the following is the equivalent of x 5 y 5 xy ? (A) x + y (B) x + y (C) 0

MCQ 2.1.58

(D) A [B _A + C i] D

(D) 1

The minimized form of _X + W i_Y 5 Z i + XW l is (A) (X + W ) (YZ l + Y l Z ) + XW l (B) (XYZ l + XY l Z + WYZ l + WY l Z ) (C) WYZ l + WY l Z + XW l (D) WYZ l + WY l Z


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MCQ 2.1.59


Digital Electronics


Which of the following logic diagrams represents the original and simplified expression of the function, F = (x + y) (x + y l ) ?


i. n

i d

o n

. w w

w

MCQ 2.1.60 IES EC 1992

o c . a

A copy machine generate a stop sign S , to stop the machine operation and energize and indicates light if according to either of the following conditions exists: (1) There is no paper in the paper feeder tray. (2) The two micro switch in the paper path are activated, indicating a jam in the paper path. The presence of paper in the feeder tray is indicated by a high at logic signal P as shown in figure.


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Which of the following represents the correct logic circuit so as to get HIGH output at S ?


MCQ 2.1.61

In the following circuit, the motor will turn on when DRIVE = 1

in . o

c . ia

d o

n . w w

Which of the following give correct values of A0, A1, A2, A3, A4, A5, A6, A7, A8 , and A9 in order to move motor ? (A) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = A9 = 1

w

(B) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A9 = 1; A7 = A8 = 0; (C) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = 1 ; A8 = A9 = 0 (D) A0 = A1 = A2 = A3 = A4 = A5 = A6 = A7 = A8 = 1 ; A9 = 0

MCQ 2.1.62

When two gates with open collector outputs are tied together as shown in the figure, the output obtained will be

(A) A + B + C + D

(B) A + B + C + D

(C) (A + B ) + (C + D )

(D) (A + B) + (C + D)


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MCQ 2.1.63


Digital Electronics


The output of a two level AND-OR gate network is F . What is the output when all the gates are replaced by NOR gates ? (A) F (B) F


(C) F D (D) F

D

where F D is the dual function of F Which one of the gates labelled 1,2,3, and 4 in the network shown in the figure is redundant ?

i. n

(B) 2

. w w

(C) 3

(D) 4

i d

o n

(A) 1

o c . a

w

MCQ 2.1.64

GATE EE 2002

For the circuit shown in Figure, the Boolean expression for the output Y in terms of inputs P , Q , R , and S is

(A) P + Q + R + S (B) P + Q + R + S (C) (P + Q ) (R + S ) (D) (P + Q) (R + S)

MCQ 2.1.65

Which of the following circuit implement the Boolean expression X = AB + CD ?


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in . o

c . ia

d o

n . w w

w

(D) None of the above.

MCQ 2.1.66

Consider the logic circuit shown below.

Using NOR gates only, the circuit can be realised as


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i. n

i d

o n

. w w

o c . a

w MCQ 2.1.67

Which of the following represent the correct realization of the given circuit using NAND gate only ?


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in . o

c . ia

MCQ 2.1.68

d o

n . w w

The logic operations of two combinational circuits given in Figure - I and Figure - II are

w

(A) Entirely different

(B) Identical

(C) Complementary

(D) Dual

***********


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EXERCISE 2.2

QUES 2.2.1 IES EC 2003

QUES 2.2.2 IES EC 2006


The minimum number of NAND gates required to implement the Boolean function A + AB + ABC is _____

i. n

The Boolean expression Y (A, B, C ) = A + BC is to be realized using 2-input gates of only one type. The minimum number of gates required for the realization is _____

o c . a

i d

QUES 2.2.3

The number of different sets of input conditions that produces a high output from a five-input OR gate is _____

QUES 2.2.4

A Boolean function of two variables X and Y is defined as follows : F (0, 0) = F (0, 1) = F (1, 1) = 1; F (1, 0) = 0 Assuming complements of X and Y are not available, a minimum cost solution for realizing F using 2-input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of _____ unit.

o n

. w w

w QUES 2.2.5

To implement Y = ABCD using only two-input NAND gates, minimum number of requirement of NAND gates is _____

QUES 2.2.6

In circuit shown below, for what input at the terminal A the output is X = 1 ?

QUES 2.2.7

If X = 1 in logic equation [A + Z {Y + (Z + XY )}][{X + Z (X + Y)} = 1 then Z is _____


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QUES 2.2.8

The minimum number of NOR gates required to implement A (A + B ) (A + B + C ) is equal to ______

QUES 2.2.9

In the following circuit the output Z is _____

QUES 2.2.10

The number of distinct Boolean expressions of 4 variables is _____

QUES 2.2.11

The number of duals of distinct Boolean expressions of 4 variables is _____


QUES 2.2.12

in . o

c . ia

To implement Y = ABCD using two-input NAND gates and NOR gates, minimum number of requirement of gates is _____

d o

n . w w

***********

w


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EXERCISE 2.3

MCQ 2.3.1 K SHASHIDHAR 214/12



MCQ 2.3.4


The NAND gate can perform the invert function if the inputs are (A) Connected together (B) Left open (C) Either (A) or (B)

(D) None of these

i. n

o c . a

Which of the following gate corresponds to the action of parallel switches for the input ? (A) AND (B) NAND

i d

(C) OR

o n

. w w

(D) NOR

Which of the following gate corresponds to the action of series switches for the input ? (A) AND (B) NAND (C) OR

(D) NOR

w

K SHASHIDHAR 214/15


Which of the following gate is called universal gate ? (A) AND (B) OR (C) XOR

(D) NAND

In positive logic, (A) a HIGH = 1, a LOW = 0 (B) a LOW = 1, a HIGH = 0 (C) Only HIGHs are present (D) Only LOWs are present


The output of an AND gate is LOW (A) All the time (B) When any input is LOW (C) When any input is HIGH (D) When all inputs are HIGH


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The output of an OR gate is LOW when (A) All inputs are LOW (B) Any INPUT is LOW (C) Any input is HIGH (D) All inputs are HIGH




If a three-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH output? (A) 1 (B) 2 (C) 7

(D) 8

If a three-input OR gate has eight input possibilities, how many of those possibilities will result in a HIGH output? (A) 1 (B) 2 (C) 7

(D) 8

in . o

c . ia

The output of NOT gate is HIGH when (A) the input is LOW

d o

(B) the input is HIGH

n . w w

(C) power is applied to the gate’s IC (D) power is removed from the gate’s IC


w

The output of an AND gate with three inputs, A, B , and C , is HIGH when (A) A = 1, B = 1, C = 0

(B) A = 0 , B = 0 , C = 0 (C) A = 1, B = 1, C = 1 (D) A = 1, B = 0 , C = 1


The output of an OR gate with three inputs, A, B, and C , is LOW when (A) A = 0 , B = 0 , C = 0

(B) A = 0 , B = 0 , C = 1 (C) A = 0 , B = 1, C = 1 (D) All of the above


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If a three-input NAND gate has eight input possibilities, how many of those possibilities will result in a HIGH output?

(A) 1

(B) 2

(C) 7

(D) 8

K SHASHIDHAR 215/32


If a three-input XOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?

(A) 2 (B) 4 (C) 6

i. n

(D) 8

MCQ 2.3.15


o c . a

i d

A two-input NOR gate is equivalent to a

(A) (B) (C) (D)

negative-OR gate negative-AND gate negative-NAND gate none of the above

o n

. w w

w

MCQ 2.3.16

K SHASHIDHAR 215/34

The exclusive-OR gate’s output is HIGH if

(A) All inputs are low (B) all inputs are HIGH (C) the inputs are different (D) none of the above


The exclusive-NOR gate’s output is HIGH if (A) the inputs are the same (B) one input is High, and the other input is LOW (C) the inputs are different (D) none of the above


How many two-input NOR gates does it take to produce a twoinput NAND gate ? (A) 1 (B) 2 (C) 3

(D) 4


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MCQ 2.3.19 V K PURI 94/1

Boolean algebra can be used to (A) Simplify any algebraic expressions (B) Minimize the number of switches in a circuits (C) Solve the mathematical problems (D) Perform arithmetic calculations.

MCQ 2.3.20 V K PURI 95/13

De Morgan’s theorems state that (A) A + B = A.B and A.B = A.B . (B) A + B = A + B and A B = A.B . (C) A + B = A.B and A B = A + B (D) A + B = A + B and A.B = A + B

MCQ 2.3.21 V K PURI 95/16

The gate ideally suited for bit comparison is a (A) Two input Exclusive NOR gate

c . ia

(B) Two input Exclusive OR gate (C) Two input NAND gate (D) Two input NOR gate

MCQ 2.3.22 B.R. GUPTA 73/521

in . o

d o

n . w w

A buffer is (A) always non-inverting (B) always inverting

w

(C) inverting or non-inverting (D) none of above

MCQ 2.3.23

Symbol in figure given below is IEEE symbol for

B.R. GUPTA 83/522

MCQ 2.3.24 B.R. GUPTA 85/522

(A) AND

(B) OR

(C) NAND

(D) NOR

As per Boolean Algebra, inputs can be interchanged in (A) OR gates (B) AND gates (C) both OR and AND gates

(D) none of above


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MCQ 2.3.25 B.R. GUPTA 94/522


Digital Electronics

In which function is each term known as minterm (A) SOP (B) POS (C) Hybrid

MCQ 2.3.26 MAINI 1/102

MAINI 4/103

(D) Ex-NOR

i. n

In general, logic gates whose all output entries are logic ‘1’ except for one entry that is logic ‘0’ are (A) AND, OR

(D) NOR, AND

o n

. w w

o c . a

i d

(C) NAND, OR

MAINI 8/103


For a certain two-input logic gate, the output is ‘1’ for like inputs and ‘0’ for unlike inputs. The logic gate is (A) Ex-OR (B) NAND

(B) NAND, NOR

MCQ 2.3.28

Page 111 Chap 2

(D) both SOP and POS

(C) NOR

MCQ 2.3.27


A logic gate with four inputs can have (A) 16 possible input combinations (B) 4 possible input combinations

w

(C) 8 possible input combinations (D) None of these

MCQ 2.3.29 MAINI 4/200

MCQ 2.3.30 MAINI 5/200

The dual of a Boolean expression is A + B . The expression is (A) A : B (B) Al : B l (C) Al + B l (D) A + B

Complement of complement of Al : B + A : B l is (A) A : B + Al : B l (B) _Al + B i : _A + B li (C) Al : B + A : B l (D) None of these

MCQ 2.3.31

The operation A : A = (A) A 2

(B) 2A

(C) 1

(D) A


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MCQ 2.3.32 Chakravorty M4.10/111




The operation A + A = (A) A 2

(B) 2A

(C) 0

(D) A

The operation A + A = (A) 1

(B) A

(C) 0

(D) A

The operation A : A = (A) 1

(B) A

(C) 0

(A) A

The AND, OR, and NOT gates are called (A) universal gates

c . ia

(B) basic gates (C) hexadecimal gates (D) decimal number gates

MCQ 2.3.36

d o

n . w w

The gate shown in Fig. is an alternative symbol of

Chakravorty M6.6/171

w MCQ 2.3.37

in . o

(A) AND gate

(B) OR gate

(C) NAND gate

(D) NOR gate

The gate shown in Fig. is an alternative symbol of


(A) AND gate (B) OR gate (C) NAND gate (D) NOR gate


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MCQ 2.3.38


Digital Electronics


The gate shown in below is an alternative symbol of

Page 113 Chap 2

Chakravorty


M6.8/171

MCQ 2.3.39

(A) AND gate

(B) OR gate

(C) NAND gate

(D) NOR gate

The gate shown below is an alternative symbol of

i. n


(A) AND gate

i d

(B) OR gate (C) NAND gate

o n

(D) NOR gate

MCQ 2.3.40 MANDAL 1/72

. w w

o c . a

In a positive logic circuit, (A) Logic 0 and 1 represented 0 V (ground) and positive voltage _+ VCC i respectively

w

(B) Logic 0 and 1 represented by negative and positive voltages respectively (C) Logic 0 voltage level is higher than logic 1 voltage level (D) Logic 0 voltage level is lower than logic 1 voltage level


In negative logic, the logic 1 state corresponds to (A) Ground level (B) High voltage level (C) Negative voltage level (D) Low voltage level


A NAND gate is called a universal logic element because (A) All digital computers use NAND gates (B) All the minimisation techniques are applicable for optimum NAND gate realisation (C) Every body use this gate (D) Any logic function can be realised by NAND gates alone


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MCQ 2.3.43 MANDAL 17/73

Boolean algebra is different from ordinary algebra in which way ? (A) Boolean algebra can represent more than 1 discrete level between 0 and 1. (B) Boolean algebra have only 2 discrete levels : 0 and 1 (C) Boolean algebra can describe up to levels of logic levels (D) They are actually the same

MCQ 2.3.44 ANAND KUMAR 10/21

The voltage levels for positive logic system (A) must necessarily be positive (B) must necessarily be negative (C) may be positive or negative (D) must necessarily be 0 V and 5 V


in . o

Knowledge of binary number system is required for the designers of computers and other digital systems because (A) it is easy to learn binary number system

c . ia

(B) it is easy to learn Boolean algebra (C) it is easy to use binary codes

d o

(D) the devices used in these systems operate in binary


n . w w

Which of the following statements is true ? (A) OR and NOT gates are necessary and sufficient for realization of any logic function.

w

(B) AND and NOT gates are necessary and sufficient for realization of any logic function. (C) NAND gates are not sufficient to realize any logic function. (D) NOR gates are sufficient to realize any logic function.

MCQ 2.3.47

For the gate shown in the figure, the output will be HIGH

(A) if and only if both inputs are HIGH (B) if and only if both the inputs are LOW (C) if one of the inputs is LOW (D) if one of the inputs is HIGH


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In a digital computer binary subtraction is performed (A) in the same way as we perform subtraction in decimal number system (B) using 2’s complement method


(C) using 9’s complement method (D) using 10’s complement method


ANAND KUMAR 65/138

(D) AND, OR, and NOT

o c . a

Which of the following operations is commutative but not associative ? (A) AND (B) NOR (C) OR

MCQ 2.3.51

i d

o n

. w w

(D) X-OR

A + AB + ABC + ABCD + ABCDE + ... = (A) 1 (B) A (C) A + AB

(D) AB

w


MCQ 2.3.53

A + AB + A BC + A B C D + .... = (A) A + B + C + ...

(B) A + B + C + D + ...

(C) 1

(D) 0

The number of table entries needed for a five input logic circuit is (A) 4 (B) 8 (C) 16


i. n

(C) NOR

MCQ 2.3.50

ANAND KUMAR 1/192

The most suitable gate to check whether the number of 1s in a digital word is even or odd is (A) X-OR (B) NAND

(D) 32

The dual of a Boolean expression is obtained by (A) interchanging all 0s and 1s (B) interchanging all 0s and 1s, all + and ‘:’signs (C) interchanging all 0s and 1s, all + and ‘:’ signs and complementing all the variables (D) interchanging all + and ‘:’ signs and complementing all the variables


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The complement of a Boolean expression is obtained by (A) interchanging all 0s and 1s (B) interchanging all 0s and 1s, all + and ‘:’ signs (C) interchanging all 0s and 1s, all + and ‘:’ signs and complementing all the variables (D) interchanging all + and ‘:’ signs and complementing all the variables

MCQ 2.3.56 SEDHA 7/118

All Boolean expressions can be implemented with (A) NAND gates only (B) NOR gates only (C) combinations of NAND and NOR gates (D) Any of these

MCQ 2.3.57

in . o

Which of the following logic gates will have an output of 1 ?

c . ia

d o

MCQ 2.3.58 SEDHA 1/183

MCQ 2.3.59 SEDHA 15/184

MCQ 2.3.60 KHARATE 7/197

n . w w

w

Boolean algebra is essentially based on (A) symbols (B) logic (C) truth

(D) numbers

X + XY is reduced to (A) X

(B) X + Y

(C) X + Y

(D) X + Y

A carry look ahead adder is frequently used for addition, because it (A) is faster (B) is more accurate (C) uses fewer gates

(D) costs less

***********


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SOLUTIONS 2.1

SOL 2.1.1


Correct option is (B). From the Boolean properties, we know that

i. n

o c . a

So, its equivalent logic will be

i d

o n

i.e. AND-Invert = Invert-OR By converting AND Invert logic to equivalent Invert-OR logic in the given circuit diagram, we get

. w w

w

So, the output Z is Z = AB + CD + EF ALTERNATIVE METHOD :

Expression of output can be directly obtained from given circuit as Z = _AB i_CD i_EF i Using De-Morgan’s theorem, we have Z = AB + CD + EF

SOL 2.1.2

Correct option is (D). From the Boolean properties, we know that


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So, its equivalent logic will be

i.e. AND-Invert = Invert-OR Applying the property, we have the modified logic circuit as

in . o

c . ia

d o

So, the output X is

X = MNQ + MNQ + M NQ

n . w w

w SOL 2.1.3

= MQ _N + N i + M NQ = MQ + M NQ = Q _M + M N i = Q _M + N i

Correct option is (A). We convert the AND-Invert logic to equivalent Invert-OR logic as

or


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So, the output Z is given as Z = AB + E _C + D i

SOL 2.1.4

i. n

o c . a

Correct option is (C). By using the Boolean properties, we minimize the given Boolean expression as

_X + Y i_X + Y i_X + Y i = _X + Y i_X : X + XY + X Y + Y : Y i

o n

i d

SOL 2.1.5

. w w

= _X + Y i_XY + X Y i = XY + XY = XY

Correct option is (D). From the given logic diagram, expression of the output can be written as

w

Z = A + _AB + BC i + C = A+A+B+B+C+C = A+B+C 4 = ABC From the above logic function, we can observe that options (A) and (B) are matched. Now, we check the expression given in option (C).

Z = AB + BC + AC = A+B+B+C+A+C = A+B+C Hence, all the options are same, and equal to the output Z of the given logic circuit.

SOL 2.1.6

Correct option is (B). Given that AB + AC + BC = AB + AC From Consensus Theorem, when a particular variable is associated with some variable and it’s complement is associated with another variable and next term is formed by the leftover variables, then the last term becomes redundant.


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AB + AC + BC S

Page 120 Chap 2

= AB + AC

redundant term


It’s dual also exists. Taking dual of the expression, we get

_A + B i_A + C i_B + C i = _A + B i_A + C i

Hence,

SOL 2.1.7

_A + C i_B + C i_A + B i = _A + B i_A + C i

Correct option is (A). Expression of output for the circuit is given by X = _A 5 B i : _A + B i = _AB + AB i_AB i = AB

SOL 2.1.8

Y = _A 5 B i : C

c . ia

= _AB + AB i : C = _AB + AB i + C = _AB + A B i + C = A B + AB + C

SOL 2.1.9

in . o

Correct option is (B). Expression of the output for the circuit is given by

d o

{Using De Morgan’s theorem} {A 9 B = A 5 B or A 5 B = A 9 B }

n . w w

Correct option is (C). Expression of the output Z for the circuit is given by Z = A : _A + A i : B : C = ABC

{A + A = 1}

Correct option is (A). Expression of the output Z for the circuit is given by Z = _A : B i : _B + C i = A : B : B + ABC = ABC

{B : B = 0 }

w SOL 2.1.10

SOL 2.1.11

Correct option is (A). The expression of the output Z for the circuit is given by Z = _A + B i : BC {Using De-Morgan’s theorem} = AB : BC = ABC


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SOL 2.1.12

Digital Electronics


Correct option is (C). Expression for X from given table is obtained by writing logic for X corresponding to 0 output. i.e. X = A BC + ABC = _A + Ai BC = BC

SOL 2.1.13


{A + A = 1}

Correct option is (A). Given expression is A + BC . Using distributive law, we have A + BC = _A + B i_A + C i This law states that ANDing of several variables and ORing the result with a single variable is equivalent to ORing that single variable with each of the several variables and then ANDing the sums. It can be verified from the table below.

i. n

SOL 2.1.14

A+C

_A + B i_A + C i

A + BC

0

0

0

1

0

0

0

0

0

1

1

1

1

A

B

C

A+B

0

0

0

0

0

0

1

o n 0

. w w

w

i d

o c . a

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

0

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

Correct option is (B). The expression of Z from given truth table can be written for logic 1 or indirectly we can solve for Z and then take complement. The expression for Z is given by , writing logic expression for 0 output as, Z = A BC Taking complement, we get {Using De-Morgan’s theorem} Z = Z = A BC or Z = A+B+C Now, we check the result for the given options. From expression given in option (B), we get same minimized result. _A + B i_B + C i = _A + B i + _B + C i

= A+B+C


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Page 122 Chap 2

SOL 2.1.15


Correct option is (A). From truth table, the expression of the function f is given by f = ABC + ABC = B _AC + AC i = B _A + C i_A + C i

SOL 2.1.16

Correct option is (D). The given Boolean expression is rewritten as or

AC + BC = AC _B + B i + BC _A + A i AC + BC = ABC + ABC + ABC + ABC

SOL 2.1.17

Correct option is (D). The given expression is A + AB + A BC + A B C D + A B C DE On simplification of the expression using Boolean algebra, we get A + AB + A BC + A B C D + A B C DE

in . o

c . a

= A + A 8B + B #C + C _D + DE i-B Using redundant literal rule, we have

...(1)

i d

A + AB = A + B or A + A _B + C i = A + B + C Applying this rule in equation (1), we get

o n . w w

A + AB + A BC + A B C D + A B C DE

w SOL 2.1.18

= A + A 7B + B #C + C _D + E i-A = A + A #B + B _C + D + E i= A + A _B + C + D + E i = A+B+C+D+E

Correct option is (B). Given logic function is

Y = A #B + C _AB + AC iOn simplification, we get

Y = AB + AC 7_A + B i_A + C iA = AB + AC _A + A C + A B + B C i = AB

SOL 2.1.19

Correct option is (D). Given logic expression is Y = _AB i : _AB i On simplification by using Boolean algebra, we get


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Y = _AB i : _AB i (Using De-Morgan’s theorem) = _A + B i_A + B i = _AA + A B + AB + BB i = A B + AB

SOL 2.1.20


Correct option is (B). Given that Z = XY + XY So, we simplify the given function as XZ + X Z = X _XY + XY i + X _XY + XY i = X _XY + X Y i + XY = XY + XY

o c . a

= Y _X + X i =Y

SOL 2.1.21

Correct option is (A). Given that XY = 0 Since, we know that

i d

o n

. w w

i. n

X 5 Y = XY + XY

X5Y = X9Y So, by using the given condition, we get

w or

SOL 2.1.22

X 5 Y = XY + XY = _XY + X Y i X5Y = X Y = X+Y

(XY = 0 )

Correct option is (C). Rearranging the given expression, we get

Z = 7A + EF + BC + DA7A + D E + BC + D F A = 7A + BC + EF + DA7A + BC + D _E + F iA

= 7_A + BC i + _EF + D iA7_A + BC i + _D + EF iA Let A + BC = X and EF + D = Y So, we may write Z = _X + Y i_X + Y i = X + XY + XY = X 71 + Y + Y A =X = A + BC

Given that A = 0 , then Z = BC


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Page 124 Chap 2

SOL 2.1.23


Correct option is (C). There are Four inputs (let A, B , C , D ) to a OR gate. So, we have Total no. of input conditions = 2 4 = 16 Now, the output of OR gate is given by Z = A+B+C+D i.e. the output is High, if any one out of 4 input is high; and output will Low, only for one condition (0 0 0 0). Thus, output will high for 15 input conditions.

SOL 2.1.24

Correct option is (C). The expression for the output of given circuit is F = 7_A + B i + A + _A + B iA : 7_A + B i + A A Let A + B = X and A + _A + B i = Y So, the expression for output can be minimized as

in . o

F = _Y + X i Y = Y + XY = Y _1 + X i = Y

= A + _A + B i = A : _A + B i = AA + AB = AB Thus, we may conclude that F = 1 for A = 0 and B = 1

c . ia

d o

SOL 2.1.25

n . w w

Correct option is (A). We check the given requirements for the circuits given in the options. Consider the circuit of option (A).

w

1. For B = C : P = B5C = 0 and X = A+0 = A i.e. Output X will equal A when control input B and C are the same. 2. For B ! C : P = B5C = 1 and X = A+1 = 1 i.e. X will remain HIGH when B and C are different. Hence, the circuit satisfies both the requirements.


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SOL 2.1.26


Digital Electronics


Correct option is (A). We check the circuits in given option for the required condition. The output of the logic circuit will be high only when both inputs of last AND are high. Now, we have the two conditions: 1. Given that A and B are both High. For A and B as logic High, one input of last AND gate is high for the circuits given in options (A) and (B). 2.


Given that C and D are either both LOW or both HIGH. For the circuit given in option (A), if C and D inputs are either both high or both low, i.e. C = D applied to XNOR gate then C 9 D = 1 for C = D i.e. another input of last AND gate will be High.

i. n

Thus, the circuit given in option (A) is HIGH whenever A and B are both HIGH as long as C and D are either both LOW or both HIGH.

SOL 2.1.27

o c . a

i d

Correct option is (D). Consider a 2-input OR gate shown below.

o n

. w w

Now, we check the correctness of the given two statements. 1. Given that output waveform _X i is same as the any one input (let A). For this condition, we may have the following two state diagrams.

w

From the above state diagram, we may observe that it is not necessary that B should be permanently Low to satisfy the required condition. Therefore, statement-1 is False. 2.

Given that output wave form _X i is always high. Again, we may draw the state diagram for the condition.


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From the above state diagram, we observe that it is not necessary that any one input should be permanently high. Therefore, statement-2 is False.


SOL 2.1.28

Correct option is (A). Given Boolean function is Z = ABC To obtain the Boolean expression in form of NAND gate output and NOR gate output, we rewrite the expression as Z = ABC = ACB = AC + B Let AC = D then Z = D+B Therefore, one NAND gate and one NOR gate is required to implement the Boolean function as shown below.

in . o

c . ia

Hence, the minimum cost for the implementation is 2 units.

SOL 2.1.29

d o

n . w w

Correct option is (C). Given Boolean function,

Z = ABC To implement the function using using only NAND gates, we draw the logic circuit as

w

Now, we convert each gate to its NAND implementation.

Thus, the minimum cost for implementation of the function using NAND gate will be 5 units.


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SOL 2.1.30


Digital Electronics


Correct option is (D). For the LED circuit, we know the following points: 1. Output of NAND gate must be Low for LED to emit light. 2.

Both inputs to NAND must be High for Low output.

3.

If any one of the switches is closed, output of AND gate will be Low.

4.

If Both switches are open, output of XOR gate will be Low.


So there can not be both input High to NAND. Therefore, LED does not emit light irrespective of the switch positions.

SOL 2.1.31

i. n

Correct option is (D). For the given circuit, we have Output of 1 st XOR = X : 1 + X : 1 = X Output of 2 nd XOR = X 5 X = X X + XX = 1 rd Output of 3 XOR = 1 5 X and so on. = X:1+X:1 = X Hence, after 2, 4, 6, 8, .......20 XOR (i.e. even number of XOR gates), output will be 1.

i d

o n

SOL 2.1.32

. w w

o c . a

Correct option is (C). For the given network, we obtain Output of gate 1 = X0 X1

w

Output of gate 2 = X0 X1 + X2 Output of gate 3 = _X0 X1 + X2i X3 = X0 X1 X3 + X2 X3 Similarly, we may deduce Output of gate 4 = X0 X1 X3 + X2 X3 + X4 Output of gate 5 = _X0 X1 X3 + X2 X3 + X4i X5 = X0 X1 X3 X5 + X2 X3 X5 + X4 X5 Hence, the output of gate n would be F = X0 X1 X3 X5 .........Xn + X2 X3 X5 .........Xn + X4 X5 X7 ..........Xn + ........ + Xn - 1 Xn

SOL 2.1.33

Correct option is (C). Given that G1 has delay of 10 ns and G2 has delay of 20 ns. Let output of G1 is X . So, we get the output waveform for the given circuit as shown below.


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SOL 2.1.34

Correct option is (D). From the circuit diagram, we have X = PQ Y = P+Q

and

and Hence,

SOL 2.1.35

in . o

c . ia

Z = X : Y = _PQ i_P + Q i = _P + Q i_P + Q i = PQ + PQ = P 5 Q M1 = Z 5 R

d o

M1 = _P 5 Q i 5 R M1 = _P XOR Q i XOR R

n . w w

Correct option is (A). XOR logic using 2-input NAND gates is implemented as

w

Now, we may prove that the above logic circuit implements an XOR gate Z = $_XY i X . : $_XY i Y . = _XY i X + _XY i Y = _X + Y i X + _X + Y i Y = XY + XY = X 5 Y Thus, 4 NAND gates are required


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SOL 2.1.36

SOL 2.1.37


Digital Electronics

Correct option is (A). In negative logic system, Low-level or more negative represent the logic 1 and HIGH level or less negative represent the logic 0, as illustrated in figure below.


i. n

Correct option is (D). In positive logic system Low-level or more negative represents the logic 0 and HIGH level or less negative represents the logic 1.

. w w

o c . a

i d

o n

SOL 2.1.38


Correct option is (C). Ex-OR gate output is given by

w

(A and B are inputs) Y = A5B = AB + AB To make inversion of a input using XOR gate, we consider one input, let A. So, we must have the output Y =A For the required output, we should take another input at logic 1 (High). i.e. Y = A:1+A:1 = A

SOL 2.1.39

Correct option is (B). We know that, XOR output is logic 1 when both inputs are not equal and logic 0 when both inputs are same. Hence, we have A 5 B = 0 for A = B i.e. (a " 2 ) and _d " 1i A 5 B = 1 for A ! B Again, XNOR output become logic 0, if any one input of XNOR is logic 1 (high), i.e. i.e. _b " 3i A + B = 0 for A = 1 or B = 1 or A = B = 1 Also, we have i.e. _c " 4i A : B = 0 for A = 1 or B = 0 Therefore, the correct match in the list is (a " 2 ), _b " 3i , _c " 4i , _d " 1i


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Page 130 Chap 2

SOL 2.1.40


Correct option is (A). A NAND gate output can be expressed as Y = A : B = A + B = A OR B So, NAND gate is equivalent to an OR gate with its inverted inputs.

Again, the NOR gate output can be expressed as Y = A + B = A : B = A _ANDi B Hence, NOR gate is equivalent to an AND gate with its inverted input.

in . o

Therefore, statements (1) and (2) are correct.

SOL 2.1.41

c . ia

Correct option is (B). For given logic circuit, expression for output X is

X = _A + B i : B = _A + B i + B = Â + B h + B = A + B Output waveform for the given input waveforms is

d o

n . w w

w


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SOL 2.1.42

Digital Electronics


Correct option is (C). The expression of the output for the given logic circuit is


X = AB + A B = A 9 B So, we may conclude that X = A 9 B = 1 for A = B = 0 for A ! B Therefore, we obtain the output waveform for the given input waveforms as

i. n

i d

o n

SOL 2.1.43

. w w

w

o c . a

Correct option is (D). The expression of the output for the given logic circuit is X = _A + B i + B = _A + B i : B

= _A : B i : B =0 Hence, the output for the circuit will remain zero irrespective of the input.

SOL 2.1.44

Correct option is (C). According to the given problem, we represent the fruits as A = apple; B = banana; M = Mango; O = orange So, the logical expression that specifies the fruit available for desert is f _A, B, M, O i = _1st Choicei + _2nd Choicei + _3rd Choicei = _O + A + OAi + _MAi + _OB i = _A + O i + MA + BO = A _1 + M i + O _1 + B i = A+O


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Page 132 Chap 2

SOL 2.1.45

Correct option is (C). The wired AND in open-collector is given by


Since, for the given circuit, we have C = A and D = B Hence, the output of the circuit is given as F = AB : A B = AB + AB = A 5 B = A _XOR i B

SOL 2.1.46

in . o

Correct option is (C). Given Boolean expression is _w + x i_w l + x + yz li_w + y li On simplification, we obtain _w + x i_w l + x + yz li_w + y li = _w l + x + yz li_w + xy li = ww l + w l xy l + xw + xxy l + yz l w + yz l xy l = w l xy l + xy l + xw + yz l w

c . ia

d o

SOL 2.1.47

n . w w

= _w l + 1i xy l + w _x + yz li = xy l + wx + wyz l

w

Correct option is (A). The elevator door will open in the following two cases. Case 1: If the elevator is stopped, it is level with the floor, and the timer has not expired. Since, we have the representations Elevator is stopped = S ; Level with the floor = F ; Time has not expired = T l So, the given condition is expressed as X1 = SFT l Case 2: If the elevator is stopped, it is level with the floor, and a button is pressed. Again, we have the representations Elevator is stopped = S and Level with the floor = F and Button is pressed = B So, the given condition is expressed as


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X2 = SFB Since, the door will be open is case-1 or case-2. Therefore, we may express the condition for elevator door to be open as D = X1 OR X2 D = SFT l + SFB

or

SOL 2.1.48


Correct option is (D). Given logic circuit is

i. n

o c . a

i d

So, the output Z is given by

Z = X + X + Y = X : X + Y = X : _X + Y i = X + XY = X _1 + Y i = X = X In option (D), the circuit provides the output X as shown below.

o n

. w w

Hence, the circuit given in option (D) is minimized form of the logic circuit.

w SOL 2.1.49

Correct option is (B). We redraw the given logic circuit as

Output Z of the logic circuit is Z = AB C D + ABCD + A D


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GATE STUDY PACKAGE Electronics & Communication 10 Subject-wise books by R. K. Kanodia General Aptitude Engineering Mathematics Networks Electronic Devices Analog Electronics Digital Electronics Signals & Systems Control Systems Communication Systems Electromagnetics = AD ^B C + BC h + A D

Page 134 Chap 2

= AD _B 9 C i + A D


= AD _B 5 C i + A D

SOL 2.1.50

Correct option is (D). Given Boolean expression is AD + ABCD + ACD + AB + AC D + A B On minimization using Boolean algebra, we get AD + ABCD + ACD + AB + AC D + A B = AD _1 + BC + C + C i + AB + A B

= AD + AB + A B

= AD + A _B + B i = AD + A = _A + A i_D + A i = A + D

in . o

NOTE :

Here, it must be noted that, we got first the expression ÂD + A h , and this is also given in option (B). At first glance it seems to be Answer but it is not. It can be minimized further into Â + D h .

SOL 2.1.51

c . ia

Correct option is (C). We redraw the given digital circuit as

d o

n . w w

w

Output Y is given by

Y = AB + AB = A 5 B = A _XOR i B

SOL 2.1.52

Correct option is (A). We have the switching circuit as


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Now, we consider the parallel switches as shown below.


The logic expression for parallel switches is obtained as L = A+B Again, we consider the series connected switches

i. n

o c . a

i d

o n

The logic expression for series connected switches is

. w w

L = A:B Hence, the logic expression for given circuit is

SOL 2.1.53

L = _A + B i : _C + D i : E

w

Correct option is (A). We have to check the correctness of each options. Option (A) On minimizing L.H.S. of the equation, we have or

X + XY = _X + X i_X + Y i = X + Y ! X X + XY ! X

Option (B) On minimizing L.H.S. of the equation, we have X _X + Y i = XX + XY = XY X _X + Y i = XY

or Option (C) On minimizing L.H.S. of the equation, we have X + XY = X _1 + Y i = X X + XY = X

or Option (D) On minimizing L.H.S. of the equation, we have or

ZX + ZXY = Z _X + XY i = Z _X + Y i = ZX + ZY ZX + ZXY = ZX + ZY


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Page 136 Chap 2

SOL 2.1.54

Correct option is (D). We have the switching circuit diagram as


in . o

From the circuit diagram, we deduce that LED will glow when Z = Low _ 0 i , and Z will be low only when X or Y or both will be High. Now, we consider the different input conditions as 1. For A = B = 1,

c . ia

X = 1 and Y = 0 & Z = 0 ; LED glows 2.

For A = B = 0 ,

3.

X = 0 and Y = 1 & Z = 0 ; LED glows For A = 0 , B = 1;

d o

n . w w

4.

X = 0 and Y = 0 & Z = 1; LED doesn’t glow For A = 1, B = 0 ; X = 0 and Y = 0 ( Z = 1; LED doesn’t glow

SOL 2.1.55

w

Correct option is (C). We have the Boolean identity

AB + AC = _A + C i_A + B i Dual form of any identity can be found by replacing all AND function to OR and vice-versa. Hence, dual form of the expression is given as _A + B i : _A + C i = _A : C i + _A : B i

SOL 2.1.56

Correct option is (D). Dual form of any identity can be found by replacing all AND functions to OR functions and vice-versa. Now, we have the Boolean expression as A + 7B + _AC iA + D So, the dual form of the expression is given as or

A : 7B : _A + C iA : D A 7B _A + C iA : D


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SOL 2.1.57


Digital Electronics


Correct option is (B). We have the Boolean expression as


Z = x 5 y 5 xy On minimizing the expression, we have

Z = x 5 7y 5 xyA = x 5 7yxy + yxyA = x 5 7y _x + y i + 0A = x 5 7yx + 0A = x : yx + x : yx = x _y + x i + xy = x + xy + xy = x _1 + y i + xy = x + xy

i. n

= x+y

SOL 2.1.58

Correct option is (C). We have the Boolean expression as

o c . a

i d

_X + W i_Y 5 Z i + XW l On simplification and minimization of the Boolean expression, we get _X + W i_Y 5 Z i + XW l = _X + W i_YZ l + Y l Z i + XW l = XYZ l + XY l Z + WYZ l + WY l Z + XW l From consensus theorem, we have

o n

. w w

AB + AC + BC = AB + AC So, eliminating the redundant term in the expression, we get

w

i.e. the minimized expression WY l Z + XW l + WYZ l

SOL 2.1.59

of

_X + W i_Y 5 Z i + XW l

is

Correct option is (B). We have the Boolean expression

F = _x + y i_x + y li On simplification, we get the expression Fsimplified = x + xy l + xy + yy l

...(1)

= x _1 + y l + y i ...(2) =x Hence, the logic diagram for the expression (1) and (2) is shown below.


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SOL 2.1.60

Correct option is (C). To get output at High state, i.e. to stop the Machine operation; either P is low (no paper in paper feeder) or Q and R are high (jam in paper path). Hence, logic expression for output S is

in . o

S = P+Q:R So, the logic circuit for the given condition is drawn as

c . ia

d o

SOL 2.1.61

n . w w

w

Correct option is (B). We redraw the given logic circuit as

DRIVE is active-HIGH, and it will go high only when X =Y=0 X will be LOW only when either A8 and A9 is HIGH.


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Y will be LOW only when W = 0 and A7 = 0 W will be LOW only when A0 through A6 are all HIGH. Putting this all together, we have the condition for DRIVE to be high as


A0 = A1 = A2 = A3 = A4 = A5 = A6 = 1 A7 = 0 A8 or A9 or both are 1

and either

SOL 2.1.62

Page 139 Chap 2

Correct option is (A). We have the wired-OR logic circuit as shown below.

i. n

o c . a

o n

i d

For the logic circuit, the output is

SOL 2.1.63

. w w

Y = _A + B i + _C + D i

Correct option is (C). We have the two level AND-OR gate as shown below.

w

Now, all the gates are replaced by NOR gate. So, we get the modified circuit as

Hence, the output of the modified network is Z = _A + B i + _C + D i = _A + B i : _C + D i = dual of F = F D


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SOL 2.1.64


Correct option is (C). The output function for the given circuit is f = xyz + wyz + wxz Let y = A; x = B ; w = C then f = Z _AB + AC + BC i Using consensus theorem, we conclude that BC term is redundant. So, we have f = Z _AB + AC i or f = xyz + wyz Hence, gate 3 is redundant.

SOL 2.1.65

Correct option is (B). We have the logic circuit as shown below

in . o

c . ia

d o

n . w w

From the Boolean algebra, we have

w

By using the above conversion, we redraw the given logic circuit as

Hence, the output of the logic circuit is Y = P+Q+R+S


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SOL 2.1.66

Digital Electronics


Correct option is (A). All the given circuit in the options include NOR gate. So, we implement the given expression using NOR gate as


X = AB + CD = (A + B ) (C + D ) = (A + B ) + (C + D )

i. n

SOL 2.1.67

i d

o n

. w w

o c . a

Correct option is (B). In order to convert the given circuit into all NOR, we apply the bubbles at the input terminals of gates as shown below.

w


and

Therefore, by using the above conversion, we get the logic circuit with NOR gates.


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SOL 2.1.68


Correct option is (D). In order to convert the given circuit using only NAND gate, we apply bubbles at the input terminal of each gates as shown below.


and

in . o

c . ia

Therefore, by using the above conversion, we get the logic circuit with NAND gates as

d o

n . w w

w SOL 2.1.69

Correct option is (A). Figure I We have the combinational circuit in Figure - I as

So, the output of the circuit is F1 = X + (X + Y ) = X (X + Y ) = X X + XY = XY Figure II We have the combinational circuit in Figure - II as


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So, the output of the circuit is F2 = X $ Y Hence, we have F1 ! F2 i.e. the output of the given two circuits are entirely different.

***********

i. n

i d

o n

. w w

o c . a

w


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SOLUTIONS 2.2


SOL 2.2.1

Correct answer is 0. Given Boolean function is

F = A + AB + ABC = A _1 + B + BC i = A Therefore, no gate is required to implement this function.

SOL 2.2.2

Correct answer is 3. As the given expression is to be realized using one type of 2-input gates. So, we may use universal gates (NAND, NOR) for realization. Now, we implement the given function using NAND and NOR gates. 1. NAND Implementation: For NAND implementation, we rewrite the given expression

in . o

c . ia

Y = A + BC = A + BC = _A i : _BC i So, the logic circuit can be implemented as

d o

n . w w

w

2. NOR Implementation: For NOR implementation, we rewrite the given expression as [Distributive Y = A + BC = _A + B i_A + C i ; property] or

Y = _A + B i_A + C i = _A + B i + _A + C i

Thus, to implement given circuit, minimum 3 gates are required.


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SOL 2.2.3

SOL 2.2.4

Digital Electronics


Correct answer is 31. We know that, if any one input of the OR gate becomes high logic (1), OR gate gives the high logic (1) output. The output is High only for the case when all the inputs are at Low logic (0). Now, for 5-inputs, we have Total number of input conditions = 2 5 = 32 Out of the 32 conditions, all inputs are zero (0) for only one condition. i.e. for only one condition the output is low. Hence, 31 input conditions produce the high output from a five-input OR gate.


i. n

Correct answer is 2. The Boolean function of two variables x and y are defined as f _0, 0i = f _0, 1i = f _1, 1i = 1 and f _1, 0i = 0 For the Boolean function, we obtain the truth table as x

y

f

0

0

1

0

1

1

0

1

1

i d

o n

. w w

1

o c . a

0 1

From the truth table, we define the function f as f = xy So, f = xy = x + y Hence, the function _ f i can be implemented using 2 input NOR and 2-input OR gate as shown below.

w

Thus, the total cost for the logic circuit will be 2 units.

SOL 2.2.5

Correct answer is 6. The circuit is as follows


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SOL 2.2.6


Correct answer is 011. For given logic circuit, output X = 1, if all inputs to AND gate are High. The output for the circuit can be expressed as X = _A 5 B i : _B 9 C i : C Also, we have A 5 B = 1 if A ! B and B 9 C = 1 if B = C Hence, for X = 1, the required conditions are C must be High B =C=1 A =0

SOL 2.2.7

(since A ! B )

Correct answer is 0. Given the logic equation,

in . o

7X + Z #Y + _Z + XY i-A#X + Z _X + Y i- = 1 and X =1 So, by substituting X = 1 and X = 0 in the logic equation, we get

c . ia

71 + Z #Y + _Z + 1Y i-A : 80 + Z _1 + Y iB = 1 71A8Z _ 1 iB = 1

or Hence, we have

SOL 2.2.8

Z = 1 or Z = 0

d o

n . w w

Correct answer is 0. Given logic expression is A _A + B i_A + B + C i On solving the expression, we have

w

A _A + B i_A + B + C i = _AA + AB i_A + B + C i = _A + AB i_A + B + C i = A + AB + A : AB + A : B : B + AC + ABC = A + AB + AC + ABC = A _1 + B + C + BC i = A Therefore, no gate is required to implement this function.

SOL 2.2.9

Correct answer is 1. From the given circuit, we can observe that input to last XNOR gate is same. So, the XNOR output is given by (Let input is X ) Z = X:X+X:X = X+X = 1 i.e. the output will be High (logic 1), irrespective of the inputs A and B.


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SOL 2.2.10


Digital Electronics


Correct answer is 65536. n The number of distinct Boolean expressions of n variables is 2 2 . Since, we have n =4 Hence, the number of distinct Boolean expressions is


2 2 = 2 2 = 2 16 = 65536 n

SOL 2.2.11

4

Correct answer is 256. The number of duals of distinct boolean expressions of n variables is 2 2 . Since, we have n = 4 . Hence, the number of duals of distinct Boolean expressions is n-1

22

SOL 2.2.12

n-1

= 2 2 = 2 2 = 2 8 = 256 4-1

3

i. n

o c . a

Correct answer is 3. To implement the given function using NAND and NOR gates, we rewrite the given function as

i d

o n

Y = ABCD = ABCD = AB + CD So, the equivalent circuit for the Boolean function is

. w w

w

Therefore, two NAND gates and one NOR gate is required to implement the function Y = ABCD .

***********


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SOLUTIONS 2.3


SOL 2.3.1

Correct option is (A). NAND gate output Y = A : B Where, A and B are inputs, if inputs are connected together, i.e. A = B Y = A:A = A

SOL 2.3.2

Correct option is (C).

SOL 2.3.3

Correct option is (A).

SOL 2.3.4

Correct option is (D).

SOL 2.3.5


SOL 2.3.6

in . o

c . ia

d o

n . w w

w

Correct option is (B).

SOL 2.3.7


SOL 2.3.8

Correct option is (A). AND gate output Y = A : B : C If any one of the inputs is LOW then output becomes LOW. Output will HIGH only when all the inputs are HIGH. For 3-inputs, 8 input possibilities are there, out of which only one case has all inputs high.

SOL 2.3.9

Correct option is (C). OR gate output Y = A+B+C If any one input is HIGH, output will be HIGH. Output will be LOW


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only when all three inputs become LOW. Out of 8 input possibilities, seven cases have one or more inputs high results in HIGH.

SOL 2.3.10


SOL 2.3.11


SOL 2.3.12


SOL 2.3.13

Correct option is (C)

SOL 2.3.14


SOL 2.3.15


o c . a

i d

Output of two input _A, B i NOR gate, Using De’morgan theorem, AND gate

w


i. n

o n

. w w

Page 149 Chap 2

Y = A+B Y = A:B =

negative-

SOL 2.3.16


SOL 2.3.17


SOL 2.3.18

Correct option is (D). Two-input NAND gate using two-input NOR gate is realized as :


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SOL 2.3.19


SOL 2.3.20


SOL 2.3.21

Correct option is (A). The Ex-NOR gate output is HIGH only when both input bits of it are equal. Hence, Ex-NOR gate is suitable for bit comparison.

SOL 2.3.22


SOL 2.3.23


SOL 2.3.24

Correct option is (C). AND : Y = A : B = B : A OR : Y = A + B = B + A


in . o

c . ia

d o

SOL 2.3.25

SOL 2.3.26

n . w w


w

Correct option is (D). The truth table for Ex-NOR gate is, Inputs

Output

A

B

Y = A9B

0

0

1

0

1

0

1

0

0

1

1

1

The output is ‘1’ for like inputs and ‘0’ for unlike inputs.

SOL 2.3.27

Correct option is (C). The truth table for NAND and OR is,


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Inputs


Page 151 Chap 2

Outputs

A

B

X = A:B

Y = A+B

0

0

1

0

0

1

1

1

1

0

1

1

1

1

0

1


For both NAND and OR gates, all output entries are logic ‘1’ except for one entry.

i. n

SOL 2.3.28


SOL 2.3.29


SOL 2.3.30

Correct option is (C). Taking of two times complement results the original function.

i d

o n

. w w

o c . a

Y = AB + AB

Complement of Y = Y = AB + AB

SOL 2.3.31

w

Complement of Y = Y = Y = AB + AB = AB + AB


SOL 2.3.32


SOL 2.3.33


SOL 2.3.34


SOL 2.3.35


SOL 2.3.36

Correct option is (C). Y = A + B = A $ B = NAND gate logic


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SOL 2.3.37

Correct option is (D). Y = A.B = A + B = NOR gate logic

Boolean Algebra and Logic Simplification SOL 2.3.38

Correct option is (B). Y = A.B = A + B = A + B = OR gate logic

SOL 2.3.39

Correct option is (A). Y = A + B = A $ B = AND gate logic

SOL 2.3.40


SOL 2.3.41


SOL 2.3.42


SOL 2.3.43


SOL 2.3.44


in . o

c . ia

d o

n . w w

w

SOL 2.3.45


SOL 2.3.46

Correct option is (D). NAND and NOR gates are universal gates. Any logic function can be realized using only NAND or only NOR gates. So, AND, OR and NOT gates are not necessary to realize any logic function.

SOL 2.3.47

Correct option is (B). X = A.B = A + B = NOR gate logic Hence, output will be HIGH if and only if both the inputs are low.


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SOL 2.3.48


Digital Electronics




SOL 2.3.49

Correct option is (A). When the no. of inputs in the XOR gate is even then output is ‘0’ and when the no. of inputs is odd then output is ‘1’.

SOL 2.3.50

Correct option is (B). NAND and NOR gates do not follow the associative property. Now check for NOR gate, (A + B ) + C is equal to or not equal to A + (B + C ) .

SOL 2.3.51


i. n

o c . a

(A + B ) + C ! A + (B + C ) (A + B ) + C ! A + (B + C )

or or

o n

i d

A + AB + ABC + ABCD + ABCDE + .... = A (1 + B + BC + BCD + BCDE + ...)

SOL 2.3.52

. w w

= A (1 + X) = A

w

Correct option is (A). A + AB + A BC + A B C D + ... = A + A (B + BC + BC D + ...) = A + A (X ) = (A + A) (A + X ) = A+X = A + B + BC + B C D + ... and so on. = A + B + C + ...

SOL 2.3.53

Correct option is (D). The number of combinations for five inputs is = 2 5 = 32 .

SOL 2.3.54


SOL 2.3.55


SOL 2.3.56



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SOL 2.3.57


Correct option is (C). Output of each option is (A) Y = 0.1 = 0

(B) Y = 0 + 1 = 1 = 0

(C) Y = 0 $ 1 = 0 = 1

(D) Y = 0 9 1 = 0

SOL 2.3.58


SOL 2.3.59


SOL 2.3.60


in . o

***********

c . ia

d o

n . w w

w


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