Digital Fundamentals Counters
1
Objectives •Describe the difference between an asynchronous and a synchronous counter •Analyze counter timing diagrams •Analyze counter circuits •Explain how propagation delays affect the operation of a counter •Determine the modulus of a counter •Modify the modulus of a counter •Recognize the difference between a 4-bit binary counter and a decade counter •Use an up/down counter to generate forward and reverse binary sequences •Determine the sequence of a counter • •Use IC counters in various applications •Design a counter that will have any specified sequence of states •Use cascaded counters to achieve a higher modulus •Use logic gates to decode any given state of a counter •Eliminate glitches in counter decoding •Explain how a digital clock operates •Troubleshoot counters for various types of faults •Interpret counter logic symbols that use dependency notation •Discuss mode selection in an SPLD •Apply a counter in a system application
2
Figure 9--1
A 2-bit asynchronous binary counter. Open file F09-01 to verify operation.
Figure 9--2 Timing diagram for the counter of Figure 9-1. As in previous chapters, output waveforms are shown in green.
Thomas L. Floyd Digital Fundamentals, 8e
3 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--3
Three-bit asynchronous binary counter and its timing diagram for one cycle. Open file F09-03 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e
4 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--4
Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.
Thomas L. Floyd Digital Fundamentals, 8e
5 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-5 Example 9-1: Four-bit asynchronous binary counter and its timing diagram. Open file F09-05 and verify the operation. Propagation delay is 10 ns for the flip-flops. Draw the timing diagram and determine the total propagation delay and the maximum clock frequency at which the counter can be operated.
Thomas L. Floyd Digital Fundamentals, 8e
t p ( tot ) = 4 ⋅10 ns = 40 ns 1 1 f max = = = 25 MHz t p (tot ) 40 ns
6 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--6
An asynchronously clocked decade counter with asynchronous recycling.
Thomas L. Floyd Digital Fundamentals, 8e
7 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-7 Example 9-2: Asynchronously clocked modulus-12 counter with asynchronous recycling.
Thomas L. Floyd Digital Fundamentals, 8e
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 0000 etc.
8 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--8 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.)
Figure 9--9 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.)
Thomas L. Floyd Digital Fundamentals, 8e
9 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-10 Example 9-3: Show how the 74LS93A can be connected as a modulus-12 counter.
Thomas L. Floyd Digital Fundamentals, 8e
10 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--11
A 2-bit synchronous binary counter.
Thomas L. Floyd Digital Fundamentals, 8e
11 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--12 equal).
Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be
Thomas L. Floyd Digital Fundamentals, 8e
12 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--13
Timing diagram for the counter of Figure 9-11. NO EXTRA DELAYS!
Thomas L. Floyd Digital Fundamentals, 8e
13 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--14
A 3-bit synchronous binary counter. Open file F09-14 to verify the operation.
Figure 9--15 Timing diagram for the counter of Figure 9-14.
Thomas L. Floyd Digital Fundamentals, 8e
000 001 010 011 100 101 110 111 000
14 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--16 A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.
Thomas L. Floyd Digital Fundamentals, 8e
15 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--17
A synchronous BCD decade counter. Open file F09-17 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e
16 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--19
The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)
Thomas L. Floyd Digital Fundamentals, 8e
17 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
18
19
Figure 9--20
Timing example for a 74HC163.
Thomas L. Floyd Digital Fundamentals, 8e
20 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--21
The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)
Thomas L. Floyd Digital Fundamentals, 8e
21 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
22
Figure 9--22
Timing example for a 74LS160.
Thomas L. Floyd Digital Fundamentals, 8e
23 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--23
A basic 3-bit up/down synchronous counter. Open file F09-23 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e
24 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-24 Example 9-4: Shot the timing diagram in the following situation:
Thomas L. Floyd Digital Fundamentals, 8e
Q 3210 0000 0001 0010 0100 0011 0010 0001 0000 1111 0000 0001 0010 0001 0000
UP
DOWN
UP DOWN 25
Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--25
The 74HC190 up/down synchronous decade counter.
Thomas L. Floyd Digital Fundamentals, 8e
26 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
27
Figure 9--26
Timing example for a 74HC190.
Thomas L. Floyd Digital Fundamentals, 8e
28 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Design of synchronous counters Figure 9--27
General clocked sequential circuit.
Thomas L. Floyd Digital Fundamentals, 8e
29 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--28
State diagram for a 3-bit Gray code counter.
STEP 1
Thomas L. Floyd Digital Fundamentals, 8e
30 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Next-State table Present state
STEP 2
Q 210 000 001 011 010 110 111 101 100
Next state
Q 210 001 011 010 110 111 101 100 000
31
Flip-flop transition table Output transitions
STEP 3
Q N N+1 0→0 0→1 1→0 1→1
Flip-flop inputs
Q J 0 1 X X
K X X 1 0
Q N: present state N+1: next state X: don’t care 32
Figure 9--29
Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.
STEP 4
Thomas L. Floyd Digital Fundamentals, 8e
33 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
STEP 5
From the K-maps:
J 0 = Q2Q1 + Q2 Q1 = Q2 ⊕ Q1 K 0 = Q2 Q1 + Q2Q1 = Q2 ⊕ Q1 J1 = Q2Q0 K1 = Q2Q0 J 2 = Q1 Q0 K 2 = Q1 Q0
34
Figure 9--30
Karnaugh maps for present-state J and K inputs.
Thomas L. Floyd Digital Fundamentals, 8e
35 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--31
Three-bit Gray code counter. Open file F09-31 to verify operation.
STEP 6
Thomas L. Floyd Digital Fundamentals, 8e
36 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Summary of steps: 1. Specify the counter sequence and draw a state diagram. 2. Derive a next-state table from the state diagram. 3. Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop. 4. Transfer the J and K states from the transition table to K-maps. There is a K-map for each input of each flip-flop. 5. Group the K-map cells to generate and derive the logic expression for each flip-flop input. 6. Implement the expressions with combinational logic, and combine with the flip-flops to create the counter. 37
Figure 9-32 Example 9-5: Design a counter with following state diagram:
Step 1 Present state
Q 210 001 Step 2 0 1 0 101 111 Thomas L. Floyd Digital Fundamentals, 8e
Next state
Q 210 010 101 111 001
Step 3
38 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--33
Thomas L. Floyd Digital Fundamentals, 8e
Step 4
39 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Step 5
J 0 = 1, K 0 = Q2 J 1 = K1 = 1 J 2 = K 2 = Q1
40
Figure 9--34
Step 6
Thomas L. Floyd Digital Fundamentals, 8e
41 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-35 Example 9-6: Develop a synchronous 3-bit u/d counter with a Gray code sequence.
STEP 2
STEP 1
STEP 3
42
Figure 9--36
J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.
STEP 4
Thomas L. Floyd Digital Fundamentals, 8e
43 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
STEP 5
44
Figure 9--37
Three-bit up/down Gray code counter.
STEP 6
45
CASCADED COUNTERS Figure 9--38
Two cascaded counters (all J and K inputs are HIGH).
Figure 9--39 Timing diagram for the cascaded counter configuration of Figure 9-38.
46
Figure 9--40
A modulus-100 counter using two cascaded decade counters.
Thomas L. Floyd Digital Fundamentals, 8e
47 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--41 100 outputs.
Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-
Thomas L. Floyd Digital Fundamentals, 8e
48 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-42 Example 9: Determine the overall modulus in the following cascaded counters
Solution 8x12x16 = 1536 10x4x7x5 = 1400
Thomas L. Floyd Digital Fundamentals, 8e
49 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-43 Example 9-8: Use 74LS160 counters to obtain a 10 kHz waveform from a 1 MHz clock. Solution: A divide-by-100 counter using two 74LS160 decade counters.
Thomas L. Floyd Digital Fundamentals, 8e
50 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--44 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).
Thomas L. Floyd Digital Fundamentals, 8e
51 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Counter decoding Figure 9--45
Decoding of state 6 (110). Open file F09-45 to verify operation.
Thomas L. Floyd Digital Fundamentals, 8e
52 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-46 Example 9-9: Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. counter with active-HIGH decoding of count 2 and count 7. Open file F09-46 to verify operation.
A 3-bit
53
Decoding glitches Figure 9-47
Figure 9--48 Outputs with glitches from the decoder in Figure 9-47. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.
A basic decade (BCD) counter and decoder.
Thomas L. Floyd Digital Fundamentals, 8e
54 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--49
The basic decade counter and decoder with strobing to eliminate glitches.
Figure 9--50
Thomas L. Floyd Digital Fundamentals, 8e
Strobed decoder outputs for the circuit of Figure 9-49.
55 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Application examples Figure 9--51 53.
Simplified logic diagram for a 12-hour digital clock. Logic details using specific devices are shown in Figures 9-52 and 9-
Thomas L. Floyd Digital Fundamentals, 8e
56 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--52 Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).
Thomas L. Floyd Digital Fundamentals, 8e
57 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--53
Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.
Thomas L. Floyd Digital Fundamentals, 8e
58 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--54
Figure 9--55
Functional block diagram for parking garage control.
Logic diagram for modulus-100 up/down counter for automobile parking control.
Thomas L. Floyd Digital Fundamentals, 8e
59 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--56
Parallel-to-serial data conversion logic.
Thomas L. Floyd Digital Fundamentals, 8e
Figure 9--57 Example of parallel-to-serial conversion timing for the circuit in Figure 9-56.
60 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Troubleshooting Figure 9--58
Example of a failure that affects following counters in a cascaded arrangement.
Thomas L. Floyd Digital Fundamentals, 8e
61 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--59
Example of a failure in a cascaded counter with a truncated sequence.
Thomas L. Floyd Digital Fundamentals, 8e
62 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-60 Example 9-10: Frequency measurements are made on the truncated counter (see below) as indicated. Determine if the counter is working properly, and if not, isolate the fault.
Solution: Check frequency at TC 4 ...
Thomas L. Floyd Digital Fundamentals, 8e
63 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9-61 Example 9-11: Determine if there is a problem with the counter
Thomas L. Floyd Digital Fundamentals, 8e
64 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Hands on tip When observing the time relationship between two digital signals with a dual-trace oscilloscope, trigger the scope with the slower signal (it has fewer possible trigger points!). Hence do not use clock signals for triggering (they are usually the fastest signal in the system).
65
Logic symbols with dependency notation Figure 9--62
The 74HC163 4-bit synchronous counter.
Thomas L. Floyd Digital Fundamentals, 8e
66 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--63
Combinational mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.
Thomas L. Floyd Digital Fundamentals, 8e
67 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--64
Registered mode for active-LOW and active-HIGH outputs. The red lines show the logic paths in each case.
Thomas L. Floyd Digital Fundamentals, 8e
68 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--65
Thomas L. Floyd Digital Fundamentals, 8e
69 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--66
Traffic light control system block diagram and light sequence.
Thomas L. Floyd Digital Fundamentals, 8e
70 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--67
Block diagram of the sequential logic.
Thomas L. Floyd Digital Fundamentals, 8e
71 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--68
State diagram showing the 2-bit Gray code sequence.
Thomas L. Floyd Digital Fundamentals, 8e
72 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--69
Sequential logic.
Thomas L. Floyd Digital Fundamentals, 8e
73 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
74
Figure 9--70
Thomas L. Floyd Digital Fundamentals, 8e
75 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--71
Thomas L. Floyd Digital Fundamentals, 8e
76 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--72
Thomas L. Floyd Digital Fundamentals, 8e
77 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--73
Comparison of asynchronous and synchronous counters.
Thomas L. Floyd Digital Fundamentals, 8e
78 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.
Figure 9--74 Note that the labels (names of inputs and outputs) are consistent with text but may differ from the particular manufacturer’s data book you are using. The devices shown are functionally the same and pin compatible with the same device types in other available TTL and CMOS IC families.
Thomas L. Floyd Digital Fundamentals, 8e
79 Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.