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Fan In and Fan Out are characteristics of Digital ICs. Digital ICs are complete functioning logic networks. Typically, Typically, a Digital IC requires only a power supply, I/ !input" and O/ !output". #ere are the definitions of Fan In an d Fan Out. Fan In$ The fan%in defined as the ma&imum num'er of inputs that a logic gate can accept. If num'er of input e&ceeds, the output will 'e undefined und efined or incorrect. It is specified 'y manufacturer and is pro(ided in the data sheet. Fan Out$ The fan%out is defined as the ma&imum num'er of inputs !load" that can 'e connected to the output of a gate without degrading the normal operation. Fan Out is calculated from the amount of current a(aila'le in the output of a gate and the amount of current needed in each input of the connecting gate. It is specified 'y manufacturer and is pro(ided in the data sheet. )&ceeding the specified ma&imum load may cause a malfunction 'ecause the circuit will not 'e a'le supply the demanded power.
The difference 'etween these two characteristics of a digital IC is significant from the definitions a'o(e. #ope you find the information presented here useful. Feel free to lea(e your footprints in the comments section 'elow for any further queries, q ueries, feed'ack or suggestions.
*ogic families can 'e classified 'roadly according to the technologies they are 'uilt with. In earlier days we had (ast num'er of these technologies, as you can see in the list 'elow.
1mong these, only CO is most widely used 'y the 1IC !Chip" designers2 we will still try to understand a few of the e&tinct / less used technologies. ore in%depth e&planation of CO will 'e co(ered in the 3*I section.
4efore we start looking at the how gates are 'uilt using (arious technologies, we need to understand a few 'asic concepts. These concepts will go long way i.e. if you 'ecome a 1IC designer or 4oard designer, you may need to know these concepts (ery well.
Fan%in is the num'er of inputs a gate has, like a two input 10D gate has fan%in of two, a three input 010D gate as a fan%in of three. o a 0OT gate always has a fan%in of one. The figure 'elow shows the effect of fan%in on the delay offered 'y a gate for a CO 'ased gate. 0ormally delay increases following a quadratic function of fan%in.
The num'er of gates that each gate can dri(e, while pro(iding (oltage le(els in the guaranteed range, is called the standard load or fan%out. The fan%out really depend s on the amount of electric current a gate can source or sink while dri(ing other gates. The effects of loading a logic gate output with more than its rated fan%out has the following effects.
• • •
In the *O6 state the output (oltage 3O* may increase a'o(e 3O*ma&. In the #I5# state the output (oltage 3O# may decrease 'elow 3O#min. The operating temperature of the de(ice may increase there'y reducing the relia'ility of the de(ice and e(entually causing the de(ice failure. Output rise and fall times may increase 'eyond specifications The propagation delay may rise a'o(e the specified (alue.
0ormally as in the case of fan%in, the delay offered 'y a gate increases with the increase in fan%out.
5ate delay is the delay offered 'y a gate for the signal appearing at its input, 'efore it reaches the gate output. The figure 'elow shows a 0OT gate with a delay of 7Delta7, where output 89 changes only after a delay of 7Delta7. 5ate delay is also known as propagation delay.
5ate delay is not the same for 'oth transitions, i.e. gate delay will 'e different for low to high transition, compared to high to low transition.
*ow to high transition delay is called turn%on delay and #igh to low transition delay is called turn%off delay.
5ates are connected together with wires and these wires do delay the signal they carry, these delays 'ecome (ery significant when frequency increases, say when the transistor si:es are su'%micron. ometimes wire delay is also called flight time !i.e. signal flight time from point 1 to 4". 6ire delay is also known as transport delay.
The same signal arri(ing at different parts of the design with different phase is known as skew. kew normally refers to clock signals. In the figure 'elow, clock signal C*;
reaches flip%flop FF< at time t<, so with respect to the clock phase at the source, it has at FF< input a clock skew of t< time units. 0ormally this is e&pressed in nanoseconds.
The wa(eform 'elow shows how clock looks at different parts of the design. 6e will discuss the effects of clock skew later.
*ogic le(els are the (oltage le(els for logic high and logic low.
VOHin ! The minimum output (oltage in #I5# state !logic 9=9". 3O#min is .> 3 for TT* and >.? 3 for CO. VOLa" ! The ma&imum output (oltage in *O6 state !logic 9<9". 3O*ma& is <.> 3 for TT* and <.= 3 for CO. VIHin ! The minimum input (oltage guaranteed to 'e recognised as logic =. 3I#min is 3 for TT* and @.A 3 for CO. VILa" ! The ma&imum input (oltage guaranteed to 'e recognised as logic <. 3I*ma& is <.B 3 for TT* and =.A 3 for CO.
IOHin! The ma&imum current the output can source in #I5# state while still maintaining the output (oltage a'o(e 3O#min. IOLa" ! The ma&imum current the output can sink in *O6 state while still maintaining the output (oltage 'elow 3O*ma&. IIa" ! The ma&imum current that flows into an input in any state !=1 for CO".
5ate circuits are constructed to sustain (ariations in input and output (oltage le(els. 3ariations are usually the result of se(eral different factors.
4atteries lose their full potential, causing the supply (oltage to drop #igh operating temperatures may cause a drift in transistor (oltage and current characteristics purious pulses may 'e introduced on signal lines 'y normal surges of current in neigh'ouring supply lines.
1ll these undesira'le (oltage (ariations that are superimposed on normal operating (oltage le(els are called noise. 1ll gates are designed to tolerate a certain amount of noise on their input and output ports. The ma&imum noise (oltage le(el that is tolerated 'y a gate is called noise margin. It deri(es from I/%O/ (oltage characteristic, measured under different operating conditions. It9s normally supplied from manufacturer in the gate documentation.
L#$ %Low noise argin&! The largest noise amplitude that is guaranteed not to change the output (oltage le(el when superimposed on the input (oltage of the logic gate !when this (oltage is in the *O6 inter(al". *03I*ma&%3O*ma&. H#$ %Hig' noise argin&! The largest noise amplitude that is guaranteed not to change the output (oltage le(el if superimposed on the input (oltage of the logic gate !when this (oltage is in the #I5# inter(al". #03O#min%3I#min
tr %(ise tie&
The time required for the output (oltage to increase from 3I*ma& to 3I#min.
t) %Fall tie&
The time required for the output (oltage to decrease from 3I#min to 3I*ma&.
tp %*ropagation +elay&
The time 'etween the logic transition on an input and the corresponding logic transition on the output of the logic gate. The propagation delay is measured at midpoints.
)ach gate is connected to a power supply 3CC !3DD in the case of CO". It draws a certain amount of current during its operation. ince each gate can 'e in a #igh, Transition or *ow state, there are three different currents drawn from power supply.
• • •
ICC#$ Current drawn during #I5# state. ICCT$ Current drawn during #I5# to *O6, *O6 to #I5# transition. ICC*$ Current drawn during *O6 state.
For TT*, ICCT the transition current is negligi'le, in comparison to ICC# and ICC*. If we assume that ICC# and ICC* are equal then,
1(erage ower Dissipation 3cc E !ICC# ICC*"/
For CO, ICC# and ICC* current is negligi'le, in comparison to ICCT. o the 1(erage power dissipation is calculated as 'elow.
1(erage ower Dissipation 3cc E ICCT.
o for TT* like logics family, power dissipation does not depend on frequency of operation, and for CO the power dissipation depends on the operation frequency.
ower Dissipation is an important metric for two reasons. The amount of current an d power a(aila'le in a 'attery is nearly constant. ower dissipation of a circuit or system defines 'attery life$ the greater the power dissipation, the shorter the 'attery life. ower dissipation is proportional to the heat generated 'y the chip or system2 e&cessi(e heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range2 will cause gates to generate improper output (alues. Thus power dissipation of any gate implementation must 'e kept as low as possi'le.
oreo(er, power dissipation can 'e classified into tatic power dissipation and Dynamic power dissipation.
*s %Static *ower Dissipation&! ower consumed when the output or input are not changing or rather when clock is turned off. 0ormally static power dissipation is caused 'y leakage current. !1s we reduce the transistor si:e, i.e. 'elow ?
Total power dissipation static power dissipation dynamic power dissipation.