Department of Engineering
Lecture 08 Finite State Machine Design Using VHDL
10/1/2006
ECE 358: Introduction Introduction to VHDL
Lecture 8-1
Today Department of Engineering
Sequential state
10/1/2006
digital logic system design
diagram/state graph
ECE 358: Introduction to VHDL
Lecture 8-2
Synchronous sequential design Department of Engineering
Most
sequential systems are synchronous; that is controlled by a clock.
State
transfer diagram or Algorithmic state machines (ASM) are used to design sequential circuits.
Sequential
circuits:
– Mealy machine: output =func (current state, inputs) – Moore machine: output=func (current state) 10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-3
Synchronous Design Summary using VHDL Department of Engineering
Draw
a state graph and state table
Write
VHDL code and implement in EDA software package
Check
and simulate your design
Download
10/1/2006
or fabricate
ECE 358: Introduction to VHDL
Lecture 8-4
State assignment in VHDL Department of Engineering
State
encoding:
– Binary state encoding – One-hot state encoding Example:
four states S0,S1,S2,S3
Binary state encoding: 00,01,10,11 One-hot state encoding: 1000,0100,0010,0001 Binary
state encoding: CPLD
One-hot
state encoding: FPGA, rich resources in registers.
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-5
State assignment in VHDL Department of Engineering
Binary
state encoding
type STATE_TYPE is (S1, S2, S3, S4); attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "00 01 10 11"; signal CURRENTSTATE, NEXTSTATE: STATE_TYPE; One-hot state encoding type STATE_TYPE is (S1, S2, S3, S4); Attribute ENUM_ENCODING: STRING; attribute ENUM_ENCODING of STATE_TYPE: type is "0001 0010 0100 1000"; signal CS, NS: STATE_TYPE; 10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-6
State machine VHDL code Department of Engineering
TWO
processes for Mealy Machine:
– One process is used to model the state registers to decide the next state – Second process models to update the next state and output logic
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-7
State machine VHDL code Department of Engineering
Two
or Three processes for Moore machine: – One process is used to model the state registers to decide the next state – Second process models to update the next state – Three process models the output logic – OR 2nd and 3rd combined into one process
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-8
FSM VHDL Design Example Department of Engineering
0110 sequence detector, Mealy machine no pattern overlapping
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-9
0110 Detector Mealy FSM No overlapping Department of Engineering
architecture NOOV of MEALY0110NV is
library IEEE; use IEEE.STD_LOGIC_1164.all; entity MEALY0110NV is port (CLK,RST,X : in std_logic;
type STATE_TYPE is (IDLE,S0,S01,S011); signal CS,NS: STATE_TYPE; begin
Z : out std_logic); end entity MEALY0110NV;
SEQ: process (CLK,RST) is begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if;
10/1/2006
end process SEQ;
ECE 358: Introduction to VHDL
Lecture 8-10
0110 Detector Mealy FSM No overlapping COM: process (CS,X) is
when S01=>
begin
if (X = ‘0') then
Z<=‘0’;
NS<=S0;
case CS is
else
when IDLE =>
NS<=S011;
if (X = ‘0') then
end if;
NS<=S0;
when S011 =>
else
if (X = ‘0') then
NS<=IDLE;
NS<=IDLE;
end if;
Z<=‘1’;
when S0 =>
else
if (X = ‘0') then
NS<=IDLE;
NS<=S0;
end if;
else NS<=S01; end if;
10/1/2006
Department of Engineering
end case; end process COM; end architecture NOOV;
ECE 358: Introduction to VHDL
Lecture 8-11
0110 Detector Mealy FSM No overlapping Simulation Department of Engineering
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-12
0110 detector Moore Machine Department of Engineering
0110 sequence detector, Moore machine no pattern overlapping
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-13
0110 Detector Moore FSM No overlapping Department of Engineering
architecture NOOV of MOORE0110NV is
library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic);
type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is
end entity MOORE0110NV;
begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-14
0110 Detector Moore FSM No overlapping with two processes COM: process (CS,X) is
when S01=> if (X = ‘0') then
begin
NS<=S0;
Z<=‘0’;
else
case CS is
NS<=S011;
when IDLE =>
end if;
if (X = ‘0') then
when S011 =>
NS<=S0;
if (X = ‘0') then
else
NS<=S0110; else
NS<=IDLE;
NS<=IDLE;
end if;
end if;
when S0 => if (X = ‘0') then
when S0110=> Z<=‘1’;
NS<=S0; else NS<=S01; end if;
10/1/2006
Department of Engineering
NS<=IDLE; end case; end process COM; end architecture NOOV;
ECE 358: Introduction to VHDL
Lecture 8-15
0110 Detector Moore FSM No overlapping Simulation Department of Engineering
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-16
0110 Detector Moore FSM No overlapping Another VHDL code style
(three processes) Department of Engineering
architecture NOOV of MOORE0110NV is
library IEEE; use IEEE.STD_LOGIC_1164.all; entity MOORE0110NV is port (CLK,RST,X : in std_logic; Z : out std_logic);
type STATE_TYPE is (IDLE,S0,S01,S011,S0110); signal CS,NS: STATE_TYPE; begin SEQ: process (CLK) is
end entity MOORE0110NV;
begin if (rising_edge(CLK)) then if (RST=‘1’ ) then CS<=IDLE; else CS <= NS; end if; end if; end process SEQ;
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-17
0110 Detector Moore FSM No overlapping COM: process (CS,X) is
when S01=> if (X = ‘0') then
begin
NS<=S0;
case CS is
else
when IDLE =>
NS<=S011;
if (X = ‘0') then
end if;
NS<=S0;
when S011 =>
else
if (X = ‘0') then
NS<=IDLE;
NS<=S0110; else
end if;
NS<=IDLE;
when S0 =>
else NS<=S01;
No output Z in the COM process
end if;
if (X = ‘0') then NS<=S0;
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when S0110=> NS<=IDLE; end case; end process COM;
end if; 10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-18
0110 Detector Moore FSM No overlapping OUTPUTZ: process (CS) is
begin
Department of Engineering
OR
Z<=‘1’ when CS=S0110 else
case CS is
‘0’;
when IDLE|S0|S01|S011=>
end architecture NOOV;
Z<=‘0’; when S0110=> Z<=‘1’; end case; end process OUTPUTZ;
3rd process defines the output function
end architecture NOOV;
10/1/2006
ECE 358: Introduction to VHDL
Lecture 8-19
