IMPLEMENTATION AND TESTING OF ADDERS USING BIST A Mini-Project Report Report Submitted in partial fulfillment of the requirements for the award of the degree Of
BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATION ENGINEERING By
Veeramachaneni Deepthi (09BN1A04A0) Under the guidance Of
Mr P.Nataraju
M.Tech,
Asst. Professor ECE,TECA. ECE,TECA.
Department Of Electronics and Communication Engineering
TENALI ENGINEERING COLLEGE (Affiliated to JNTU KAKINADA, Approved by AICTE) ANUMARLAPUDI ANUMARLAPUDI (POST), Via SANGAMJAGARLAMUDI SANGAMJAGARLAMUDI TENALI
(R.M.S), GUNTUR (Dt.) - 522213. 2012-13
TENALI ENGINEERING COLLEGE [Sponsored by JAMPALA GOPALA RAO EDUCATION SOCIETY]
(Affiliated to JNTU KAKINADA, Approved by AICTE) ANUMARLAPUDI(POST), ANUMARLAPUDI(P OST), Via SANGAMJAGARLAMUDI
TENALI (R.M.S), GUNTUR (Dt.) - 522213.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
BONAFIDE CERTIFICATE
This is to certify that this Project entitled “Implementation and Testing of Adders using BIST” is the bonafide work of Veeramachaneni Deepthi (09BN1A04A0), who carried out the project under our supervision .
(Mr P.Nataraju
M.Tech)
Internal Guide
(Mr. A. Nagaraju M.Sc., M.Tech.)
Head of the Department
Submitted for Viva voice Examination held on__________________
Internal Examiner
External Examiner
DECLARATION
I
VEERAMACHANENII DEEPTHI VEERAMACHANEN
(09BN1A04A0),
hereby
declare that the Mini - Project Report entitled “IMPLEMENTATION AND TESTING OF ADDERS USING BIST”is the bonafide work done by me
under the guidance of Mr . P.Nataraju M.Tech, Asst. Professor in ECE Department at Tenali Engineering College, Anumarlapudi, is submitted in partial fulfillment of the requirements for the award of the degree of B.Tech in Electronics and Communication Engineering.
NAME OF CANDIDATE Veeramachaneni Deepthi (09BN1A04A0)
DATE: PLACE: TECA
SIGNATURE OF CANDIDATE
ACKNOWLEDGEMENT
My deep sense of gratitude goes to our beloved Director, Prof. J. Jawahara Rao garu who provided all facilities and necessary encouragement encouragement during the course of study.
I extend my gratitude and sincere thanks to our Principal, Dr. G. Srinivasa Rao garu for his support.
I take the privilege to thank our Head of the Department, Mr. A. Nagaraju garu for his support and encouragement. encouragement.
I dedicate my whole hearted thanks to our guide, Mr P.Nataraju for his commendable inspiring guidance, valuable advice, encouragement and motivation given to succeed in our endeavors.
I extend my sincere thanks to all of our Teachers.
Last but not the least; I sincerely si ncerely thank my parents, friends and all well wishers for their loving prayers for successful completion of this project.
CONTENTS TOPIC
PAGE NO
ABSTRACT LIST OF FIGURES LIST OF TABLES ABBREVATIONS CHAPTER 1 INTRODUCTION
1
1.1 INTRODUCTION TO VLSI
1
1.2 OBJECTIVE
1
1.3 SOFTWARE
2
1.3.1 Xilinx ISE
2
CHAPTER 2 BUILT IN SELF TESTING (BIST)
3
2.1 OVERVIEW
3
2.2 BASIC BIST ARCHITECTURE
4
2.3 DESIGNS FOR TESTABILITY
4
2.4 BIST STRUCTURE
5
2.4.1 PSEUDO RANDOM PATTERN GENERATOR
5
2.4.2 BIST RESPONSE COMPACTION
6
2.4.3 OUTPUT RESPONSE ANALYSER
7
2.4.4 CUT (CIRCUIT UNDER TEST)
7
2.4.5 SIGNATURE ANALYSIS
7
2.4.6 MISR (MULTIPLE INPUT SIGNATURE REGISTER)
7
2.5 BUILT IN LOGIC BLOCK OBSERVER (BILBO)
8
2.5.1 BILBO IN SERIAL SCAN MODE
9
2.5.2 BILBO IN LFSR PATTERN GENERATOR MODE
9
2.5.3 BILBO IN D FLIP-FLOP MODE
10
2.5.4 BILBO IN MISR MODE
10
CHAPTER 3 FAULT DETECTION
11
3.1 FAULT DETECTION
11
CHAPTER 4 ADDERS
14
4.1 BASIC ADDER UNIT
14
4.1.1 HALF ADDER
14
4.1.2 FULL ADDER
15
4.2 RIPPLE CARRY ADDER
16
4.3 CARRY LOOK-AHEAD ADDER
17
4.4 CARRY SAVE ADDER
20
CHAPTER 5 INTRODUCTION TO VHDL
21
5.1 DEFINITION
21
5.2 FEATURES OF VHDL
21
5.3 DESIGN FLOW IN VHDL
21
5.4 MODELING TECHNIQUES
22
5.4.1 BEHAVIORAL MODELING
23
5.4.2 DATAFLOW MODELING
24
5.4.3 STRUCTURAL MODELING
24
5.5 OPERATORS
27
5.6 APPLICATIONS
28
CHAPTER 6 RESULTS
29
6.1 OUTPUT WAVE FORMS
29
6.1.1 FULL ADDER
29
6.1.2 RIPPLE CARRY ADDER
29
6.1.3 CARRY LOOK AHEAD ADDER
30
6.1.4 CARRY SAVE ADDER
30
6.1.5 BILBO SERIAL SCAN MODE
31
6.1.6 BILBO LFSR MODE
31
6.1.7 BILBO D-FF MODE
32
6.1.8 BILBO MISR MODE
32
6.2 TECHNOLOGY SCHEMATIC
33
6.2.1 FULL ADDER
33
6.2.2 RIPPLE CARRY ADDER
34
6.2.3 CARRY LOOK AHEAD ADDER
35
6.2.4 CARRY SAVE ADDER
36
6.2.5 BILBO
37
6.3 SIMULATION RESULTS OF STUCK AT FAULTS
38
6.3.1 RIPPLE CARRY ADDER
38
6.3.2 CARRY LOOK AHEAD ADDER
39
CHAPTER 7 CONCLUSION
40
7.1 CONCLUSION 7.2 FUTURE ENHANCEMENT
40 40
REFERENCES
ABSTRACT Very Large Scale Integration (VLSI) has made a dramatic impact on the growth of integrated circuit technology. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost advantages in VLSI systems. There are, however, potential problems which may retard the effective use and growth of future VLSI technology. Among these is the problem of circuit testing, which becomes increasingly difficult as the scale of integration grows. Because of the high device counts and limited input/output access that characterize VLSI circuits, conventional testing approaches are often ineffective and insufficient for VLSI circuits. Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test itself. BIST has gained popularity as an effective solution over circuit test cost, quality and reuse problems. During test mode, because of more switching activity, it exhibits at about 200% more power than in normal mode. Test pattern generation is the major step in BIST that mainly affects the power consumption.BILBO technique is one of the type in BIST which is used to reduce switching activity. From this we can design a variety of adders like ripple carry adder, carry look ahead adder, carry save adder, etc. In this project, these adders are designed and tested using different BIST techniques.
LIST OF FIGURES FIGURE 2.2
BASIC BIST ARCHITECTURE
4
FIGURE 2.3
DESIGN FOR TESTABILITY
4
FIGURE 2.4
BIST STRUCTURE
5
FIGURE 2.4.1
LFSR SEQUENCE GENERATOR
6
FIGURE 2.5
GENERAL BILBO STRUCTURE
8
FIGURE 2.5.1
SERIAL SCAN MODE
9
FIGURE 2.5.2
LFSR PATTERN GENERATOR GENERATOR
9
FIGURE 2.5.3
D FLIP FLOP MODE
10
FIGURE 2.5.4
MISR MODE
10
FIGURE 3.1
CIRCUIT UNDER TEST (CUT)
11
FIGURE 3.2
FAULTY CIRCUIT
12
FIGURE 4.1.1
HALF ADDER
14
FIGURE 4.1.2
FULL ADDER
15
FIGURE 4.1.3
REALIZATION OF FULL ADDER USING 2 HALF ADDERS 16
FIGURE 4.2
RIPPLE CARRY ADDER
16
FIGURE 4.2.1
CARRY PROPAGATION FOR RIPPLE CARRY ADDER
17
FIGURE 4.3
CARRY LOOK AHEAD ADDER
19
FIGURE 4.3.1
GENERATION OF SUM AND CARRY IN CARRY LOOK AHEAD ADDER
19
FIGURE 4.4
CARRY SAVE ADDER
20
FIGURE 5.3
DESIGN FLOW CHART
22
FIGURE 5.3.1
VHDL PROGRAM STRUCTURE
22
FIGURE 5.4
MODELING TECHNIQUES
22
FIGURE 5.5
PROPERTIES USED IN THE PROJECT
27
FIGURE 6.1.1
WAVE FORM OF FULL ADDER
29
FIGURE 6.1.2
WAVE FORM OF RIPPLE CARRY ADDER
29
FIGURE 6.1.3
WAVE FORM OF CARRY LOOK AHEAD ADDER
30
FIGURE 6.1.4
WAVE FORM OF CARRY SAVE ADDER
30
FIGURE 6.1.5
WAVE FORM OF SERIAL SCAN MODE
31
FIGURE 6.1.6
WAVE FORM OF LFSR MODE
31
FIGURE 6.1.7
WAVE FORM OF D FF MODE
32
FIGURE 6.1.8
WAVE FORM OF MISR MODE
32
FIGURE 6.2.1
TECHNOLOGY TECHNOLOGY SCHEMATIC OF FULL ADDER
33
FIGURE 6.2.2
TECHNOLOGY SCHEMATIC OF RIPPLE CARRY ADDER
34
FIGURE 6.2.3
TECHNOLOGY SCHEMATIC OF CARRY LOOK AHEAD ADDER
35
FIGURE 6.2.4
TECHNOLOGY SCHEMATIC OF CARRY SAVE ADDER
36
FIGURE 6.2.5
TECHNOLOGY SCHEMATIC OF BILBO
37
FIGURE 6.3.1
SIMULATION RESULTS OF STUCK AT FAULT FOR RIPPLE CARRY ADDER
FIGURE 6.3.2
38
SIMULATION RESULTS OF STUCK AT FAULT FOR CARRY LOOK AHEAD ADDER
39
LIST OF TABLES
PAGE NO
TABLE 2.4.1
SEQUENCES GENERATED USING LFSR
6
TABLE 2.5
BILBO MODES
8
TABLE 3.1
RESPONSE OF FAULT FREE CIRCUIT
12
TABLE 3.2
RESPONSE OF FAULTY CIRCUIT
13
TABLE 4.1.2
TRUTH TABLE OF FULL ADDER
15
TABLE 5.5
OPERATORS
27
ABBREVATIONS S.NO
Short Form
Full Form
1.
ATE
Automatic Test Equipment
2.
ASIC
Application Specific Integrated Circuit
3.
BIST
Built In Self Test
4.
BILBO
Built In Logic Block Observer
5.
CUT
Circuit Under Test
6.
CLB
Configurable Logic Blocks
7.
DUT
Device Under Test
8.
DFT
Design For Testability Testabilit y
9.
HDL
Hardware Description Language
10.
IC
Integrated Circuits
11
LFSR
Linear Feed Back Shift Register
12.
MISR
Multiple Input Signature Analysis
13.
ORA
Output Response Analyzer
14.
PRPG
Pseudo Random Pattern Generator
15.
RAM
Random Access Memory
16.
TPG
Test Pattern Generator
17.
VHSIC VHS IC
Very High Speed Integrated Circuit
18.
XST
Xilinx Synthesis Technology
CHAPTER 1 INTRODUCTION In this chapter a brief introduction to VLSI is presented. Along with this objective of the project and the software used is also illustrated here.
1.1 INTRODUCTION TO VLSI VLSI field involves packing more and more logic devices into smaller and smaller areas. It has not only reduced the size and the cost but also increased the complexity of the circuits. The positive improvements have resulted in significant performance/cost performance/cost advantages in VLSI systems. Testing of integrated circuits (ICs) is of crucial importance to ensure a high level of quality. The impact of testing affects affects areas of manufacturing manufacturing as well as those involved in design. Given this range of design involvement, how to go about best achieving a high level of confidence in IC IC operation is a major concern. concern. This desire to attain a high quality quality level must be tempered tempered with the cost and time involved involved in this process. process. These two design design considerations are at constant odds. It is with both goals in mind (effectiveness vs. cost/time) that Built-In-Self Test (BIST) has become a major design consideration in Design-For-Testability Design-For-Testability (DFT) ( DFT) methods. This work presents methodology to detect faults using Built in Self Test (BIST) and other various Designs for Testability (DFT) methods. It also introduces Automatic Test Pattern Generation for maximum fault coverage. The task of determining whether the chip is working properly or not is very tedious. However, if chip is not properly fabricated, they can cause system failure and result in heavy loss in economy. System failure results difficulty in debugging. The debugging cost grows exponentially as we move from chip to board level and then towards the system level. As the number of transistor integrated in the chip increases, task to test the functionality of chip become more and more difficult. To overcome these design issues, Design for Testability has become more important.
1.2 OBJECTIVE The main objective is designing and implementation of various adders with self testing (using built in self test), which can be used in any processor application, as adders are the basic building blocks in many digital system. In addition to the designing part, we test the designed adders to detect whether the adder is fault free or not.
1.3 SOFTWARE The software used is VHDL. VHDL is an acronym for VHSIC Hardware Description Language. Language. The word 'hardware' The language VHDL covers the complete range of applications and can be used to model (digital) hardware in a general way. Hardware Description Language (HDL) = "Programming"-language for modeling of (digital) hardware. VHDL features have three important modeling techniques: Behavioral Modeling
Dataflow Modeling
Structural Modeling
1.3.1 Xilinx ISE
The Integrated Software Environment (ISE) is the Xilinx design software suite that allows you to take your design from design entry through Xilinx device programming. The ISE Project Navigator manages and processes your design through the following steps in the ISE design flow Design Entry
Synthesis
Implementation
Verification
Device Configuration
CHAPTER 2 BUILT IN SELF TESTING (BIST) Digital system is tested during its lifetime on numerous occasions. It is very important to have quick and very high fault coverage testing. This chapter explains the need for self testing. BIST can be implemented in many different diff erent ways, one such advanced method is BILBO (Built in Logic Block Observer).
2.1 OVERVIEW One common and widely used in semiconductor semiconductor industry for IC chip testing is to to ensure that this is to specify test as one of the t he system functions and thus becomes selftest. BIST is one of the most popular test solutions to test the embedded cores. Main advantage of this methodology is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. This aspect impacts the cost/time constraint. Also it saves the memory requirement. In addition, BIST can provide at speed, in system testing of the Circuit-UnderTest (CUT). This is crucial to the quality component component of testing. In addition, BIST can overcome pin limitations due to packaging, packaging, make efficient use of available extra chip area and provide more detailed information about the faults present. All these benefits are plentiful motivations for BIST. The basic idea of BIST, in its most simple form, is to design a circuit so that the circuit ci rcuit can test itself and determine whether it is “good” or “bad” (fault-free (fault-free or faulty, respectively). This typically requires additional circuitry whose functionality must be capable of generating test patterns as well as providing a mechanism to determine if the output responses of the circuit under test (CUT) to the test patterns correspond to that of a fault-free circuit. Test pattern generation is the major step in BIST that mainly affects the power consumption. In order to reduce the switching activity during test mode, several test pattern generators are proposed .On a very basic level, BIST needs a stimulus Test Pattern Generator (TPG), a circuit to be tested, a way to analyze the results, and a way to compress those results for simplicity and handling.
2.2 BASIC BIST ARCHITECTURE A representative architecture of the BIST circuitry as it might be incorporated into the CUT is illustrated in the block diagram of Figure below.
Fig 2.2 Basic BIST Architecture The two essential functions include the test pattern generator (TPG) and output response analyzer (ORA). While the TPG produces a sequence of patterns for testing the CUT, the ORA compacts the output responses of the CUT into some type of Pass/Fail
indication. This BIST architecture includes two essential functions. The two essential functions include the test pattern generator (TPG) and output response analyzer (ORA). While the TPG produces a sequence of patterns for testing the CUT, the ORA compacts the output responses of the CUT into some type of Pass/Fail indication.
2.3 DESIGNS FOR TESTABILITY
Fig 2.3 Design for Testability The mechanics of testing, as illustrated in below Figure, are similar at all levels of testing, including design verification. A set of input stimuli is applied to a circuit and the output response of that circuit is compared to the known good output response, or expected response, to determine if the circuit is "good" or "faulty". There are various testing techniques of a circuit. Basic testing t esting flow is shown above.
2.4 BIST STRUCTURE Generate test vectors, apply them to the circuit under test (CUT) or device under test (DUT), and then verify the response.
Fig 2.4 BIST Structure
Fig shows a simple BIST block diagram which uses a linear feedback shift register (LFSR) to generate the test vectors and multiple input signature register (MISR) to verify the output against the correct response of the circuit under test. A general BIST includes the following: 1. Pseudo random pattern generator (PRPG) 2. BIST Response Compaction 3. Output response analyzer (ORA) 2.4.1 Pseudo Random Pattern Generator
To perform test on any circuit, a Pseudo random pattern generator use mostly linear feedback shift register (LFSR) to generate input test vectors. When the outputs of the flip-flops are loaded with a seed value i.e anything except all 0s, which would cause the LFSR to produce all 0 patterns and when the LFSR is clocked, it will generate a pseudo random pattern of 1s and 0s. Standard LFSR The main part of BIST is LFSR which can generate random numbers which are used to identify the physical faults in the IC. Every LFSR has a characteristic polynomial
that describes its behaviour. Fig 2.4.1 LFSR Sequence Generator Q0*=Q1 XOR Q2 Q1*=Q0 Q2*=Q1
Q0*
Q1*
Q2*
Q0Q1Q2
1
1
1
111 (7)
0
1
1
011 (3)
0
0
1
001 (1)
1
0
0
100 (4)
0
1
0
010 (2)
1
0
1
101 (5)
1
1
0
110 (6)
Table 2.4.1 Sequences generated using LFSR A Linear Feedback Shift Register is a sequential shift register with combinational logic. It generates pseudo-random cycles through a sequence of binary values. A linear feedback shift register can be formed by performing exclusive-OR on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip flops.The fl ops.The standard LFSR method has been used as the test pattern generator for the BIST. It consists of D flip-flops fl ip-flops and linear exclusive-OR gates which is shown in figure. 2.4.2 BIST Response Compaction During BIST, for every test pattern that being generated, the CUT produces a set of output values. In order to ensure the chip is fault free, every output values from the CUT for each test pattern will need to compare with the correct output values obtained from the simulations. This is a tedious and time consuming process. Thus, it is necessary to reduce the enormous of circuit responses to a manageable size that can be either store in the chip or can easily compared with the golden response values. 2.4.3 Output Response Analyser
The on-chip storage of the entire test input vectors with their corresponding outputs are stored in RAM. After applying the input, Outputs are checked and compared with the stored ones. If stored data is same as the output of the circuit then circuit is fault free otherwise it is fault. In BIST, both the Test Pattern Generation (TPG) and Output Response Analyzer (ORA) are incorporated inside the chip. Assuming that all levels of hierarchy uses BIST, each element element test itself and transmits t ransmits the result to the higher level of hierarchy. 2.4.4 CUT (Circuit Under Test)
The system that is to be tested is termed as DUT. It is the circuit of the IC that is going to be checked for any defects after its manufacturing. Any digital design represented in one of the Hardware Description Languages (HDL’s) is used as a DUT.
2.4.5 Signature Analysis
Signature Analysis is a compression technique based on the concept of cyclic redundancy checking .The good and faulty circuits produce different signatures. Test Patterns for BIST can be generated at-speed by an LFSR with only a clock input. The outputs of the circuit-under-test must be compared to the known good response. In general, collecting each output response and off-loading it from the circuit under test for comparison is too inefficient to be practical. The general solution is to compress the entire output stream into a single signature value. 2.4.6 MISR (Multiple Input Signature Register) Multiple-input signature register (MISR) is the solution that compacts all outputs into one LFSR. It works because LFSR is linear and obeys superposition principle. All responses are superimposed in one LFSR. The final remainder is XOR sum of remainders of polynomial divisions of each Primary Output by the characteristic polynomial. Its output develops a signature based on the effect of all the bits fed into it. If any bit is wrong, the signature will be different from the expected value and a fault will have been detected. A Multiple Input Signature-analysis Register (MISR) can be used to reduce the amount of hardware required to compress a multiple bit stream. The MISR provides an alternative to using multiple Linear Feedback Shift Registers (LFSRs) in parallel and separately comparing the error polynomials. pol ynomials.
2.5 BUILT IN LOGIC BLOCK OBSERVER (BILBO) A BILBO (built-in logic block observer) combines normal flip flops with a few additional gates. Built-in logic block observer (BILBO) has become one of the most widely accepted techniques for self-testing self- testing of complex digital IC’s. This technique is based on grouping the storage elements of the circuit in the two registers which give this technique its name. A BILBO register provide four different modes. With each of its stages acting as independent registers; as a generator of pseudo random sequences; as analyser of multiple-input signatures; and reset of all stages.
Fig 2.5 General BILBO Structure
B1
B2
MODE
0
0
Serial Scan mode
0
1
LFSR mode
1
0
D Flip Flop mode
1
1
MISR Mode Table 2.5 BILBO Modes
2.5.1 BILBO In Serial Scan Mode
B1=B2=0.BILBO acts as serial shift register. Data are serially clocked into the register through SI while the register contents can be simultaneously read parallel at the output, or clocked out through the serial output SO.
Fig 2.5.1 Serial Scan Mode 2.5.2 BILBO In LFSR Pattern Generator Mode
Here B1=0, B2=1 in this mode BILBO is used to Generate Test Sequences. These test sequences (input test vectors) are then applied to the Circuit under Test.
Fig 2.5.2 LFSR Pattern Generator
2.5.3 BILBO IN D FLIP-FLOP MODE
B1=1, B2=0i n this mode we can externally apply the inputs say D1, D2….Dn. These inputs are then given to the D Flip flop and then forwarded as Q1, Q2….Qn.
Fig 2.5.3 D Flip Flop Mode 2.5.4 BILBO IN MISR MODE
Here B1=B2=1, The BILBO is converted into Multiple Input Signature Register. In this mode, it may be used for performing parallel signature analysis or for generating pseudo random sequences.
Fig 2.5.4 MISR Mode
CHAPTER 3 FAULT DETECTION There are various kinds of faults which can affect the output of any circuit, one such fault is stuck at fault and this fault is illustrated in this chapter.
3.1 FAULT DETECTION Consider the circuit shown in figure. The circuit can be expressed using Boolean equation as, Out [0] = In [0] + In [1] + In [2] Out [1] = In [0] . In [1]. In [2] Out [2] = (In [0] . In [1]) + In [2] We have three input bits and three output bits for the t he given circuit to be tested. So we design an LFSR with three output bits to generate the test vectors. Let the LFSR be of maximal length so that we get the test vector sequence or pseudo random binary sequence as {111, 011, 001, 100, 010, 101, and 110} as explained earlier. This pseudo random binary sequence is applied to the circuit under test and the output is recorded. The output at the end of 7th clock is t aken as the signature.
Fig 3.1 Circuit Under Test (CUT)
Clock Pulse
LFSR Output
Output of CUT
MISR outputs
1
111
111 11 1
000
2
011
101 10 1
110
3
001
001
000
Signature
110 4
100
101 10 1
001
5
010
001 00 1
111
6
101
101 10 1
100
7
110
101 10 1
110
Table 3.1 Response of fault free fr ee circuit From the table we can see that the signature value is 110 for fault free circuit.Now considers the circuit in the presence of a fault. Let the circuit has a stuck at zero (s-@-0) fault at the input of the t he OR gate for the computing out bit. For the 4th clock tick the faulty circuit gives incorrect output. But for the 5th clock tick the output i s same in the presence and absence of fault, but the multiple input signature register output remain different ever after the first occurrence of the fault. Also when the complete pseudo random binary sequence is applied to the circuit under test, i.e. at the end of 7 clock ticks, we take the output of signature register as the signature of the circuit under test.
Fig 3.2 Faulty circuit
Clock Pulse
LFSR output
Output of CUT
MISR outputs
1
111
111
000
2
011
101
110
3
001
001
000
4
100
001
001
5
010
001
011
6
101
001
111
7
110
001
100
Signature
100
Table 3.2 Response of faulty circuit We can see that the signature values computed for correct and faulty circuit are different. Hence we can conclude that verifying the signature of a circuit, on applying the complete pseudo random binary sequence, sequence, to the t he signature value computed earlier or generated by a fault free circuit is sufficient to determine whether the circuit is faulty or operating correctly. The MISR propagates the fault from the clock cycle where it appeared first till the end of the input i nput sequence with the help of the feedback. The test pattern can be repeated after resetting the multiple input signature register. When the test pattern is repeated, the responses remain the same as long as the fault is present. When fault is detected in an IC ri ght after manufacturing, we can easily remove it. But if the fault f ault is to be detected after integrating the IC to a PCB, the cost of finding the fault as well as correcting it is higher. This cost keeps increasing as the fault detection stage is later in the production procedure.
CHAPTER 4 ADDERS Addition is a fundamental operation for any digital system, digital signal processing or control system. A fast and accurate operation of a digital system is greatly influenced by the performance of the resident adders. In this chapter various adders are explained. Adders are also very important component in digital systems because of their extensive use in other basic digital operations such as subtraction, multiplication and division. Hence, improving performance of the digital adder would would greatly advance the execution of binary operations inside a circuit compromised of such blocks. The performance of a digital circuit block is gauged by analyzing its power dissipation, layout area and its operating speed.
4.1 BASIC ADDER UNIT The most basic arithmetic operation is the addition of two binary digits, i.e. bits. A combinational circuit that adds two t wo bits, according the scheme outlined below, is called a half adder. A full adder is one that adds three bits, the third produced produced from a previous addition operation. One way of implementing a full adder adder is to utilizes two half adders in its implementation. The full adder is the basic unit of addition employed employed in all the adders that are implemented in this project. 4.1.1 Half Adder A half adder is used to add two binary digits digits together, A and B. It produces S, the sum of A and B, and the corresponding corresponding carry out Co. Although by itself, a half adder is not extremely useful, it can be used as a building block for larger adding circuits (FA). One possible implementation is using two AND gates, two inverters, and an OR gate instead of a XOR gate as shown in Fig. 4.1.
Fig 4.1.1 Half Adder Boolean expressions for sum and carry are Sum = A B= A′B + AB′ Carry = AB 4.1.2 Full Adder
A full adder is a combinational circuit that performs the arithmetic sum of three bits: A, B and a carry in, C. Also, as in the case of the half adder, the full adder produces produces the corresponding sum, S, and a carry carry out Co. A full adder may be designed designed by two half adders in series as as shown in below Figure .The sum of A and and B are fed to a second second half adder, which then adds it to the carry in C (from a previous addition operation) to
generate the final final sum S. The carry out is the result of an OR operation operation taken from the carry outs of both half adders. Boolean expressions for sum and carry are Sum = C
(A
B)
Carry = AB + C (A
B) A B C Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
Table 4.1.2 Truth Table of Full Adder
Fig 4.1.2 Full Adder
Fig 4.1.3 Realization of Full Adder Using Two Half Adders
4.2 RIPPLE CARRY ADDER The ripple carry adder is constructed by cascading full adders (FA) blocks in series. One full adder is responsible responsible for the addition of two binary binary digits at any stage stage of the ripple carry. The carryout of one stage is fed fed directly to the carry-in of the next stage. For an n-bit parallel adder, adder, it requires requires n computational computational elements elements (FA). Figure shows an example example of a parallel adder: adder: a 4-bit ripple-carry adder. It is composed of four full adders. The augend’s bits of x are added to the addend bits of y r espectfully espectfully of their binary position. Each bit addition creates creates a sum and a carry out. The carry out is then transmitted to the carry in of the next higher-order higher-order bit. The final result creates creates a sum of four bits plus a carry out (c4).
Fig 4.2 Ripple Carry Adder
Even though this is a simple adder and can be used to add unrestricted bit length numbers, it is however not very efficient when large bit numbers are are used. One of the the most serious drawbacks of this adder is that the delay increases linearly with the bit length. Each full adder has to wait for the carry out of the previous stage to output steadystate result. Therefore even if the adder has a value at its output t erminal, it has to wait for the propagation of the carry before the output reaches a correct value. v alue. Taking the example shown below, the addition of x3 and y3 cannot reach steady state until c3 becomes available. available. In turn, c4 has to wait for c3, and so on down to c1. c1. If one full adder takes Tfa seconds to complete its operation, the final result will reach its steady-state value only after 4Tfa seconds. seconds. Its area is nA fa. A small improvement in area consumption can be achieved achieved if it is known in advance that the first carry in (c0) will always be zero. (If so, the first full adder can be replacing by a half adder).
Fig 4.2.1 Carry Propagation for Ripple Carry Carr y Adder The delay of ripple carry adder is linearly proportional to n, the number of bits, therefore the performance of the RCA is limited when n grows bigger. The advantages of the RCA are lower power consumption as well as a compact layout giving smaller chip area.
4.3 CARRY LOOK-AHEAD ADDER In the ripple-carry adder, its limiting factor is the time it takes to propagate the carry. The carry look-ahead look-ahead adder solves this problem problem by calculating the carry carry signals in advance, based based on the input signals. The result is a reduced carry propagation propagation time. The Propagate P and generate G in a full-adder, is given as:
Carry propagate: Pi = Ai
Bi
Carry generate: Gi = Ai.Bi Here both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay. The new expressions for the output sum and the carryout are given by: Si = Pi
Ci-1
Ci+1= Gi + PiCi These equations show that a carry signal will be generated in two cases: 1) If both bits Ai and Bi are 1 2) If either Ai or Bi is 1 and the carry-in Ci is 1. Let's apply these equations for a 4-bit adder: C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 These expressions show that C2, C3 and C4 do not depend on its previous carryin. Therefore C4 does not need need to wait for C3 to propagate. As soon as C0 is computed, computed, C4 can reach reach steady state. The same is also true for C2 and C3 The general expression is PiPi -1….P2P1G0 + PiPiPiPi -1 ….P1P0C0. Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 PiPi-1Gi- 2 + ……. PiPiFor example: A:
1
1
0
1
B:
0
1
1
0
P:
1
0
1
1
G:
0
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
C:
0
S Co
1
Carry look-ahead look-ahead adder’s structure can be divided into three parts: propagate/generate propagate/generate generator, the sum generator and the carry generator
Fig 4.3 Carry Look Ahead Adder
the
Fig 4.3.1 Generation of Sum and Carry in Carry Look Ahead Adder
4.4 CARRY SAVE ADDER Carry save technique can be used when adding together several numbers. A carry-save adder is a type of digital adder, used in computer micro architecture to compute the sum of three or more n-bit numbers in binary. It differs from other digital adders in that it outputs two numbers of the same dimensions as the inputs, one which is a sequence of partial sum bits and another which is a sequence of carry bits. Carry save adder is used to compute sum of three or more n-bit binary numbers. Carry save adder adder is same as a full adder. Figure has 3 inputs inputs a,b,c which are given to full adder as inputs and produces partial sum and carry as S and C as shown in the foll owing example: The final addition is then computed as: 1. Shifting the carry sequence C left by one place. 2. Placing a 0 to the front (MSB) of the partial sum sequence S. 3. Finally, a ripple carry adder is used to add these two together and computing the resulting sum. For example X:
1
0
0
1
1
Y:
1
1
0
0
1
Z:
0
1
0
1
1
S:
0
0
0
0
1
C: Sum:
1
1
0
1
1
1
1
0
1
1
Fig 4.4 Carry Save Adder
1
CHAPTER 5 INTRODUCTION TO VHDL 5.1 DEFINITION VHDL stands for “VHSIC Hardware Description Language.” VHSIC, in turn stands for “Very High Speed Integrated Circuit”. The word 'hardware', however, is used in a wide variety of contexts which range from complete systems like personal computers on one side to the small logical gates on their internal integrated circuits on the other side. This is why different descriptions exist for the hardware functionality. Complex systems are often described by the behavior that is observable from the outside. The description of a basic logic gate, on the other hand, may consist of only one Boolean equation. This is a very short and precise description. Hardware Description Language (HDL) = "Programming"-language for modeling of (digital) hardware.
5.2 FEATURES OF VHDL
The VHDL Hardware Description Language has the following features Designs may be decomposed hierarchically.
Each Design element has both a well-defined interface (for connecting it to other elements) and a precise behavioral specification (for simulating it ).
Behavioral specifications can use either an algorithm or an actual hardware structure to define an element’s operation.
Concurrency, Concurrency, timing, and clocking can all be modeled.
VHDL handles
asynchronous asynchronous as well as synchronous sequential-circuit structures.
5.3 DESIGN FLOW IN VHDL VHDL was designed with principles of structured programming in mind, borrowing ideas from the Pascal Pascal and Ada software programming languages. A key idea is to define the interface of a hardware module module while hiding its internal details. Thus, a VHDL entity is simply a declaration of module’s inputs and outputs, while a VHDL architecture is a detailed detail ed of the module’s internal structure or behavior.
Fig: 5.3 Design flow chart
Fig: 5.3.1 5.3.1 VHDL program structure
5.4 MODELING TECHNIQUES
Fig: 5.4 Modeling Techniques VHDL features also three important modeling techniques:
Behavioral Modeling
Dataflow Modeling
Structural Modeling
5.4.1 Behavioral Modeling At the most fundamental level, the behavior of a module is described by signal assignment statements within processes. The basis for sequential modeling is the t he process construct. 1. Process: A process statement is the main construct in behavioral modeling that
allows you to use sequential statements to describe the behavior of a system over time. 2. If Statements: The if statement executes a sequence of statements whose sequence
depends on one or more conditions. 3. Case statements: The case statement executes one of several sequences of
statements, based on the value of a single expression. 4. Loop statements: A loop statement is used to repeatedly execute a sequence of
sequential statements. statements. There are two types of iteration schemes: schemes:
basic loop
while … loop
5. Next and Exit Statement: The next statement skips execution to the next iteration
of a loop statement and proceeds with the next iteration. 6. Wait statement: The wait statement will halt a process until an event occurs. 7. Null statement: The null statement states that no action will occur.
The syntax is
null;
8. Assertion Statement: Used for internal consistency check or error message
generation. [label:] assert Boolean condition [report string] [severity name]; 9. Report Statement: Used to output messages.
[label:] report string [severity name]; 10. Subprograms: Sub programs are divided into Functions and Procedures. Both
procedures and functions written in VHDL must have a body and may have declarations. Procedures perform sequential computations and return values in global objects or by storing values into int o formal parameters 11. Procedure Call Statement: Call a procedure.
[label:] procedure-name [(actual parameters)]; 5.4.2 Dataflow Modeling A dataflow model specifies the functionality of the entity without explicitly specifying its structure. This functionality shows the fl ow of information through the entity, which is expressed primarily using concurrent signal assignment statements and block statements. This is in contrast to the behavioral style of modeling in which the functionality of the entity is expressed using statements that are executed sequentially. Concurrent Statements Signal Assignment Statement: The signal assignment statement is typically
considered as a concurrent statement rather than as a sequential statement. It can be used as a sequential statement but has the side effect of obeying the general rules for when the target actually gets updated.
Variable Assignment Statement: Assign the value of an expression to a target
variable. [Label:] target: = expression;
Block Statement: A block statement is a concurrent statement. It can be used for
three major purposes:
a. To disable signal drivers by using guards. b. To limit scope of declarations, including signal declarations. c. To represent a portion of a design. 5.4.3 Structural Modeling A structural description of a system is expressed in terms of subsystems interconnected by signals. Each subsystem may in turn be composed of an interconnection of subsystems, and so on, until we finally reach a level consisting of primitive components, described purely in terms of their t heir behavior. A structural description can best be compared to a schematic block diagram that can be described by the components and the interconnection i nterconnections. s. VHDL provides a formal way to do this by Declaring a list of components being used.
Declaring signals which define the nets that interconnect components.
Label multiple instances of the same component so that each instance is uniquely defined.
VHDL Structural Elements The main units in VHDL are entities, architectures, configurations and packages (together with package bodies).
Entity : Interface
Architecture : Implementation, behavior, function
Configuration : Model chaining, structure, hierarchy
Package : Modular design, standard solution, data types, Constants
a.Entity
While an entity describes an interface consisting of the port list most of the time, architecture contains the description of the function of the corresponding module. In general, a configuration is used for simulation purposes, only. In fact, the configuration is the only simulatable object in VHDL as it explicitly selects the entity/architecture pairs to build the complete model. Packages hold the definition of commonly used data types, constants and subprograms. By referencing a package, its content can be accessed and used
Entity entity-nameis port(signal-names: mode signal-type; signal-names: mode signal-type; …….
signal-names: mode signal-type); end entity-name; Architecture b. Architecture
An architecture body describes the internal view of an entity. It describes the functionality or the structure of the entity. The syntax of an architecture body is: Architecture is split into an optional declarative part and the definition part. The declarative part is located between the keywords ' is ' and ' begin '. New objects that are needed only within the architecture constants, data types, signals, subprograms, etc. can be declared here.
Architecture architecture-nameof entity-name is type declarations signal declarations constant declarations function definitions definitio ns procedure definitions definition s component declarations
begin concurrent-statement ……...
concurrent-statement end architecture-name; c.Configuration: A Configuration statement is used to bind a component instance to an entity-
architecture pair. d.Package:
The VHDL design unit package is used to store data that will be accessed by multiple modules. This usually includes constants, constants, data types, sub-types, sub-program declarations, etc Package Body:
The package body is a dependent unit of the package. It is used to store details of the objects declared in the package. This includes sub-programs, sub-programs, algorithms, etc Library:
Usually referred to as the work library. This is an actual sub-directory or physical location used to store all compiled design units. Each simulator or synthesis tool will create such a structure
5.5 OPERATORS VHDL supports different classes of operators that operate on signals, variables and constants. Class 1.Logical operators
And
Or
Nand
Nor
xor
Xnor
2.Relational operators
=
/=
<
<=
>
>=
3. Shift operators
Sll
Srl
Sla
Sra
rol
Ror
4.Addition operators
+
=
&
5. Unary operators
+
-
6. Multiplying operators
*
/
Mod
7. Miscellaneous operators
**
Abs
Not
Rem
Table 5.5 operators The following table gives the properties used in our project
Fig 5.5 Properties used in the project
5.6 APPLICATIONS VHDL is used mainly for the development of Application Specific Integrated Circuits (ASIC s). Tools for the automatic transformation of VHDL code into a gate-level net list were developed already at an early point of time. This transformation is called synthesis and is an integral part of current design flows. For the use with Field Programmable Gate Arrays (FPGA s) several problems exist. In the first step, Boolean equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this Boolean code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLB s as the available resources for interconnections are the bottleneck of current FPGAs. While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLD s). An ongoing field of research is the hardware/software design. The most interesting question is which part of the system should be implemented in software and which part in hardware. The decisive constraints are the costs and the resulting performance.
CHAPTER 6 RESULTS The output of the project is to obtain various characteristics of the adders like RTL schematic, stuck at faults, fault coverage.
6.1 OUTPUT WAVE FORMS 6.1.1 FULL ADDER
Fig 6.1.1 Wave Form of Full Adder 6.1.2 RIPPLE CARRY ADDER
Fig 6.1.2 Wave Form of Ripple Carry Adder
6.1.3 CARRY LOOK AHEAD ADDER
Fig 6.1.3 Wave Form Of Carry Look Ahead Adder 6.1.4 CARRY SAVE ADDER
Fig 6.1.4 Wave Form Of Carry Save Adder
6.1.5 BILBO SERIAL SCAN MODE
Fig 6.1.5 Wave Form Of Serial Scan Mode 6.1.6 BILBO LFSR MODE
Fig 6.1.6 Wave Form Of LFSR Mode
6.1.7 BILBO D FF MODE
Fig 6.1.7 Wave Form Of D FF Mode 6.1.8 BILBO MISR MODE
Fig 6.1.8 Wave Form Of MISR Mode
6.2 TECHNOLOGY SCHEMATIC 6.2.1 FULL ADDER
Fig 6.2.1 Technology schematic of full adder
6.2.2 RIPPLE CARRY ADDER
Fig 6.2.2 Technology schematic of ripple carry adder
6.2.3 CARRY LOOK AHEAD ADDER
Fig 6.2.3 Technology schematic of carry look ahead adder
6.2.4 CARRY SAVE ADDER
Fig 6.2.4 Technology schematic of carry save adder
6.2.5 BILBO
Fig 6.2.5 Technology schematic of BILBO
6.3 SIMULATION RESULTS OF STUCK AT FAULTS 6.3.1 RIPPLE CARRY ADDER
Fig 6.3.1 Simulation Results of Stuck at Fault for Ripple Carry Adder
No. of faults introduced: No. of faults detected:
58 55
Percentage of fault coverage:
*100 = 94.82
6.3.2 CARRY LOOK AHEAD ADDER
Fig 6.3.2 Simulation Results of Stuck at Fault for Carry Look Ahead Adder
No. of faults introduced: No. of faults detected:
58 57
Percentage of fault coverage:
*100 = 98.27
CONCLUSION In this project, we have implemented and tested various types of adders which includes ripple carry, carry look ahead and carry save adder using self test(BILBO).Apart from the designing part, we test the designed adders to find whether the circuit is fault y or not. The simulator used is ISE with Xilinx 7.1 version. Adders are one of the most important components of many systems. Adders are very important basic component in digital systems, because because of their t heir extensive use in other basic digital operations such as subtraction, multiplication and division. So we always need to find a better solution in case of adders. The adders should always consume less power and produce less delay. So through our project we tried to determine which of the three adders works the best. Also as the number of bits used for adders increases, the circuit becomes more complex for testing. Main advantage of this project is that the test patterns are not applied by external Automatic Test Equipments (ATEs) but generated by inbuilt testing circuit. This aspect impacts the cost/time constraint. Also it saves the memory requirement. The biggest advantage of using this project is, the designed circuits can test itself and determine whether it is good or bad using fault coverage.
FUTURE ENHANCEMENT The VLSI field involves packing more and more logic devices into smaller and smaller areas by which the complexity of the circuits increases. Testing of such complex circuits is very difficult. One of the major concerns in testing is the large volumes of test data for reasonably large circuits. As the t he test data increases the memory required r equired for storing them also increases. Some of the future work that can be performed along this project may be designing of all the available adders and to compare them with their delays, power consumptions. Along with designing part, the adders can also be tested to find their t heir fault coverage. When longer sequences are used, signature analysis gives high fault coverage. coverage.
REFERENCES 1) L.T.Wang, Cheng-Wen Wu and Xiaoqing Wen, “VLSI Test Principles & Architectures Design for testability”. 2) M.J. Smith, “Application Specific Integrated Circuits”. 3) Charles E. Stroud, “A Designer’s Guide to Built -In Self-Test”, Self-Test”, University of North Carolina at Charlotte, ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow. 4) Morling R. C. S., “ Designing for Testability”, MSc VLSI System Design, Univ. o Westminster, Dec. 2000. 5) Psarakis, M., D. Gizopoulos and A. Paschalis, “ Test Generation and Fault Simulation for Cell Fault Model Using Stuck at Fault Model Based Test Tools”, Electronic
Testing Journal: Theory and Applications, vol. 13, no:3, Dec. 1998.
URL’S
1) http://www.wikipedia.com 2) http://www.xilinx.com 3) http://www.examsadda http://www.examsadda.com/2011/01/vlsi-introduc .com/2011/01/vlsi-introduction-to-vlsi-circuits-and.html tion-to-vlsi-circuits-and.html
TEXTBOOKS
1) Circuit Design using VHDL, by Pedroni . 2) VHDL by Sjoholm Stefan. 3) VHDL by B Bhaskar. 4) Introduction to VLSI systems by Carver mead-lynn convay rd
5) Basic VLSI design 3 edition by Douglas.A.Pucknell Douglas.A.Pucknell 6) Fault coverage problems in reconfigurable VLSI systems by RanLibeskind-Hadas 7)
VHDL for programmable logic by Kevin skahill.
