Interview questions for DFT

wht is dft? wht is the dirence between verication and dft? dierence between defect, fault and failure? wht is observability and controlability? controlability? wht is scan? how can we perform scan operation? wht is serial and parallel loading? wht is the dierence between sequential and combinational atpg? wht is atpg? wht is drc violation? wht is fault model? how many fault models are there? wht is scan stiching? wht is bist? Compare LOC and LOS hat is setup time and hold time Cloc! divider hat is compression "ault coverage vs test coverage #n scan chains if some $ip $ops are %ve edge triggered and remaining $ip $ops are &ve edge triggered hat you mean by scan chain reordering? 'i b(w )amed Capture *recedures and Cloc! *rocedures +ow much is your design count? Compleity? Cloc! freq how do you debug simulation mismatches when you simulae the generated -.*/ -.*/ patterns? how do you solve coverage issues?

loc!up latches in the scan chains0  .hese are inserted in the chains chains where ever there is a change in the cloc! domain0 domain0 1y cloc! domain we mean, two cloc!s or the same cloc! with phase dierence0

Let us have a condition here to eplain the things2 we have a design with 3 cloc!s CL45 and CL430 .here is a single chain in the design, which means that the scan chain have $ops which can be cloc!ed by either of the cloc!0  .he tool by default will order the $ops in the scan chain such that rst we have one cloc! domain6s $op followed by the other domain $ops0 Let us consider that the CL43 $ops follows CL45 $ops0 )ow consider the $op which is at the boundary that is the one where the output of the CL456s $op is going to the CL436s scan7in0 Cloc! s!ew between these successive scan&storage cells must be less than the propagation delay between the scan output of the rst storage cell and the scan input of the net storage cell0 Otherwise, data slippage may occur0 .hus, data that latches into the last $op of CL45 also latches into the rst $op of CL430 .his situation results in an error because the CL436s $op should latch the CL456s 8old8 data rather than its 8new8 data0  .o overcome this issue we add the loc! up latch where ever there are cloc! domain crossing0 #n our eample we would add a loc!&up latch which has an active high enable and is being controlled by inverted of CL450 .hus becomes transparent only when CL4- goes low and eectively adds a half cloc! of hold time to the output of the last $ip&$op of cloc! domain CL450

50 #n your design you have dual port memories each wor!ing at a dierent frequency0 hat is the cloc! frequency you use for testing 9:1#S.;? 30 hen a failure is detected in parallel testing of memories, how do you !now which memory is failing? <0 hat are the etra pins needed for 1#=- 91uilt #n =epair -nalysis; implementation? >0 hat could be the possible reasons for scan chain failures during /LS 9/ate level Simulation;? Other than setup issues0 0 'id you got any issues during timing simulation of :1#S. patterns? @0 hat are typical frequencies for scan shift, :1#S. tests? A0 +ow is it dierent implementing :1#S. logic for =O:s, S=-:, '=-:S, and register les? Can same controller handle all these? hat are the typical issues faced? B0 hat are the dierences between #.-/ and .-/ standard? D0 hat are the dierences between 1oundary scan and #EEE5FF st andards? Other than 1oundary scan is used for board level testing and the #EEE5FF for core based testing0 5F0 hat is the eect of LOS method for testing delay faults on the tester? 550 hat are the typical issues you face during timing simulation of scan and :1#S. patterns?

530 hat are copy and shadow cell? +ow are they useful? 5<0 hat are the typical cloc! s!ew issues you faced during post layout( timing simulation? 5>0 +ow do you implement '". for a design have lot of -nalog bloc!s? +ow to improve coverage? 50 +ow do you test at&speed faults for inter cloc! domains? 5@0 -re multi&cycle paths tested in the design? 5A0 hy do you need multiple&load patterns? hat are its advantages over basic scan patterns? 5B0 hat are the typical steps to improve coverage when our coverage target is not achieved? 5D0 Steps to  bro!en scan chain issues during -.*/? Step by step procedure to nd the issue? 3F0 hat is sequential depth? 350 +ow to specify cloc!s for at&speed testing in encounter test or any other tool? hat is the synta? 330 #n S'" we have < values best, typical and worst case? 1est is for good processor, less temp , high vol and worst is reverse0 hat is typical? 3<0 hat is split capture? 3>0 hat #s the most challenging issue you faced? +ow you ed it?