ACADEMIC YEAR : 2014-2015 VL7111 VLSI DESIGN LABORATORY-I RECORD NOTE BOOK I SEM ME VLSI DESIGN
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BONA)IDE CERTI)ICATE _______________________ _______________________ LABORAT LABORATORY ORY RECORD 2014-2015 Certified
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____________________________ ____________________________________Reg.No ________Reg.No_______________ ______________________in _______in ____________________________ ____________________________(sub (sub code & name) of Akshaya Akshaya College of Engineering and and ec echnology! hnology! Coimbatore during during the academic academic year "#$%"#$'. "#$%"#$'.
aculty ncharge
*ead of the +e,artment
-ubmitted for Anna ni/ersity! ni/ersity! 0ractical E1amination held on Akshaya College College of Engineering Engineering and e echnology! Coimbatore.
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BONA)IDE CERTI)ICATE _______________________ _______________________ LABORAT LABORATORY ORY RECORD 2014-2015 Certified
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bonafide
record
work
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____________________________ ____________________________________Reg.No ________Reg.No_______________ ______________________in _______in ____________________________ ____________________________(sub (sub code & name) of Akshaya Akshaya College of Engineering and and ec echnology! hnology! Coimbatore during during the academic academic year "#$%"#$'. "#$%"#$'.
aculty ncharge
*ead of the +e,artment
-ubmitted for Anna ni/ersity! ni/ersity! 0ractical E1amination held on Akshaya College College of Engineering Engineering and e echnology! Coimbatore.
I&"e#&a% E*am&e#
E*"e#&a% E*am&e#
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TABLE TABLE O) CONTENTS E+,NO DATE
TITLE O) TE E+.ERIMENT
01,
NO, De!g& $/ NMOS a& CMOS I&e#"e#! - DC a& "#a&!e&" '(a#a'"e#!"'! a& S"'(&g "me!
02,
E!"ma"$& $/ Re!!"a&'e3 Caa'"a&'e a& I&'"a&'e
06,
De!g& $/ M%"%e*e#!3 De'$e#! a& '$m a#a"$ a"$#! A&a%"'a% M$e%&g a& !m%a"$& $/ I-V '(a#a'"e#!"'! $/ a '(a&&e%8& '(a&&e% MOS)ET !&g Ne"$& Ra!$& me"($
04,
.AGE
MARKS STA)) SIGN,
A&a%"'a% M$e%&g a& !m%a"$& $/ $"e&"a% !"#9"$&8/e% $/ "(e MOS)ET !&g /&"e //e#e&'e me"($
05, 0;,
M$e%&g a& a&a%!! $/ MOS 'aa'"$# Sma%% !g&a% A&a%!!
07,
Sm%a"$& $/ S'(#$&ge# e<a"$& 9a!e e'e m$e%&g
0=,
M$e%&g a& Sm%a"$& $/ NMOS a& CMOS '#'"! !&g S'e
0>,
De!g& $/ De!g&&g )IR /%"e#! !&g ).GA
E+,NO:1a
DESIGN AND ANALYSIS ANALYSIS O) NMOS INVERTER INVE RTER
DATE: 3
AIM:
To design a NMOS Inverter and to simulate the DC, Transient characteristics and switching time using Orcad Pspice9. tools. SO)T?ARE RE@IRED:
Orcad Pspice9. ALGORITM:1a
ST!P "# Create Pspice Pro$ect. ST!P # !na%le %lan& pro$ect. 'n Orcad Capture Schematic window appears. ST!P(# Select Place)* part and select re+uired components and place in schematic window. ST!P# Connect the NMOS transistor, resistor, -o -oltage sources and ND using wires. ST!P/# Place -oltage0level -oltage0level mar&ers at input and output terminals. ST!P 1# 'ssign 'ssign constant values 2or voltage sources and %it values 2or inputs. ST!P 3# Per2orm transient, DC and switching anal4sis and simulate the netlist. ST!P 5# -iew -iew the output wave2orm in the wave2orm window.
3
1,DC CARACTERISTICS: SCEMATIC:
V 1
5 V d c 5 . 0 0 0 V
R 1 2 0 0 K 0 V 5 . 0 0 0 V V 2
M 1
V
0 V d c 2 .4 9 9 m V M b re a k N
V
0
.-S.ICE NETLIST:
67i%raries# 6 7ocal 7i%raries# 68rom 68rom PSPIC PSPIC! ! N!T7IS N!T7IST: T: secti section on o2 C#;Pro C#;Progra gram m 8iles; 8iles;Orc Orcad; ad;PSpi PSpice; ce;PSpi PSpice. ce.ini ini 2ile# 2ile#.li .li% % "> " .P?O@! -A6B IA6B A6B DA6B NOIS!A6B .INC <.;nmosinv)SC!M'TIC <.;nmosinv)SC!M'TIC".net< ".net< 6666 INC7EDIN nmosinv)SC!M'TI nmosinv)SC!M'TIC".net C".net 6666 666 6 6 source NMOSINM=M" N>>"5> N>>5(5 > > M%rea&N ?=?" N>>"5> N>>/( >>F -=- N>>5(5 > >-dc -=-" N>>/( > /-dc 6666 ?!SEMIN nmosinv)schematic")ssss n mosinv)schematic")sssss.sim.cir s.sim.cir 6666 .!ND
3
SIMLATION OT.T ?AVE)ORM:
2,TRANSIENT CARACTERISTICS: SCEMATIC:
V 1
5 V d c 5 . 0 0 0 V
R 1 2 0 0 K 0 V 5 . 0 0 0 V V 2
M 1
V
0 V d c 0 V M b re a k N
V
0
3
. - S.ICE NETLIST:
67i%raries# 67ocal 7i%raries # 68rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile#.li% >"5> N>>5(5 > > M%rea&N ?=?" N>>"5> N>>/( >>F -=- N>>5(5 > >-dc -=-" N>>/( > /-dc 6666 ?!SEMIN nmosinv)schematic")sssss.sim.cir 6666 .!ND
3
SIMLATION OT.T ?AVE)ORM:
3
6,S?ITCING CARACTERISTICS: SCEMATIC:
.-S.ICE NETLIST:
67i%raries# 6 7ocal 7i%raries # 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile#.li% ">us > .P?O@! -A6B IA6B A6B DA6B NOIS!A6B .INC <.;nmosinv)SC!M'TIC".net< 6666 INC7EDIN nmosinv)SC!M'TIC".net 6666 6 source NMOSINM=M" N>>"5> N>>5(5 > > M%rea&N ?=?" N>>"5> N>>/( >>F -=-" N>>/( > /-dc E=DSTM STIMA","B G=DP? G=DND N>>5(5 IO=STM IO=7!-!7H> >> ./uS " ?!P!'T 8O?!-!? ./uS > ./uS " !ND?!P!'T 6666 ?!SEMIN nmosinv)schematic")sssss.sim.cir 6666 .!ND 3
SIMLATION OT.T ?AVE)ORM:
RESLT: Thus the NMOS inverter was designed using Orcad Pspice9. tools and its Transient, DC and switching characteristics was simulated.
3
E+,NO:19
DESIGN AND ANALYSIS O) CMOS INVERTERS
DATE: AIM:
To design a CMOS Inverter and to simulate the DC, Transient characteristics and switching time using Orcad Pspice9. tools. SO)T?ARE RE@IRED:
Orcad Pspice9. ALGORITM:
ST!P "# Create Pspice Pro$ect. ST!P # !na%le %lan& pro$ect. 'n Orcad Capture Schematic window appears. ST!P(# Select Place)* part and select re+uired components and place in schematic window. ST!P# Connect the NMOS transistor, PMOS transistor, -oltage sources and ND using wires. ST!P/# Place -oltage0level mar&ers at input and output terminals. ST!P 1# 'ssign constant values 2or voltage sources and %it values 2or inputs. ST!P 3# Per2orm transient, DC and switching anal4sis and simulate the netlist. ST!P 5# -iew the output wave2orm in the wave2orm window.
1,DC CARACTERISTICS 3
SCEMATIC:
.-S.ICE NETLIST:
. 7i%raries# 6 7ocal 7i%raries # 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile# .li% / " .P?O@! -A6B IA6B A6B DA6B NOIS!A6B .INC <.;cmos)SC!M'TIC".net< 6666 INC7EDIN cmos)SC!M'TIC".net 6666 6 source CMOS M=M" N>>" N>>/( > > M%rea&N M=M N>>"/ N>>/( N>>" N>>"/ M%rea&P -=-" N>>"/ > /-dc -=- N>>/( > /-dc 6666 ?!SEMIN cmos)schematic")cmos.sim.cir 6666 .!ND
3
SIMLATION OT.T ?AVE)ORM:
2,TRANSIENT ANALYSIS: SCEMATIC:
.-S.ICE NETLIST: 3
67i%raries# 6 7ocal 7i%raries # 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile#.li% >" N>>/( > > M%rea&N M=M N>>"/ N>>/( N>>" N>>"/ M%rea&P -=-" N>>"/ > /-dc -=- N>>/( > /-dc 6666 ?!SEMIN cmos)schematic")cmos.sim.cir 6666 .!ND SIMLATION OT.T ?AVE)ORM:
6,S?ITCING CARACTERISTICS: 3
SCEMATIC: V 1
5 V d c
M 2
5 . 0 0 0 V
M b r e a k P
V
0 V
D
S T M 2
2 . 4 9 9 m
V
5 . 0 0 0 V
C L K
V
M 1
M b r e a k N
0
.-S.ICE NETLIST #
67i%raries# 6 7ocal 7i%raries# 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile#.li% ">us > .P?O@! - A6B I A6B A6B D A6B NOIS! A6B .INC <.;cmos)SC!M'TIC".net< 6666 INC7EDIN cmos)SC!M'TIC".net 6666 6 source CMOS M=M" N>>" N>>"9" > > M%rea&N E=DSTM STIM A", "B G=DP? G=DND N>>"9" IO=STM IO=7!-!7H> >> ./uS " ?!P!'T 8O?!-!? ./uS > ./uS " !ND?!P!'T M=M N>>"/ N>>"9" N>>" N>>"/ M%rea&P -=-" N>>"/ > /-dc 6666 ?!SEMIN cmos)schematic")cmos.sim.cir 6666 .!ND 3
SIMLATION OT.T ?AVE)ORM:
RESLT:
Thus the CMOS inverter was designed using Orcad Pspice9. tools and its Transient, DC and switching characteristics was simulated. 3
E+,NO:2 ESTIMATION O) RESISTANCE3 INDCTANCE AND CA.ACITANCE DATE: AIM:
To estimate the resistance, inductance and capacitance values %4 C programming. SO)T?ARE RE@IRED:
Tur%o C DESIGN E@ATIONS: Re!!"$#: R = Rs *
R1 = Where
R1 –load resistance
? S Jsheet resistance l )length o2 resistor w Jwidth o2 resistor t )thic&ness o2 resistor Caa'"$#: Cg
Cd H
3
Cg% H here )gate capacitance )drain capacitance )gate to %ul& capacitance )permittivit4 o2 silicon)di)oKide )permittivit4 in 2ree space )permittivit4 o2 silicon d
)depth o2 capacitance )oKide thic&ness
'
)area
I&'"$#: l H r 6 An 6 nB 6u > here r )radius. n )num%er o2 turns. uo)permea%ilit4 in 2ree space.
ALGORITM:
ST!P "# Open tur%o C and create new 2ile. ST!P # T4pe the coding 2or the calculation o2 resistance, inductance L capacitance. ST!P (# Save the 2ile with eKtension as.cpp. ST!P # Compile and run the program. .ROGRAM: E!"ma"$& $/ #e!!"$#: includestdio.h* includeconio.h* includemath.h* void mainAB int ?sH"/int PH12loat tH(>6powA">,)(B 2loat l,w,?,?" ?H?s6Al0wB print2A
3
E!"ma"$& $/ &'"$# : includestdio.h* includeconio.h* -oid mainAB int nH1,rH"> 2loat l,uoH".0">>>>>> lHuo6n6n6r print2Ainductor value#Q2,lB getchAB R E!"ma"$& $/ 'aa'"$#: includestdio.h* includeconio.h* includemath.h* void mainAB 2loat Cg,Cd,Cg%,'H">6powA">,)B 2loat toKH">>>6powA">,)5B,e>H5.5/6powA">,)B,esioH(.9 2loat esiH",dH".36powA">,)(B CgHAesio6e>0toKB6' print2A6esi0dB6' print2A
OT.T:
RESISTANCE:
The resistance value is #"(13(11"5>/553>>>>>>>>>>>.>>>>>> INDCTANCE:
Inductance value is .15>>> CA.CITANCE:
The gate capacitance is#(./(>1> The capacitance is#>.1955 The gate %ul& capacitance is#>.1"(533
3
RESLT:
The resistance, inductance and capacitance values are estimated %4 C programming.
E+,NO:6
DESIGN O) MLTI.LE+ER3 DECODER
DATE:
ANDCOM.ARATOR
AIM:
To design a multipleKer, decoder and comparator using -D7 and -erilog. SO)T?ARE RE@IRED:
UilinK IS! 9."i. ALGORITM:
ST!P "# Open UilinK IS! 9."i so2tware. ST!P # Create a new pro$ect using 8ile New pro$ect. ST!P (# T4pe the program and save the pro$ect. ST!P # In s4nthesis0implementation dou%le clic& s4nthesiVe)UST to chec& s4ntaK. ST!P /# Choose %ehavioral simulation. ST!P 1# In create new sourceTest %ench wave2orm and save the test %ench wave2orm. ST!P 3# In UilinK IS! Simulator Simulate @ehavioral Model. ST!P 5# -eri24 the output wave2orm. .ROGRAM )OR MLTI.LE+ER IN VDL:
li%rar4 I!!! use I!!!.STD=7OIC=""1.'77 use I!!!.STD=7OIC='?IT.'77 use I!!!.STD=7OIC=ENSIN!D.'77 entit4 multipleKer is Port Ai>, i" # in STD=7OIC i # in STD=7OIC i( # in STD=7OIC i # in STD=7OIC i/ # in STD=7OIC i1 # in STD=7OIC i3 # in STD=7OIC i5 # in STD=7OIC 3
i9 # in STD=7OIC i"> # in STD=7OIC i"" # in STD=7OIC i" # in STD=7OIC i"( # in STD=7OIC i" # in STD=7OIC i"/ # in STD=7OIC s # in STD=7OIC=-!CTO? A( downto >B 4 # out STD=7OICB end multipleKer architecture %ehavioral o2 multipleKer is %egin processAi>,i",i,i(,i,i/,i1,i3,i5,i9,i">,i"",i",i"(,i",i"/,sB %egin case s is when <>>>> when <>>>">">>""">>">""">""">>>""> when <">"">"
3
.ROGRAM )OR MLTI.LE+ER IN VERILOG:
module muKAi>, i", i, i(, i, i/, i1, i3, i5, i9, i">, i"", i", i"(, i", i"/, s>, s", s, s(, VB input i> input i" input i input i( input i input i/ input i1 input i3 input i5 input i9 input i"> input i"" input i" input i"( input i" input i"/ input s> input s" input s 3
input s( output V reg op alwa4sWAi> or i" or i or i( or i or i/ or i1 or i3 or i5 or i9 or i"> or i"" or i" or i"( or i" or i"/ or s> or s" or s or s(B %egin caseAs>,s",s,s(RB X%>>>>#opHi> X%>>>"#opHi" X%>>">#opHi X%>>""#opHi( X%>">>#opHi X%>">"#opHi/ X%>"">#opHi1 X%>"""#opHi3 X%">>>#opHi5 X%">>"#opHi9 X%">">#opHi"> X%">""#opHi"" X%"">>#opHi" X%"">"#opHi"( X%""">#opHi" X%""""#opHi"/ de2ault#opHop endcase end assign VHop endmodule
SIMLATION ?AVE)ORM:
.ROGRAM )OR DECODER IN VDL:
li%rar4 I!!! use I!!!.STD=7OIC=""1.'77 3
use I!!!.STD=7OIC='?IT.'77 use I!!!.STD=7OIC=ENSIN!D.'77 entit4 dec is Port A inp # in STD=7OIC=-!CTO? A( downto >B oup # out STD=7OIC=-!CTO? A"/ downto >BB end dec architecture @ehavioral o2 dec is %egin processAinpB %egin case inp is when <>>>>>>>>>>>>>>>>>>"< when <>>>">>>>>>>>>>>>>">< when <>>">>>>>>>>>>>>>">>< when <>>"">>>>>>>>>>>">>>< when <>">>>>>>>>>>>>">>>>< when <>">">>>>>>>>>">>>>>< when <>"">>>>>>>>>">>>>>>< when <>""">>>>>>>">>>>>>>< when <">>>>>>>>>">>>>>>>>< when <">>">>>>>">>>>>>>>>< when <">">>>>>">>>>>>>>>>< when <">"">>>">>>>>>>>>>>< when <"">>>>">>>>>>>>>>>>< when <"">">">>>>>>>>>>>>>< when <""">">>>>>>>>>>>>>>< when <"""">>>>>>>>>>>>>>< when othersH* oupH<))))))))))))))))< end case end process end @ehavioral
SIMLATION ?AVE)ORM:
3
.ROGRAM )OR DECODER IN VERILOG:
module decoderAK, 4, V, w, d>, d", d, d(, d, d/, d1, d3, d5, d9, d">, d"", d", d"(, d", d"/B input K input 4 input V input w output d> output d" output d output d( output d output d/ output d1 output d3 output d5 output d9 output d"> output d"" output d" output d"( output d" output d"/ andAd>,K%ar,4%ar,V%ar,w%arB,Ad",K%ar,4%ar,V%ar,wB,Ad,K%ar,4%ar,V,w%arB,Ad(,K%ar,4%ar,V,wB, Ad,K%ar,4,V%ar,w%arB,Ad/,K%ar,4,V%ar,wB,Ad1,K%ar,4,V,w%arB,Ad3,K%ar,4,V,wB, Ad5,K,4%ar,V%ar,w%arB,Ad9,K,4%ar,V%ar,wB,Ad">,K,4%ar,V,w%arB,Ad"",K,4%ar,V,wB, Ad",K,4,V%ar,w%arB,Ad"(,K,4,V%ar,wB,Ad",K,4,V,w%arB,Ad"/,K,4,V,wB not AK%ar,KB, A4%ar,4B, AV%ar,VB, Aw%ar,wB endmodule
3
SIMLATION ?AVE)ORM:
.ROGRAM )OR COM.ARATOR IN VDL:
use I!!!.STD=7OIC=ENSIN!D.'77 entit4 comparator is Port A a # in STD=7OIC=-!CTO? A( downto >B % # in STD=7OIC=-!CTO? A( downto >B e # out STD=7OIC g # out STD=7OIC l # out STD=7OICB end comparator architecture @ehavioral o2 comparator is %egin processAa,%B %egin i2AaH%Bthen eHX"X gHX>X lHX>X elsi2Aa%Bthen eHX>X gHX>X lHX"X else eHX>X gHX"X lHX>X end i2 end process end @ehavioral
3
SIMLATION ?AVE)ORM:
.ROGRAM )OR COM.ARATOR IN VERILOG:
module comparatorAa(, a, a", a>, %(, %, %", %>, e, g, lB input a( input a input a" input a> input %( input % input %" input %> output e output g output l wire e(,e,e",e>,g(,g,g",g>,l(,l,l",l> assign e(H a( YZ %( assign eH a YZ % assign e"H a" YZ %" assign e>H a> YZ %> assign eH e( L e L e" Le> assign g(Ha( L AY%(B assign gHe( L a L AY%B assign g"He( L e La" L AY%"B assign g>He( L e Le" L a> L AY%>B assign gH g([g[g"[g> assign l(HAYa(B L %( assign lHe( L AYaB L % assign l"He( L e L AYa"B L %" assign l>He( L e L e" L AYa>B L %> assign lHl([l[l"[l> endmodule 3
SIMLATION ?AVE)ORM:
RESLT: Thus the MultipleKers, Decoders and Comparators are designed using -D7 and -erilog and the output wave2orms are veri2ied.
E+,NO:4 DATE:
ANALYTICAL MODELLING AND SIMLATION O) MOS)ET SING NE?TON RA.SON METOD
AIM:
3
To model and simulate the I)- characteristics o2 a p)channel 0n)channel MOS8!Tusing Newton ?aphson method. SO)T?ARE RE@IRED #
M'T7'@ ?>>9%. TEORY:
Newton ?aphson method is a method 2or 2inding successivel4 %etter approKimations to the roots or Veroes o2 a real valued 2unction K#2AKBH>. In this method, the slope AderivativeB o2 the 2unction is calculated at the initial guess value and pro$ected to the x)aKis.The corresponding x)value %ecomes the new guess value.The steps are repeated until the answer is o%tained to a speci2ied tolerance. I2 Initial guess at the root is K i, a tangent can %e eKtended 2rom the point Ki,2AKiB:. The point this tangent crosses the K aKis represents an improved estimate o2 the root. It is used in man4 applications such as arti2icial intelligence and computer vision to 2ind the non linearit4. It is also called as numerical anal4sis.
DESIGN E@ATION:
7et x> %e a good estimate o2 r and let r H x> h. Since the true root is
r and h H r −x>, the num%er h measures how 2ar the estimate x> is 2rom the truth.
Since h is \small,X we can use the linear Atangent lineB approKimation to conclude that > H f Ar B H f A x> hB = f A x>B hf A x>B; and there2ore, unless f A x>B is close to >, h = - f A x>B0 f A x>B
It 2ollows that r H x> h = x> − f A x>B0 f A x>B
estimate x" o2 r is there2ore given %4 x" H x> − f A x>B0 f A x>B
The neKt estimate x is o%tained 2rom x" in eKactl4 the same wa4 as x" was o%tained 2rom x># x H x" − f A x"B0 f A x"B
I2 xn is the current estimate, then the neKt estimate xn" is given %4 3
xn" H xn − f A xnB0 f A xnB ALGORITM:
ST!P"# Open the M'T7'@ simulation tool. ST!P# Select 8ile)*New)*@lan& M)8ile ST!P(# !nter the Matla% code in %lan& M)8ile. ST!P# Save the M)8ile. ST!P/# ?un the code and veri24 the output.
3
MATLAB CODE #
clc clear all 2ormat long s4ms K e H "e)/ Q setting the tolerance value dK H e " 2 H logA)KB KZ Q enter 4our 2unction here K H 3 Q initiall4 assumed value o2 K count H > Q setting counter to &now the no o2 iterations ta&en p H VerosA","B while Aa%sAdKB * eB Q initialising the iteration and continue until the error is less than tolerance dK H evalA20Adi22A2BBB Q calculating dK, di22 is used 2or 2inding the di22erentiation o2 the 2uction K H K ) dK Q updating the value o2 K count H count " Q incrementing the counter pAcountB H K drawnowAB plotAa%sApB,XrX,XlinewidthX,(B grid i2 Acount * (>>B 2print2AX!rror...] Solution not converging ]]] ;nXB Q printing the error message %rea& end end Q plotAa%sApBB i2 Acount (>>B 2print2AXThe solution H XB Qprinting the result K 2print2AX;nNum%er o2 iteration ta&en H Qd;nX,countB
OT.T VALES:
K H (.(/9//>31/59"3 ) >."(59"911553i K H".5"1>(1>39>> ) >.519/33"5(""i K H".""(/35>31" ) >."""5/5>195"51i K H>."("("533"511 ) >.>1359555>"3i K H."3>>3>>>353( ) >.5/(9">(155(i K H".3"(/("3999"( ) >./(1/995"5>5"5i K H>.1999>((35(195 ) >.91/"9///5/>1/i K H)>."1995/5935/3 ) ".>1/1(">>51959/i K H>."11(/>(/(( ) >.5"555(9(/5(9>i K H>.3"3313(3>3"3/ ) >.539(1((1115i K H >.15"3(9(31 ) >.5/115(1/"1/i K H>.15"(9>/5((93 ) >.5/"(3911""3/i K H>.15"(9("399 ) >.5/"(39/13913i The solution H* K H>.15"(9("399 ) >.5/"(39/13913i Num%er o2 iteration ta&en H "( OT.T ?AVE)ORM: 3
Thus the potential distri%ution02ieldThus tThe distri%ution02ield o2 the MOS8!T using 8inite Di22erence method is modeled and simulated.
E+,NO:; DATE:
MODELING AND ANALYSIS O) MOS CA.ACITOR SMALL SIGNAL ANALYSIS
AIM:
To model and anal4Ve MOS Capacitor small signal anal4sis using Matla% ?>>9% SO)T?ARE RE@IRED:
Matla% ?>>9% DESIGIN .ARAMETERS:
-TO A-T> ) Vero)%ias threshold voltageB FP AMOS8!T transconductanceB 'MM' A= ) %ul& threshold parameterB PI A[=8[ ) sur2ace potentialB 7'M@D' A= ) channel length modulationB EO A^ ) electron mo%ilit4B TOU AtoK ) gate oKide thic&nessB NSE@ AN' ) %ul& doping concentrationB 7D A7D ) lateral di22usionB P@ A=@ J %ul& $unction potentialB C_ AC$> ) Vero)%ias %ul& $unction %ottom capacitance per s+uare meter o2 $unction areaB M_ Am$ J %ul& $unction %ottom grading coe22icientB C_S AC$sw ) Vero)%ias %ul& $unction sidewall capacitance per meter o2 $unction perimeterB M_S Am$sw J %ul& $unction sidewall grading coe22icientB C@O Aate)%ul& overlap capacitance per meter channel widthB CDO Aate)drain overlap capacitance per meter channel widthB CSO Aate)source overlap capacitance per meter channel widthB ALGORITM:
ST!P "# Start the program using Matla% ?>>9%. ST!P # !nter the code and save it. ST!P (# ?un the program. ST!P # !nter the num%er o2 energ4 states, length o2 well Ain nmBand step siVeAin nmB. ST!P /# O%serve the output plot. MATLAB CODE:
TH(>> N'H"! 3
NDH> NiH"!"1 doK H >.>>"e)1 es H "".5 eo H (.9 -g=min H )"> -g=maK H (> &%H".(5!)( +H".1>e)"9 eps>H5.5/!)" eps=scHes6eps> eps=oKHeo6eps> -TH&%6T0+ const H 6+6Ni6-T0eps=sc i2 N' ) ND * > 2im H )-T6logAAN')NDB0NiB else 2im H -T6logAAND)N'B0NiB end 2is"H )62im 2isH 62im d2isH A2is)2is"B0>> 2or iH"#>> 2is H 2is" i6d2is 2iAiB H 2is term H eKpA2im0-TB)eKpA2is0-TBeKpA)2im0-TB)eKpA)2is0-TBN'6A2im)2isB0Ni0-T i2 2is ) 2im * > 2ield=scAiB H s+rtA)const6termB else 2ield=scAiB H )s+rtA)const6termB end -gAiBHeps=sc0eps=oK6doK62ield=scAiB 2is)2im end iiH> 2or iH"#>> i2 -gAiB *H -g=min i2 -gAiB -g=maK iiHii" -g"AiiBH-gAiB 2ield"AiiBH2ield=scAiB 2i"AiiB H 2iAiB end end end 2igureA"B plotA2i"0-T)2im0-T,-g"B hold on sur2ace=pot H )62im0-T aA"B H sur2ace=pot 3
%A"B H -g=min aAB H sur2ace=pot %AB H -g=maK cA"B H > dA"B H -g=min cAB H > dAB H -g=maK eA"B H 2is"0-T 2A"B H > eAB H 2is0-T 2AB H > plotAa,%B plotAc,dB plotAe,2B hold o22
OT.T VALES: T H(>> N' H".>>>>e> ND H> Ni H".>>>>e>"1 doK H".>>>>e)>>9 es H"".5>>> eo H(.9>>> -g=min H )"> -g=maK H (> &% H".(5>>e)>( + H ".1>>e)>"9 eps> H5.5/>>e)>" eps=sc H".>(e)>"> eps=oK H(./"/e)>"" -T H >.>/5 const H3.955e>>/ 2im H )>.31> 2is" H".9> 2is H)".9> d2is H)>.>"9> ii H> sur2ace=pot H(1.5" c H> d H)"> c H> > d H)"> (> e H 3(.153 2 H> e H3(.153 )3(.153 2 H> >
3
C-V CARACTERISTICS :
RESLT:
3
Thus the MOS Capacitor small signal anal4sis is modeled and anal4sed using Matla% ?>>9%.
E+,NO:7
SCRODINGER E@ATION BASED DEVICE MODELLING
DATE: AIM:
Simulation o2 Schrodinger e+uation %ased on device modeling. SO)T?ARE RE@IRED:
M'T7'@ ?>>9%. TEORY:
In +uantum mechanics, the Schr`dinger e+uation is a partial di22erential e+uation that descri%es how the +uantum state o2 some ph4sical s4stem changes with time. It is not a simple alge%raic e+uation, %ut a linear partial di22erential e+uation. The di22erential e+uation descri%es the wave 2unction o2 the s4stem, also called the +uantum state or state vector. The concept o2 a state vector, and an e+uation governing its time evolution, namel4 the Schr`dinger e+uation, are 2undamental postulates o2 +uantum mechanics. These ideas cannot %e derived 2rom an4 other principle. In the standard interpretation o2 +uantum mechanics, the wave 2unction is the most complete description that can %e given to a ph4sical s4stem. Solutions to Schr`dingerXs e+uation descri%e not onl4 molecular , atomic, and su%atomic s4stems, %ut also macroscopic s4stems, possi%l4 even the whole universe. The e+uation is derived %4 partiall4 di22erentiating the standard wave e+uation and su%stituting the relation %etween the momentum o2 the particle and the wavelength o2 the wave associated with the particle in De @roglieXs h4pothesis.
DESIGN E@ATION: One dimensional time independent Schrodinger e+uation#
here m is the particleXs mass, is its potential energ4, 3
∇2 is the 7aplacian, and 2 is the wave 2unction.
MatriK representation o2 Schrodinger e+uation#
ALGORITM:
ST!P "# Start the program using Matla% ?>>9%. ST!P # !nter the code and save it. ST!P (# ?un the program. ST!P # !nter the num%er o2 energ4 states, length o2 well Ain nmBand step siVeAin nmB. ST!P /# O%serve the output plot. MATLAB CODE:
clc clear K>H> mH"." sumH" nHinputAX!nter energ4 state n# XB KlHinputAX!nter length o2 the wellAin nmB# XB whileA2loorAmBmB hHinputAX!nter stepsiVe in nm# XB mHAKl)K>B0h i2 2loorAmBm warningAXStep siVe is wrong. !nter proper valueXB end end KHK>#h#Kl 4HVerosAsiVeAKBB 4A"BH> 4Am"BH> 4ABH" 2or iH(#m 4AiB H )A4Ai)BAA)An6n6pi6pi6h6h0AKl6KlBBB64Ai)"BBB sumHsum4AiBZ end 4H40s+rtAsumB QnormaliVation 4H4.Z Q4 gives pro%a%ilit4 densit4 3
2igureAXcolorX,XwhiteXB su%plotA,","B, plotAK,4,XrXB Kla%elAXDistance in nmXB 4la%elAXwave 2unctionXB su%plotA,",B,plotAK,4B Kla%elAXDistance in nmXB 4la%elAXpro%a%ilit4 densit4XB
OT.T ?AVE)ORM:
!nter energ4 state n# "> !nter length o2 the well Ain nmB# "> !nter step siVe in nm# >.>"
0 . 0 5 n o i t c n u f e v a w
0
0 . 0 5 0
1
2
3
4
5
6
7
8
9
1 0
7
8
9
1 0
Di s t a n c ei nn m 3
x1 0 3 y t i s n 2 e d y t i l i b a 1 b o r p
0 0
1
2
3
4
5
6
Di s t a n c ei nn m
RESLT: 3
Thus the Schrodinger e+uation is simulated %ased on device modeling.
E+,NO:= DATE:
MODELLING AND SIMLATION O) NMOS AND CMOS CIRCITS SING S.ICE
AIM:
To model and simulate a NMOS and CMOS using Orcad Pspice9. Tools. SO)T?ARE RE@IRED:
Orcad Pspice9.
TEORY: 1T?O-IN.T NOR GATE ?IT CMOS LOGIC:
The NOR ga"e is a digital logic gate that implements logical NO? . It %ehaves according to the truth ta%le. ' I output A"B results i2 %oth the inputs to the gate are 7O A>B i2 one or %oth input is I A"B, a 7O output A>B results. NO? is the result o2 the negation o2 the O? operator. It can also %e seen as an 'ND gate with all the inputs inverted. SYMBOL AND TRT TABLE:
2 T?O-IN.T NAND GATE ?IT CMOS LOGIC:
The NAND ga"e is a digital logic gate that implements logical N'ND ) it %ehaves according to the truth ta%le. ' 7O output A>B results i2 %oth the inputs to the gate are I A"B i2 one or %oth input is 7O A>B, a I output A"B results. N'ND is the result o2 the negation o2 the 'ND operator.
3
SYMBOL AND TRT TABLE:
6 DI))ERENTIAL AM.LI)IER ?IT NMOS LOGIC:
Di22erential 'mpli2ier is the %asic %uilding %loc& o2 ever4 OP 'MP and is the %asis o2 high speed digital logic circuit 2amil4, called Em""e# C$%e L$g' ECL and the4 are commonl4 used 2or analog circuits. The name Di22erential 'mpli2ier is %ecause o2, the 'mpli2ier will 2ind out the Di22erence %etween two input sources connected to the %ase o2 two transistors and ampli24 the Di22erence.
ALGORITM:
ST!P "# Create Pspice Pro$ect. ST!P # !na%le %lan& pro$ect. 'n Orcad Capture Schematic window appears. ST!P(# Select Place)* part and select re+uired components and place in schematic window. ST!P# Connect the NMOS transistor, PMOS transistor, -oltage sources and ND using wires. ST!P/# Place -oltage0level mar&ers at input and output terminals. ST!P 1# 'ssign constant values 2or voltage sources and %it values 2or inputs. ST!P 3# Per2orm transient, DC and switching anal4sis and simulate the netlist. ST!P 5# -iew the output wave2orm in the wave2orm window.
3
CMOS CIRCIT NOR GATE IN T-S.ICE: SCEMATIC DIAGRAM:
V 1
5 V d c O F F T IM E ! .5 " S D S T M 2 O N T IM E ! .5 " S C LK D E L # $ ! S T # R T V # L ! 1 O P P V # L ! 1
M 4
V
M b r e a k P
5 .1 9 0 m V M 3 O F F T IM E O N T IM E ! D E L # $ !
!
.5 " S .5 " S
S T # R T V # L ! O P P V # L ! 1
5 . 0 0 0 V
D S T M 1 C LK
0
M b r e a k P
4 . 9 9 % V V
V
& & 4 . ' ( V
M 1
M 2
M b re a k N
M b r e a k N
2 .4 9 9 m V
0
.-S.ICE NETLIST:
67i%raries# 6 7ocal 7i%raries # 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile# .li% ">us > 3
.P?O@! -A6B IA6B A6B DA6B NOIS!A6B .INC <.;nor)SC!M'TIC".net< 6666 INC7EDIN nor)SC!M'TIC".net 6666 6 source NO?
M=M" N>>( N>>5// > > M%rea&N E=DSTM" STIMA","B G=DP? G=DND N>>935 IO=STM IO=7!-!7H> >> ./uS " ?!P!'T 8O?!-!? ./uS > ./uS " !ND?!P!'T M=M N>>( N>>935 > > M%rea&N M=M( N>>"> N>>935 N>>( N>>5" M%rea&P E=DSTM STIMA","B G=DP? G=DND N>>5// IO=STM IO=7!-!7H> >" ./uS " ?!P!'T 8O?!-!? ./uS " ./uS " !ND?!P!'T M=M N>>5" N>>5// N>>"> N>>5" M%rea&P -=-" N>>5" > /-dc 6666 ?!SEMIN nor)schematic")nor".sim.cir 6666 .!ND OT.T ?AVE)ORM:
3
CMOS CIRCIT NAND GATE IN T-S.ICE: SCEMATIC DIAGRAM: V 1
5 V d c
5 . 0 0 0 V M 3
M 4
M b re a k P
M b r e a k P
V
O F F T I M E ! . 5 " S D S T M 1 O N T IM E ! .5 " S C L K D E L # $ ! S T # R T V # L O P P V # L !
! 1
5 . 0 0 0 V
1 4 . 9 9 % V V
V
O F F T I M E ! . 5 " S D S T M 2 O N T IM E ! .5 " S C L K D E L # $ ! S T # R T V # L O P P V # L !
! 1
0
M 1
2 . 4 9 9 m
V
M b r e a k N
4 . 9 9 5 V
M 2
M b r e a k N
0
3
0 V
.-S.ICE NETLIST:
67i%raries# 6 7ocal 7i%raries # 6 8rom PSPIC! N!T7IST: section o2 C#;Program 8iles;Orcad;PSpice;PSpice.ini 2ile# .li% ">us > .P?O@! -A6B IA6B A6B DA6B NOIS!A6B .INC <.;nand)SC!M'TIC".net< 6666 INC7EDIN nand)SC!M'TIC".net 6666 6 source N'ND M=M" N>>595 N>>(9/ N>>(1> > M%rea&N M=M N>>(1> N>>9/ > > M%rea&N M=M( N>>/5 N>>(9/ N>>595 N>>/5 M%rea&P M=M N>>/5 N>>9/ N>>595 N>>/5 M%rea&P -=-" N>>/5 > /-dc E=DSTM" STIMA","B G=DP? G=DND N>>(9/ IO=STM IO=7!-!7H> >" ./uS " ?!P!'T 8O?!-!? ./uS " ./uS " !ND?!P!'T E=DSTM STIMA","B G=DP? G=DND N>>9/ IO=STM IO=7!-!7H> >> ./uS " ?!P!'T 8O?!-!? ./uS > ./uS " !ND?!P!'T 6666 ?!SEMIN nand)schematic")nand.sim.cir 6666 .!ND
OT.T ?AVE)ORM:
3
NMOS CIRCIT DI))ERENTIAL AM.LI)IER IN T-S.ICE: SCEMATIC DIAGRAM:
.-S.ICE NETLIST:
.pro%e .option pro%ev 3
.option pro%ei .option pro%e+ 666666666 Simulation Settings ) Parameters and SPIC! Options 666666666 ??esistor=" -dd Out ?H">& ??esistor= -dd Out ?H">& MNMOS=" Out N= nd nd NMOS H./u 7H/>n 'SH./p PSH1.5u 'DH./p PDH1.5u MNMOS= nd N=( Out nd NMOS H./u 7H/>n 'SH./p PSH1.5u 'DH./p PDH1.5u --oltageSource=( -dd nd DC / --oltageSource=" N= nd DC / --oltageSource= N=( nd DC / ICurrentSource=" nd nd DC /u
666666666 Simulation Settings ) 'nal4sis section 666666666 .tran0Powerup >u >u .end
OT.T ?AVE)ORM:
3
RESLT:
Thus the CMOS and NMOS circuit is modeled and simulated using Orcad Pspice9. Tools.
3
E+,NO:>
DESIGN O) DESIGNING )IR )ILTERS
DATE: AIM:
To design a 8I? 2ilter using UilinK So2tware.
SO)T?ARE RE@IRED:
UilinK) IS!)9."i
TEORY:
8I? 2ilters are digital 2ilters with 2inite impulse response. The4 are also &nown as &$e'#!e g"a% /%"e#! as the4 do not have the 2eed%ac& Aa recursive part o2 a 2ilterB, even though recursive algorithms can %e used 2or 8I? 2ilter realiVation. The trans2er 2unction o2 8I? 2ilter approaches the ideal as the 2ilter order increases, thus increasing the compleKit4 and amount o2 time needed 2or processing input samples o2 a signal %eing 2iltered. Due to its simplicit4 and e22icienc4, the window method is most commonl4 used method 2or designing 2ilters. One o2 the draw%ac&s o2 8I? 2ilters is a high order o2 designed 2ilter. 8I? 2ilters can have linear phase characteristic, which is not li&e II? 2ilters.
ALGORITM:
ST!P "# Open UilinK IS! 9."i so2tware. ST!P # Create a new pro$ect using 8ile New pro$ect. ST!P (# T4pe the program and save the pro$ect. ST!P # In s4nthesis0implementation dou%le clic& s4nthesiVe)UST to chec& s4ntaK. ST!P /# Choose %ehavioral simulation. ST!P 1# In create new sourceTest %ench wave2orm and save the test %ench wave2orm. ST!P 3# In UilinK IS! Simulator Simulate @ehavioral Model. ST!P 5# -eri24 the output wave2orm.
.ROGRAM )OR )IR )ILTER:
module 2ilterAK,h,h",h,h(,h,4,cl&B input (#>:K input (#>:h,h",h,h(,h input cl& output ">#>:4 reg (#>:+",+,+(,+ wire ">#>:4>,4",4,4(,4 initial +"H> 3
initial +H> initial +(H> initial +H> alwa4sWAposedge cl&B %egin +H+( +(H+ +H+" +"HK end assign 4>HK6h assign 4"H+"6h" assign 4H+6h assign 4(H+(6h( assign 4H+6h assign 4H4>4"44(4 endmodule SIMLATION ?AVE)ORM:
3
IM.LEMENTATION SING ).GA KIT:
Be/$#e a!!g&&g a'age &!
Sae a/"e# a!!g&&g &!
3
D$9%e '%' $& !&"(e!!-+ST a& m%eme&" e!g&
C%' $& !e& %a"e#
D$9%e '%' $& Ge&e#a"e #$g#amm&g /%e! 3
C%' /&!(
3
Se%e'" $# /%e
Rg(" '%' $& "(e "
3
Se%e'"
#$g#am
C%' $
.#$g#am e*e'"$&
3