Simulation of Multilevel Multil evel Inverter Using PSIM Darshan.S.Patel M.Tech (Power Electronics & Drives) Assistant Professor Department of Electrical Engineering Sankalchand Patel College of Engineerig-Visnagar E-mail:
[email protected] URL:www.darshanspatel.weebly.com
Why Multilevel Inverter?
The Voltage source Inverters Produce an output voltage or a current with level either 0 or Vdc,known as two level inverter. Two Two obta obtain in a qual qualit ity y outp output ut volt voltag age e wave wavefo form rm with with mini minimu mum m amount of ripple content, they require high switching frequency along with various PWM Techniques.
This two level inverters have some limitations in operating at high frequency mainly due to swit switc ching hing losse osses s and con constra strain ints ts of devic evice e ratings. Multilevel inverter present a new set of features that are well suited for use in reactive power compensation. It is east to produce high power, high voltage with the multilevel structure.
Two Level
Three Level
Multilevel Inverter Topologies
Neutral point clamped or Diode clamped clamped topology. Cascaded H-Bridge topology. Flying capacitor or Capacitor Capacitor clamped topology.
Diode Clamped Inverter
m - level leve l inverter inverte r con sists of
For Single Phase: (m-1) capacitors 2(m-1) Switching devices (m-1)(m-2) clamping diodes
Three Phase Three Level Diode Clamped Inverter
Simulation of Diode Clamped Inverter
Tool Box / Components
Block
Parameters
Library browser Input Voltage
Elem Elemen ents ts /Sou /Sourc rces es/V /Vol olta tage ge
DC volt voltag age e sour source ce
Amplitude =100
Power Switch
Elements Power/Switches
IGBT
Default
Sine
Peak Amplitude Amplitude = 0.8 Frequency = 50 Phase angle = 0,-120,-240 DC offset = 1
Triangular
V peak to peak = 1 Frequency = 2000 Duty cycle = 0.5 DC offset = 1 Phase Delay = 0
Ele Elements /Sources/Voltage
Triangular
V peak to peak = 1 Frequency = 2000 Duty cycle = 0.5 DC offset = 0 Phase Delay = 0
Load
Elem Elemen ents ts// Pow Power/R er/RLC LC Bran Branch ches es
Resis esisto tor r
Resistance(Ohm) =20k
Inverter
Elem Elemen ents ts /Con /Contr trol ols/ s/Lo Logi gic c Elem Elemen ents ts
NOT NOT Gate Gate
Default
On control
Elements/Others/ Switch controllers
ON OFF Controller
Default
Comparator
Elements /Controls/Comparator
Comp
Default
Sinusoidal Wave 1/2/3
Triangular Wave 1,3,5
Triangular Wave 2,4,6
Elements /Sources/Voltage
Ele Elements /Sourc urces/Voltage
Full Bridge Inverter
SPWM
Cascaded H Bridge Inverter
Each H-bridge H-bridge must have an isolated DC supply -usually -usually derived from an isolated AC supply via a diode bridge Each bridge bridge can produce +Vdc, 0, -Vdc -Vdc independently independently
Three Phase Three Level Inverter
One
phase of cascaded H bridge inverter consists of 3-1/2 = 2/2 = 1 Identical H Bridges
Phase-A
Three-level inverter needs both a carrier and a reference. In this case the number of triangular carriers is equal to m-1, where m is the number of voltage levels.
For For a thre threee-ph phas asee thre threee-le leve vell inve invert rter er this this mean meanss that that two two triangular carriers and one sinusoidal reference are needed.
Phase shifting on any two adjacent carrier waves is given by
Ø / ( m – 1 ) c r = 3 6 0 ° = 360/ 36 0/(( 3-1) 3-1) = 3 6 0 /2 = 180°
Simulation of Three Phase Three Level CHB Inverter Cascaded H bridge Inverter
Load
PWM Controller
Components
Tool Box / Library browser
Block
Sinusoidal Wave a/b/c
Elements /Sources/Voltage
Sine
Parameters
Peak Amplitude Amplitude = 0.8 Frequency = 50 Phase angle = 0/120/240 DC offset = 0
Triangular Wave 1/2
Ele Elements /Sou Sources/Voltage
Triangular
V peak to peak = 1 Frequency = 2000 Duty cycle = 0.5 DC offset = -1/0 Phase Delay = 0/180
Triangular Wave 3/4
Ele Elements /Sou Sources/Voltage
Triangular
V peak to peak = 1 Frequency = 2000 Duty cycle = 0.5 DC offset = -1/0 Phase Delay = 120/300
Elements /Sources/Voltage
Triangular
V peak to peak = 1 Frequency = 2000 Duty cycle = 0.5 DC offset = -1/0 Phase Delay = 240/60
Triangular Wave 5/6
Gate Pulses
Carrier Based PWM Schemes It classified into two categories 1.Phase Shifted Carrier PWM method (PSPWM) 2. Level Shifted PWM methods
In Phase Disposition (IPD) Alternative Phase Opposition Disposition (APOD) Phase Opposition Disposition (POD)
Triangular carriers Triangular
required
m-1=6 where m= voltage level All the triangular carriers have
the same frequency and the same peak to peak amplitude. There is a phase shift between any two adjac adjacent ent carri carrier er waves, waves, given by
Ø / (m – 1 ) c r = 3 6 0 ° Here Øcr = 360 /6 = 60 °
°
Line to neutral Voltage waveform(Van) 3E 2E
E 0
-E
-2E
-3E
(A) In Phase Disposition (IPD)
Line to neutral Voltage waveform(Van)
(B) Phase Opposition Disposition (POD)
Line to neutral Voltage waveform(Van)
(C) Alternate Alternate Phase Opposition Disposition
Line to neutral Voltage waveform(Van)
1.José Rodríguez, Jih-Sheng Lai, and Fang Zheng Peng, “Multilevel Inverters: A Survey of Topologies, Controls, and Applications”, IEEE Transactions on Industrial Electronics, Vol. 49, No. 4, August 2002, pp.724-738. 2.Darshan Patel ,Dr. R Saravanakumar, Dr K.K.Ray, R.Ramesh “A Review of Various Carr Carrie ierr Base Based d PWM PWM Meth Method ods s for for Mult Multil ilev evel el Inverter” , IICPE 2010,India International confer conferenc ence e on Power Power Electr Electroni onics cs .Janua .January ry 28-30, 28-30,201 2011,a 1,att Netaji Netaji Subhas Subhas Instit Institute ute of Technology-New Delhi by IEEE Power Electronics Society and this Paper Published in IEEE IEEE Explor Explore e Digital Digital Library Library INSPEC INSPEC Access Accession ion Number Number:: 1187377 1873778, 8, Digita Digitall Object Object Identifier: 10.1109/IICPE.2011.5728059 Identifier: 10.1109/IICPE.2011.5728059 3.Da 3.Dars rsha han n Pate Patel, l, Dr. Dr. R Sara Sarava vana naku kuma marr, Dr K.K. K.K.Ra Ray y, R.Ra R.Rame mesh sh “Design and Implementation of three Level CHB inverter with phase shifted SPWM using TMS320F24PQ”, IICPE IICPE 2010, 2010, India India Intern Internati ationa onall confer conferenc ence e on Power Power Electr Electroni onics. cs. January 28-30,2011,at Netaji Subhas Institute of Technology-New Delhi by IEEE Power Electronics Society and this Paper Published in IEEE Explore Digital Library INSPEC Accession Number: 11873860, 11873860, Digital Object Identifier: 10.1109/IICPE.2011.5728 Identifier: 10.1109/IICPE.2011.5728
