Rajagiri School Of Engineering Engineering & Technology, Technology, Kakkanad Kakkanad
Expt No: 10 Date: 30-03-2012 COUNTER AIM
To design and simulate any counter using any model
THEORY
In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Counters can be implemented quite easily using register-type circuits such as the flipflop, and a wide variety of designs exist, e.g.: - Asynchronous (ripple) counters - Synchronous counters - Johnson counters - Decade counters - Up-Down counters The simplest counter circuit is a single D-type flip-flop, with its D (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows overflows (starts over from 0). This counter counter will increment increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. Where a stable count value is important across several bits, which is the case in most counter systems, synchronous counters are used. These also use flip-flops, either the D-type or the more complex J-K type, but here, each stage is clocked simultaneously by a common clock signal. Synchronous counters can also be implemented with hardware finite state machines, which are more complex but allow for smoother, more stable transitions .
ALGORITHM
Step1: Start Step2: Declare the entity COUNTER with inputs, RESET and CLK and output, COUNT Step3: Declare the architecture COUNTER_architecture of COUNTER giving the internal description of the entity Step4: Declare the process with sensitivity list CLK, RESET
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Systems Lab
Rajagiri School Of Engineering & Technology, Kakkanad
Step5: If RESET = ‘1’ then assign temp = 0 and goto step8 Step6: Under clock synchronization, if temp = ‘7’ the assign temp = 0 and goto step8 Step7: Else assign temp with temp+1 Step8: Assign COUNT with temp Step9: Carry out Syntax check for the code and then use Model Simulator for simulation Step10: Force the required inputs in and verify the output waveforms with the truth table Step11: Stop
PROGRAM CODE
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity COUNTER is Port ( CLK, RESET : in bit; COUNT : out INTEGER range 0 to 7); end COUNTER
architecture COUNTER_architecture of COUNTER is
begin process(CLK, RESET) variable temp : INTEGER range 0 to 7; begin if (RESET = ‘1’) then temp:=0; elsif (CLK’event and CLK = ‘1’) then if (temp=7 )then temp:=0; else temp:=temp+1; end if; end if;
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Rajagiri School Of Engineering & Technology, Kakkanad
COUNT <= temp; end process;
end COUNTER_architecture;
RESULT
CLK RESET COUNTER
1 1 0
2 0 1
3 0 2
4 0 3
5 0 4
6 0 5
7 0 6
8 0 7
9 0 0
WAVEFORM
CONCLUSION
A three bit up-counter was designed and simulated successfully.
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10 0 1