* What is signal integrity? How it affects Timing? * What is IR drop? How to avoid .how it affects timing? * What is EM and it effects? * What is floor plan and power plan? * What are types of routing? * What is a grid .why we need and different types of grids? * What is core and how u will decide w/h ratio for core? * What is effective utilization and chip utilization? * What is latency? Give the types? * What is LEF? * What is DEF? * What are the steps involved in designing an optimal pad ring? * What are the steps that you have done in the design flow? * What are the issues in floor plan? * How can you estimate area of block? * How much aspect ratio should be kept (or have you kept) and what is the utilization? * How to calculate core ring and stripe widths? * What if hot spot found in some area of block? How you tackle this? * After adding stripes also if you have hot spot what to do? * What is threshold voltage? How it affect timing? * What is content of lib, lef, sdc? * What is meant my 9 track, 12 track standard cells? * What is scan chain? What if scan chain not deta ched and reordered? Is it compulsory? * What is setup and hold? Why there are ? What if setup and hold violates? * In a circuit, for re g to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency? * How R and C values are affecting time? * How ohm (R), fared (C) is related to second (T)? * What is transition? What if transition time is more ? * What is difference between normal buffer and clock buffer? * What is antenna effect? How it is avoided? * What is ESD? * What is cross talk? How can you avoid? * How double spacing will avoid cross talk? * What is difference between HFN synthesis and CTS? * What is hold problem? How can you avoid it? * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iter ation 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why? * What is partial floor plan? * What parameters (or aspects) differentiate Chip Design & Block level design?? * How do you place macros in a full chip design? * Differentiate between a Hierarchical Design and flat design?
* Which is more complicated when u have a 48 MHz and 500 MHz clock design? * Name few tools which you used for physical verification? * What are the input files will you give for primetime correlation? * What are the algorithms used while routing? Will it optimize wire length? * How will you decide the Pin location in block level design? * If the routing congestion exists between two macros, then what will you do? * How will you place the macros? * How will you decide the die size? * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem? * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM? * In your project what is die size, number of metal layers, technology, foundry, number of clocks? * How many macros in your design? * What is each macro size and no. of standard cell count? * How did u handle the Clock in your design? * What are the Input needs for your design? * What is SDC constraint file contains? * How did you do power planning? * How to find total chip power? * How to calculate core ring width, macro ring width and strap or trunk width? * How to find number of power pad and IO power pads? * What are the problems faced related to timing? * How did u resolve the setup and hold problem? * If in your design 10000 and more numbers of problems come, then what you will do? * In which layer do you prefer for clock routing and why? * If in your design has reset pin, then itll affect input pin or output pin or both? * During power analysis, if you are facing IR drop problem, then how did u avoid? * Define antenna problem and how did u resolve these problem? * How delays vary with different PVT conditions? Show the graph. * Explain the flow of physical design and inputs and outputs for each step in flow. * What is cell delay and net delay? * What are delay models and what is the difference between them? * What is wire load model? * What does SDC constraints has? * Why higher metal layers are preferred for Vdd and Vss? * What is logic optimization and give some methods of logic optimization. * What is the significance of negative slack? * How the width of metal and number of straps calculated for power and ground? * What is negative slack ? How it affects timing? * What is track assignment? * What is grided and gridless routing?
* What is a macro and standard cel l? * What is congestion? * Whether congestion is related to placement or routing? * What are clock trees? * What are clock tree types? * Which layer is used for clock routing and why? * What is cloning and buffering? * What are placement blockages? * How slow and fast transition at inputs effect timing for gates? * What is antenna effect? * What are DFM issues? * What is .lib, LEF, DEF, .tf? * What is the difference between synthesis and simulation? * What is metal density, metal slotting rule? * What is OPC, PSM? * Why clock is not synthesized in DC? * What are high-Vt and low-Vt cells? * What corner cells contains? * What is the difference between core filler cells and metal fillers? * How to decide number of pads in chip level design? * What is tie-high and tie-low cells and where it is used * What is signal integrity? How it affects Timing? * What is IR drop? How to avoid .how it affects timing? * What is EM and it effects? * What is floor plan and power plan? * What are types of routing? * What is a grid .why we need and different types of grids? * What is core and how u will decide w/h ratio for core? * What is effective utilization and chip utilization? * What is latency? Give the types? * What is LEF? * What is DEF? * What are the steps involved in designing an optimal pad ring? * What are the steps that you have done in the design flow? * What are the issues in floor plan? * How can you estimate area of block? * How much aspect ratio should be kept (or have you kept) and what is the utilization? * How to calculate core ring and stripe widths? * What if hot spot found in some area of block? How you tackle this? * After adding stripes also if you have hot spot what to do? * What is threshold voltage? How it affect timing? * What is content of lib, lef, sdc? * What is meant my 9 track, 12 track standard cells?
* What is scan chain? What if scan chain not deta ched and reordered? Is it compulsory? * What is setup and hold? Why there are ? What if setup and hold violates? * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency? * How R and C values are affecting time? * How ohm (R), fared (C) is related to second (T)? * What is transition? What if transition time is more ? * What is difference between normal buffer and clock buffer? * What is antenna effect? How it is avoided? * What is ESD? * What is cross talk? How can you avoid? * How double spacing will avoid cross talk? * What is difference between HFN synthesis and CTS? * What is hold problem? How can you avoid it? * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iter ation 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why? * What is partial floor plan? * What parameters (or aspects) differentiate Chip Design & Block level design?? * How do you place macros in a full chip design? * Differentiate between a Hierarchical Design and flat design? * Which is more complicated when u have a 48 MHz and 500 MHz clock design? * Name few tools which you used for physical verification? * What are the input files will you give for primetime correlation? * What are the algorithms used while routing? Will it optimize wire length? * How will you decide the Pin location in block level design? * If the routing congestion exists between two macros, then what will you do? * How will you place the macros? * How will you decide the die size? * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem? * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM? * In your project what is die size, number of metal layers, technology, foundry, number of clocks? * How many macros in your design? * What is each macro size and no. of standard cell count? * How did u handle the Clock in your design? * What are the Input needs for your design? * What is SDC constraint file contains? * How did you do power planning? * How to find total chip power? * How to calculate core ring width, macro ring width and strap or trunk width? * How to find number of power pad and IO power pads?
* What are the problems faced related to timing? * How did u resolve the setup and hold problem? * If in your design 10000 and more numbers of problems come, then what you will do? * In which layer do you prefer for clock routing and why? * If in your design has reset pin, then itll affect input pin or output pin or both? * During power analysis, if you are facing IR drop problem, then how did u avoid? * Define antenna problem and how did u resolve these problem? * How delays vary with different PVT conditions? Show the graph. * Explain the flow of physical design and inputs and outputs for each step in flow. * What is cell delay and net delay? * What are delay models and what is the difference between them? * What is wire load model? * What does SDC constraints has? * Why higher metal layers are preferred for Vdd and Vss? * What is logic optimization and give some methods of logic optimization. * What is the significance of negative slack? * How the width of metal and number of straps calculated for power and ground? * What is negative slack ? How it affects timing? * What is track assignment? * What is grided and gridless routing? * What is a macro and standard cel l? * What is congestion? * Whether congestion is related to placement or routing? * What are clock trees? * What are clock tree types? * Which layer is used for clock routing and why? * What is cloning and buffering? * What are placement blockages? * How slow and fast transition at inputs effect timing for gates? * What is antenna effect? * What are DFM issues? * What is .lib, LEF, DEF, .tf? * What is the difference between synthesis and simulation? * What is metal density, metal slotting rule? * What is OPC, PSM? * Why clock is not synthesized in DC? * What are high-Vt and low-Vt cells? * What corner cells contains? * What is the difference between core filler cells and metal fillers? * How to decide number of pads in chip level design? * What is tie-high and tie-low cells and where it is used
Qualcomm Interview Questions In building the timing constraints, do you need to constrain all IO (Input-Output) ports? y y y y
Can
a single port have multi-clocked? How do you set delays for such ports? How is scan DEF (Design Exchange Format) generated? What is purpose of lockup latch in scan chain? Explain short circuit current.
Answer: Short Circuit Power y
What
are pros/cons of using low Vt, high Vt cells?
Answer: Multi Threshold Voltage Technique Issues With Multi Height Cell Placement in Multi Vt Flow y
How
do you set inter clock uncertainty?
Answer: set_clock_uncertainty ±from clock1 -to clock2 y
y
In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran? What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?
Answer:
Difference in clock uncertainty values; Clocks are propagated in post CTS. In post CTS clock latency constraint is modified to model clock jitter . y
How
is clock gating done?
Answer: Clock Gating y
What
constraints you add in CTS (Clock Tree Synthesis) for clock gates?
Answer: Make the clock gating cells as through pins. y
What
is trade off between dynamic power (current) and leakage power (current)?
Answer: Leakage Power Trends Dynamic Power y
How
do you reduce standby (leakage) power?
Answer: Low Power Design Techniques y y
y
y y y y y y y y
Explain top level pin placement flow? What are parameters to decide? Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning? With net length of 1000um how will you compute R C values, using equations/tech file info? What do noise reports represent? What does glitch reports contain? What are CTS (Clock Tree Synthesis) steps in IC compiler? What do clock constraints file contain? How to analyze clock tree reports? What do IR drop Voltagestorm reports represent? Where /when do you use DCAP (Decoupling Capacitor) cells? What are various power reduction techniques?
Answer: Low Power Design Techniques
