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SHIFT REGISTERS
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Accumulation/Distribution
Multiplication:
6 × 13 = 78
Sequential Shift/Add-Method
Example 1: 0
Sequential addition from row to row:
• Method to avoid adder arrays
× 0 0 1 + 0 1 1 0 1 0 0
1 1 1 0 0
0
register for partial product and mul• shift register
1 0 0 1 1 0 0
tiplier
Sum:
00000110 00000110 00011110 01001110
1 1 0
Product
1
1
0
Multiplicand
0
0
0
1
Bits:
4:4
0 1 0 0 1 0 1
6 × 13 = 78
Product
1
0
1
Multiplier
Test = 1
4:4
0
1
1
0
1
1
0
1
5:3
0
0
1
1
0
1
1
0
ADD
Shift
cycle, • with each cycle, 1. partial product increases by one digit 2. multiplier multiplier is reduced reduced by one digit
Test = 0 NOADD Shift 6:2
0
0
0
1
1
0
1
1
6:2
0
1
1
1
1
0
1
1
7:1
0
0
1
1
1
1
0
1
• MSBs of partial product and multiplicand are aligned in each cycle
Test = 1
ADD
Shift
• not the multiplicand is shifted ⇒ partial product and multiplier are
Test = 1 7:1
1
0
0
1
1
1
0
1
8:0
0
1
0
0
1
1
1
0
ADD
Shift
DONE!
219
220
Example 2: 1
15 × 13 = 195
1
1
1
Multiplicand
0
0
0
1
1. Load multiplier multiplier into lower half of shift register (the upper half half is to be zeroed)
Carry
0
0
Product
0
1
1
1
1
0
1
1
0
2. test LSB of the shift registe registerr
1
Multiplier
1
Test = 1
ADD
1 Shift with carry
0
0
1
1
1
1
1
1
0 Test = 0 NOADD Shift with carry
0
0
0
1
1
1
1
1
1 Test = 1
1
0
0
1
0
1
1
1
1
0
1
0
0
1
0
1
1
1
ADD
Shift with carry
Test = 1
1
1
0
0
0
0
1
1
Sequential Shift/Add-Method
ADD
1
3. if LSB is is set
• then add multiplicand to the upper half of the shift register • else add nothing (make sure carrybit is cleared!) 4. perform perform right shift including including carry on full shift register
1
1
0
0
0
0
1
1 DONE!
Signed Multiplication Sign and magnitude representation:
• Calculate unsigned product as | p| = |x| × |y | ⇒ p0−(2 −2) = x 0−( −2) × y0−( −2) • determine sign separately as sgn( p) = sgn(x) × sgn(y ) p2 −1 = x −1 ⊕ y −1 ⇒ n
n
n
n
n
n
More difficult if 2’s complement is used:
5. repeat from from 2. as long as as multiplier multiplier part of shift register is not empty
• use 2’s complement of negative multipli-
6. after termination, termination, the shift register register (both halves!) contains the product
• sign extension is needed
Shift with carry
0
221
• Easy to implement in software
cand for summing up partial products
Example:
(−5) × (+6) = (−30)
Disadvantages:
Booth Algorithm
Multiplicand:
1. Sign-extension for negative multiplicands not applicable for negative multipliers
2. for each change from 0 to 1 or vice versa, encode ±1:
• if bit i is 0 and bit i −1 is 1 ⇒ recode to +1 • if bit i is 1 and bit i −1 is 0 ⇒ recode to −1 3. for bit 0, assume bit i = −1 with value 0 During the multiplication:
• the multiplicand is added for +1 digits • the 2’s complement is added for −1 digits
01000000 (64)
−0001 (1)
227
Booth Algorithm and Bit Pairing The Booth technique has its major advantage if 1. the operands have a large number of bits 2. multiplier contains long sequences of 1’s it has its limitations if
• the multiplier contains only small groups of 1’s or even alternating 0–1 pairs It can be enhanced by bit-pairing,
• 50% maximum number of summands • handling 0–1 pairs efficiently • additional overhead for multiplicand
Bit-Pairing of Booth Recoding Apply Booth recoding on the multiplier first, then pair bits — 1. Within a sequence: 0
0 0
2. Begin of a 1’s-sequence: 0 +1 +1
+1 −1 +1
+1
0 +2
3. End of a 1’s-sequence: 0 −1 −1
−1 +1 −1
231
−1
0 −2
s e l p m a x E g n i d o c e R h t o o B r i a P t i B
1 1 1
0 0 0
1 1 1
0 1
0 0
1 0
1 1 1
1 1 1
1 0 2
0 1
1 0
0 1
1 1 1
1 0 0
0 0 0
0 1
1 0
0 0
1 1 1
0 1 1
0 0 2
0 1
1 1
1 1
1 1 1
1 0 2
1 0 0
0 1
0 1
1 0
1 1 1
1 1 1
1 0 0
0 1
1 0
0 : r e i 1 l p i t l u 0 m e s a 1 c t s r o 0 W
1 1 1 1 1 1 1
: 0 r e i l p i t l 0 u m y 1 r a n i d r 1 O
0 0 0 1 1 0
232
0 : r e i 0 l p i t l u 0 m d o 0 o G
1 1
Conclusions for Booth Algorithm • Booth algorithm can reduce number of nonzero summands considerably
• Worst case: May double the number of non-zero summands
• Bit-pairing can reduce the number of summands further
• . . . won’t help if multiplier is optimal after conventional Booth recoding
• For the sequential shift/add hardware, bitpairing reduces the summation effort substantially, with or without Booth recoding