VLSI interview questions and answers, VLSI FAQs
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VLSI interview questions and answers VLSI interview questions and answers for freshers and experienced candidates. Also find VLSI online practice tests to fight written tests and certification exams on VLSI. In this section we have covered almost all VLSI questions that might be asked during an interview. Ask a question question
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VLSI interview questions and answers
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1. Explain:
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2. Explain cross-talk. How can it be divided?
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3. Explain charge sharing between bus and memory element.
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4. Situation - Two inverters are connected in series. The widths of pmos and nmos transistors transistors of the second inverter are 100 and 50 respectively. respectively. If the fan-out is assumed to be 3, what would be the widths of the transistors in the first inverter? 5. Explain: a.) Clock Race b.) Single Phase Clocking c.) Double Phase Clocking
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6. Explain the following effects and how would you eliminate them. a.) Hot electron effect. b.) Latchup problem
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7. Explain the following:
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a.) Channel length modulation b.) Repeaters in VLSI design c.) Tunneling problem
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8. Explain: a.) Mobility of electrons b.) Mobility of holes c.) Stage Ratio
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9. Write short notes on following: a.) PALs b.) PLAs c.) FPGAs d.) ASICs e.) PLDs 10. How does temperature affect the following? a.) T hreshold Voltage Voltage b.) Mobility 11. How would you make a XOP gate using NAND gates? 12. List the critical parameter parameter of following: a.) Latch b.) Flip-flop 14. Explain the following: a.) Leakage current b.) Domino Logic 15. Explain elextron migration. What would you do if you want to eliminate it? 16. Explain: a.) Elmore delay algorithm b.) False and multi cycle paths c.) Metastability
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VLSI interview questions and answers, VLSI FAQs
http://careerride.com/vl si-intervi ew-questions.aspx
17. Differentiate between: a.) Testing and Verification b.) Latch and Flip Flop c.) Depletion mode devices and Enhancement mode devices 18. Create the following: a.) An OR gate using NAND gate. b.) NAND gate using a 2:1 multiplexer. c.) NOR gate using a 2:1 multiplexer. 19. What are the advantages and disadvantages of Bi-CMOS process? 20. What do you mean by negative biased instability? How can you avoid it? 21. What factors would you consider while choosing a technology library for a design? 22. Explain clock skew. How will you avoid it? c23. Situation: a.) You want to equate rise and fall times in a inverter. How would you do that? b.) A resistor is added in series with the drain in a mos transistor. transistor. What would happen? c.) Suppose Vds is increased over saturation. What would happen? 24. What will be the effect of increase in th e number of contacts and vias in the i nterconnect layers? 25. Explain Explain a.) Body bias b.) Charge sharing on a bus 26. What are the various types of scaling? 27. List the various regions of operation in a mos transistor. 28. In the I-V characteristics curve, what does flat or constant saturation curve signify? 29. Can both pmos and nmos transistors pass good 1 and good 0? Explain. 30. Why is only nmos used in pass transistor logic? 31. You want to reduce charge sharing in dynamic logic. What are the different methologies methologies you can use? 32. Explain setup and hold time violations? How can they be eliminated? 33. What is the effect of i ncreasing thickness and increasing length on the resistance of a metal layer? 34. Explain the working of a bacis sram and dram. 35. How does Vdd effect delay? 36. You wan to change the voltage for less delay. What limitation you might face? How would you achieve this? 37. What is the role of a sense amplifier in SRAM? 38. You are given NAND gates and NOR gates, which of them would you take? Why? 39. Explain Noise margin in an inverter. How would you overcome it? 40. What is the effect of delay, rise and fall times with increase in load capacitance? 41. Which is more time consuming? Why? a.) Read Operations b.) Write Operations 42. Why is size of pmos transistor chosen to be close to three times of an nmos transistor? 43. Why should there be less number of CMOS transistors in a series? 44. a.) What are the substrates of pmos and nmos transistors connected connected to? b.) What would happen if the connections are interchanged with each other? 45. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is it done? Why ca n't you use just one big driver gate? Test your VLSI skills Get started now! now !
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